src/drivers/net/epic100.h

   1 #ifndef _EPIC100_H_
   2 # define _EPIC100_H_
   3
   4 #ifndef PCI_VENDOR_SMC
   5 # define PCI_VENDOR_SMC         0x10B8
   6 #endif
   7
   8 #ifndef PCI_DEVICE_SMC_EPIC100
   9 # define PCI_DEVICE_SMC_EPIC100 0x0005
  10 #endif
  11
  12 #define PCI_DEVICE_ID_NONE      0xFFFF
  13
  14 /* Offsets to registers (using SMC names). */
  15 enum epic100_registers {
  16     COMMAND= 0,         /* Control Register */
  17     INTSTAT= 4,         /* Interrupt Status */
  18     INTMASK= 8,         /* Interrupt Mask */
  19     GENCTL = 0x0C,      /* General Control */
  20     NVCTL  = 0x10,      /* Non Volatile Control */
  21     EECTL  = 0x14,      /* EEPROM Control  */
  22     TEST   = 0x1C,      /* Test register: marked as reserved (see in source code) */
  23     CRCCNT = 0x20,      /* CRC Error Counter */
  24     ALICNT = 0x24,      /* Frame Alignment Error Counter */
  25     MPCNT  = 0x28,      /* Missed Packet Counter */
  26     MMCTL  = 0x30,      /* MII Management Interface Control */
  27     MMDATA = 0x34,      /* MII Management Interface Data */
  28     MIICFG = 0x38,      /* MII Configuration */
  29     IPG    = 0x3C,      /* InterPacket Gap */
  30     LAN0   = 0x40,      /* MAC address. (0x40-0x48) */
  31     IDCHK  = 0x4C,      /* BoardID/ Checksum */
  32     MC0    = 0x50,      /* Multicast filter table. (0x50-0x5c) */
  33     RXCON  = 0x60,      /* Receive Control */
  34     TXCON  = 0x70,      /* Transmit Control */
  35     TXSTAT = 0x74,      /* Transmit Status */
  36     PRCDAR = 0x84,      /* PCI Receive Current Descriptor Address */
  37     PRSTAT = 0xA4,      /* PCI Receive DMA Status */
  38     PRCPTHR= 0xB0,      /* PCI Receive Copy Threshold */
  39     PTCDAR = 0xC4,      /* PCI Transmit Current Descriptor Address */
  40     ETHTHR = 0xDC       /* Early Transmit Threshold */
  41 };
  42
  43 /* Command register (CR_) bits */
  44 #define CR_STOP_RX              (0x00000001)
  45 #define CR_START_RX             (0x00000002)
  46 #define CR_QUEUE_TX             (0x00000004)
  47 #define CR_QUEUE_RX             (0x00000008)
  48 #define CR_NEXTFRAME            (0x00000010)
  49 #define CR_STOP_TX_DMA          (0x00000020)
  50 #define CR_STOP_RX_DMA          (0x00000040)
  51 #define CR_TX_UGO               (0x00000080)
  52
  53 /* Interrupt register bits. NI means No Interrupt generated */
  54
  55 #define INTR_RX_THR_STA         (0x00400000)    /* rx copy threshold status NI */
  56 #define INTR_RX_BUFF_EMPTY      (0x00200000)    /* rx buffers empty. NI */
  57 #define INTR_TX_IN_PROG         (0x00100000)    /* tx copy in progess. NI */
  58 #define INTR_RX_IN_PROG         (0x00080000)    /* rx copy in progress. NI */
  59 #define INTR_TXIDLE             (0x00040000)    /* tx idle. NI */
  60 #define INTR_RXIDLE             (0x00020000)    /* rx idle. NI */
  61 #define INTR_INTR_ACTIVE        (0x00010000)    /* Interrupt active. NI */
  62 #define INTR_RX_STATUS_OK       (0x00008000)    /* rx status valid. NI */
  63 #define INTR_PCI_TGT_ABT        (0x00004000)    /* PCI Target abort */
  64 #define INTR_PCI_MASTER_ABT     (0x00002000)    /* PCI Master abort */
  65 #define INTR_PCI_PARITY_ERR     (0x00001000)    /* PCI adress parity error */
  66 #define INTR_PCI_DATA_ERR       (0x00000800)    /* PCI data parity error */
  67 #define INTR_RX_THR_CROSSED     (0x00000400)    /* rx copy threshold crossed */
  68 #define INTR_CNTFULL            (0x00000200)    /* Counter overflow */
  69 #define INTR_TXUNDERRUN         (0x00000100)    /* tx underrun. */
  70 #define INTR_TXEMPTY            (0x00000080)    /* tx queue empty */
  71 #define INTR_TX_CH_COMPLETE     (0x00000040)    /* tx chain complete */
  72 #define INTR_TXDONE             (0x00000020)    /* tx complete (w or w/o err) */
  73 #define INTR_RXERROR            (0x00000010)    /* rx error (CRC) */
  74 #define INTR_RXOVERFLOW         (0x00000008)    /* rx buffer overflow */
  75 #define INTR_RX_QUEUE_EMPTY     (0x00000004)    /* rx queue empty. */
  76 #define INTR_RXHEADER           (0x00000002)    /* header copy complete */
  77 #define INTR_RXDONE             (0x00000001)    /* Receive copy complete */
  78
  79 #define INTR_CLEARINTR          (0x00007FFF)
  80 #define INTR_VALIDBITS          (0x007FFFFF)
  81 #define INTR_DISABLE            (0x00000000)
  82 #define INTR_CLEARERRS          (0x00007F18)
  83 #define INTR_ABNINTR            (INTR_CNTFULL | INTR_TXUNDERRUN | INTR_RXOVERFLOW)
  84
  85 /* General Control (GC_) bits */
  86
  87 #define GC_SOFT_RESET           (0x00000001)
  88 #define GC_INTR_ENABLE          (0x00000002)
  89 #define GC_SOFT_INTR            (0x00000004)
  90 #define GC_POWER_DOWN           (0x00000008)
  91 #define GC_ONE_COPY             (0x00000010)
  92 #define GC_BIG_ENDIAN           (0x00000020)
  93 #define GC_RX_PREEMPT_TX        (0x00000040)
  94 #define GC_TX_PREEMPT_RX        (0x00000080)
  95
  96 /*
  97  * Receive FIFO Threshold values
  98  * Control the level at which the  PCI burst state machine
  99  * begins to empty the receive FIFO. Possible values: 0-3
 100  *
 101  * 0 => 32, 1 => 64, 2 => 96 3 => 128 bytes.
 102  */
 103 #define GC_RX_FIFO_THR_32       (0x00000000)
 104 #define GC_RX_FIFO_THR_64       (0x00000100)
 105 #define GC_RX_FIFO_THR_96       (0x00000200)
 106 #define GC_RX_FIFO_THR_128      (0x00000300)
 107
 108 /* Memory Read Control (MRC_) values */
 109 #define GC_MRC_MEM_READ         (0x00000000)
 110 #define GC_MRC_READ_MULT        (0x00000400)
 111 #define GC_MRC_READ_LINE        (0x00000800)
 112
 113 #define GC_SOFTBIT0             (0x00001000)
 114 #define GC_SOFTBIT1             (0x00002000)
 115 #define GC_RESET_PHY            (0x00004000)
 116
 117 /* Definitions of the Receive Control (RC_) register bits */
 118
 119 #define RC_SAVE_ERRORED_PKT     (0x00000001)
 120 #define RC_SAVE_RUNT_FRAMES     (0x00000002)
 121 #define RC_RCV_BROADCAST        (0x00000004)
 122 #define RC_RCV_MULTICAST        (0x00000008)
 123 #define RC_RCV_INVERSE_PKT      (0x00000010)
 124 #define RC_PROMISCUOUS_MODE     (0x00000020)
 125 #define RC_MONITOR_MODE         (0x00000040)
 126 #define RC_EARLY_RCV_ENABLE     (0x00000080)
 127
 128 /* description of the rx descriptors control bits */
 129 #define RD_FRAGLIST             (0x0001)        /* Desc points to a fragment list */
 130 #define RD_LLFORM               (0x0002)        /* Frag list format */
 131 #define RD_HDR_CPY              (0x0004)        /* Desc used for header copy */
 132
 133 /* Definition of the Transmit CONTROL (TC) register bits */
 134
 135 #define TC_EARLY_TX_ENABLE      (0x00000001)
 136
 137 /* Loopback Mode (LM_) Select valuesbits */
 138 #define TC_LM_NORMAL            (0x00000000)
 139 #define TC_LM_INTERNAL          (0x00000002)
 140 #define TC_LM_EXTERNAL          (0x00000004)
 141 #define TC_LM_FULL_DPX          (0x00000006)
 142
 143 #define TX_SLOT_TIME            (0x00000078)
 144
 145 /* Bytes transferred to chip before transmission starts. */
 146 #define TX_FIFO_THRESH          128     /* Rounded down to 4 byte units. */
 147
 148 /* description of rx descriptors status bits */
 149 #define RRING_PKT_INTACT        (0x0001)
 150 #define RRING_ALIGN_ERR         (0x0002)
 151 #define RRING_CRC_ERR           (0x0004)
 152 #define RRING_MISSED_PKT        (0x0008)
 153 #define RRING_MULTICAST         (0x0010)
 154 #define RRING_BROADCAST         (0x0020)
 155 #define RRING_RECEIVER_DISABLE  (0x0040)
 156 #define RRING_STATUS_VALID      (0x1000)
 157 #define RRING_FRAGLIST_ERR      (0x2000)
 158 #define RRING_HDR_COPIED        (0x4000)
 159 #define RRING_OWN               (0x8000)
 160
 161 /* error summary */
 162 #define RRING_ERROR             (RRING_ALIGN_ERR|RRING_CRC_ERR)
 163
 164 /* description of tx descriptors status bits */
 165 #define TRING_PKT_INTACT        (0x0001)        /* pkt transmitted. */
 166 #define TRING_PKT_NONDEFER      (0x0002)        /* pkt xmitted w/o deferring */
 167 #define TRING_COLL              (0x0004)        /* pkt xmitted w collisions */
 168 #define TRING_CARR              (0x0008)        /* carrier sense lost */
 169 #define TRING_UNDERRUN          (0x0010)        /* DMA underrun */
 170 #define TRING_HB_COLL           (0x0020)        /* Collision detect Heartbeat */
 171 #define TRING_WIN_COLL          (0x0040)        /* out of window collision */
 172 #define TRING_DEFERRED          (0x0080)        /* Deferring */
 173 #define TRING_COLL_COUNT        (0x0F00)        /* collision counter (mask) */
 174 #define TRING_COLL_EXCESS       (0x1000)        /* tx aborted: excessive colls */
 175 #define TRING_OWN               (0x8000)        /* desc ownership bit */
 176
 177 /* error summary */
 178 #define TRING_ABORT     (TRING_COLL_EXCESS|TRING_WIN_COLL|TRING_UNDERRUN)
 179 #define TRING_ERROR     (TRING_DEFERRED|TRING_WIN_COLL|TRING_UNDERRUN|TRING_CARR/*|TRING_COLL*/ )
 180
 181 /* description of the tx descriptors control bits */
 182 #define TD_FRAGLIST             (0x0001)        /* Desc points to a fragment list */
 183 #define TD_LLFORM               (0x0002)        /* Frag list format */
 184 #define TD_IAF                  (0x0004)        /* Generate Interrupt after tx */
 185 #define TD_NOCRC                (0x0008)        /* No CRC generated */
 186 #define TD_LASTDESC             (0x0010)        /* Last desc for this frame */
 187
 188 #endif  /* _EPIC100_H_ */