src/drivers/net/smc9000.h

   1 /*------------------------------------------------------------------------
   2  * smc9000.h
   3  *
   4  * Copyright (C) 1998 by Daniel Engström
   5  * Copyright (C) 1996 by Erik Stahlman
   6  *
   7  * This software may be used and distributed according to the terms
   8  * of the GNU Public License, incorporated herein by reference.
   9  *
  10  * This file contains register information and access macros for
  11  * the SMC91xxx chipset.
  12  *
  13  * Information contained in this file was obtained from the SMC91C94
  14  * manual from SMC.  To get a copy, if you really want one, you can find
  15  * information under www.smsc.com in the components division.
  16  * ( this thanks to advice from Donald Becker ).
  17  *
  18  * Authors
  19  *      Daniel Engström                         <daniel.engstrom@riksnett.no>
  20  *      Erik Stahlman                           <erik@vt.edu>
  21  *
  22  * History
  23  * 96-01-06              Erik Stahlman   moved definitions here from main .c
  24  *                                       file
  25  * 96-01-19              Erik Stahlman   polished this up some, and added
  26  *                                       better error handling
  27  * 98-09-25              Daniel Engström adjusted for Etherboot
  28  * 98-09-27              Daniel Engström moved some static strings back to the
  29  *                                       main .c file
  30  * --------------------------------------------------------------------------*/
  31 #ifndef _SMC9000_H_
  32 # define _SMC9000_H_
  33
  34 /* I want some simple types */
  35 typedef unsigned char                   byte;
  36 typedef unsigned short                  word;
  37 typedef unsigned long int               dword;
  38
  39 /*---------------------------------------------------------------
  40  *
  41  * A description of the SMC registers is probably in order here,
  42  * although for details, the SMC datasheet is invaluable.
  43  *
  44  * Basically, the chip has 4 banks of registers ( 0 to 3 ), which
  45  * are accessed by writing a number into the BANK_SELECT register
  46  * ( I also use a SMC_SELECT_BANK macro for this ).
  47  *
  48  * The banks are configured so that for most purposes, bank 2 is all
  49  * that is needed for simple run time tasks.
  50  * ----------------------------------------------------------------------*/
  51
  52 /*
  53  * Bank Select Register:
  54  *
  55  *              yyyy yyyy 0000 00xx
  56  *              xx              = bank number
  57  *              yyyy yyyy       = 0x33, for identification purposes.
  58  */
  59 #define BANK_SELECT             14
  60
  61 /* BANK 0  */
  62
  63 #define TCR             0       /* transmit control register */
  64 #define TCR_ENABLE      0x0001  /* if this is 1, we can transmit */
  65 #define TCR_FDUPLX      0x0800  /* receive packets sent out */
  66 #define TCR_STP_SQET    0x1000  /* stop transmitting if Signal quality error */
  67 #define TCR_MON_CNS     0x0400  /* monitors the carrier status */
  68 #define TCR_PAD_ENABLE  0x0080  /* pads short packets to 64 bytes */
  69
  70 #define TCR_CLEAR       0       /* do NOTHING */
  71 /* the normal settings for the TCR register : */
  72 #define TCR_NORMAL      (TCR_ENABLE | TCR_PAD_ENABLE)
  73
  74
  75 #define EPH_STATUS      2
  76 #define ES_LINK_OK      0x4000  /* is the link integrity ok ? */
  77
  78 #define RCR             4
  79 #define RCR_SOFTRESET   0x8000  /* resets the chip */
  80 #define RCR_STRIP_CRC   0x200   /* strips CRC */
  81 #define RCR_ENABLE      0x100   /* IFF this is set, we can receive packets */
  82 #define RCR_ALMUL       0x4     /* receive all multicast packets */
  83 #define RCR_PROMISC     0x2     /* enable promiscuous mode */
  84
  85 /* the normal settings for the RCR register : */
  86 #define RCR_NORMAL      (RCR_STRIP_CRC | RCR_ENABLE)
  87 #define RCR_CLEAR       0x0             /* set it to a base state */
  88
  89 #define COUNTER         6
  90 #define MIR             8
  91 #define MCR             10
  92 /* 12 is reserved */
  93
  94 // Receive/Phy Control Register
  95 /* BANK 0  */
  96 #define RPC_REG         0x000A
  97 #define RPC_SPEED       0x2000  // When 1 PHY is in 100Mbps mode.
  98 #define RPC_DPLX        0x1000  // When 1 PHY is in Full-Duplex Mode
  99 #define RPC_ANEG        0x0800  // When 1 PHY is in Auto-Negotiate Mode
 100 #define RPC_LSXA_SHFT   5       // Bits to shift LS2A,LS1A,LS0A to lsb
 101 #define RPC_LSXB_SHFT   2       // Bits to get LS2B,LS1B,LS0B to lsb
 102 #define RPC_LED_100_10  (0x00)  // LED = 100Mbps OR's with 10Mbps link detect
 103 #define RPC_LED_RES     (0x01)  // LED = Reserved
 104 #define RPC_LED_10      (0x02)  // LED = 10Mbps link detect
 105 #define RPC_LED_FD      (0x03)  // LED = Full Duplex Mode
 106 #define RPC_LED_TX_RX   (0x04)  // LED = TX or RX packet occurred
 107 #define RPC_LED_100     (0x05)  // LED = 100Mbps link dectect
 108 #define RPC_LED_TX      (0x06)  // LED = TX packet occurred
 109 #define RPC_LED_RX      (0x07)  // LED = RX packet occurred
 110 #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
 111
 112 // Receive/Phy Control Register
 113 /* BANK 0  */
 114 #define RPC_REG         0x000A
 115 #define RPC_SPEED       0x2000  // When 1 PHY is in 100Mbps mode.
 116 #define RPC_DPLX        0x1000  // When 1 PHY is in Full-Duplex Mode
 117 #define RPC_ANEG        0x0800  // When 1 PHY is in Auto-Negotiate Mode
 118 #define RPC_LSXA_SHFT   5       // Bits to shift LS2A,LS1A,LS0A to lsb
 119 #define RPC_LSXB_SHFT   2       // Bits to get LS2B,LS1B,LS0B to lsb
 120 #define RPC_LED_100_10  (0x00)  // LED = 100Mbps OR's with 10Mbps link detect
 121 #define RPC_LED_RES     (0x01)  // LED = Reserved
 122 #define RPC_LED_10      (0x02)  // LED = 10Mbps link detect
 123 #define RPC_LED_FD      (0x03)  // LED = Full Duplex Mode
 124 #define RPC_LED_TX_RX   (0x04)  // LED = TX or RX packet occurred
 125 #define RPC_LED_100     (0x05)  // LED = 100Mbps link dectect
 126 #define RPC_LED_TX      (0x06)  // LED = TX packet occurred
 127 #define RPC_LED_RX      (0x07)  // LED = RX packet occurred
 128 #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
 129
 130 /* BANK 1 */
 131 #define CONFIG                  0
 132 #define CFG_AUI_SELECT          0x100
 133 #define BASE                    2
 134 #define ADDR0                   4
 135 #define ADDR1                   6
 136 #define ADDR2                   8
 137 #define GENERAL                 10
 138 #define CONTROL                 12
 139 #define CTL_POWERDOWN           0x2000
 140 #define CTL_LE_ENABLE           0x80
 141 #define CTL_CR_ENABLE           0x40
 142 #define CTL_TE_ENABLE           0x0020
 143 #define CTL_AUTO_RELEASE        0x0800
 144 #define CTL_EPROM_ACCESS        0x0003 /* high if Eprom is being read */
 145
 146 /* BANK 2 */
 147 #define MMU_CMD         0
 148 #define MC_BUSY         1       /* only readable bit in the register */
 149 #define MC_NOP          0
 150 #define MC_ALLOC        0x20    /* or with number of 256 byte packets */
 151 #define MC_RESET        0x40
 152 #define MC_REMOVE       0x60    /* remove the current rx packet */
 153 #define MC_RELEASE      0x80    /* remove and release the current rx packet */
 154 #define MC_FREEPKT      0xA0    /* Release packet in PNR register */
 155 #define MC_ENQUEUE      0xC0    /* Enqueue the packet for transmit */
 156
 157 #define PNR_ARR         2
 158 #define FIFO_PORTS      4
 159
 160 #define FP_RXEMPTY      0x8000
 161 #define FP_TXEMPTY      0x80
 162
 163 #define POINTER         6
 164 #define PTR_READ        0x2000
 165 #define PTR_RCV         0x8000
 166 #define PTR_AUTOINC     0x4000
 167 #define PTR_AUTO_INC    0x0040
 168
 169 #define DATA_1          8
 170 #define DATA_2          10
 171 #define INTERRUPT       12
 172
 173 #define INT_MASK        13
 174 #define IM_RCV_INT      0x1
 175 #define IM_TX_INT       0x2
 176 #define IM_TX_EMPTY_INT 0x4
 177 #define IM_ALLOC_INT    0x8
 178 #define IM_RX_OVRN_INT  0x10
 179 #define IM_EPH_INT      0x20
 180 #define IM_ERCV_INT     0x40 /* not on SMC9192 */
 181
 182 /* BANK 3 */
 183 #define MULTICAST1      0
 184 #define MULTICAST2      2
 185 #define MULTICAST3      4
 186 #define MULTICAST4      6
 187 #define MGMT            8
 188 #define REVISION        10 /* ( hi: chip id   low: rev # ) */
 189
 190 // Management Interface Register (MII)
 191 #define MII_REG         0x0008
 192 #define MII_MSK_CRS100  0x4000 // Disables CRS100 detection during tx half dup
 193 #define MII_MDOE        0x0008 // MII Output Enable
 194 #define MII_MCLK        0x0004 // MII Clock, pin MDCLK
 195 #define MII_MDI         0x0002 // MII Input, pin MDI
 196 #define MII_MDO         0x0001 // MII Output, pin MDO
 197
 198 /* this is NOT on SMC9192 */
 199 #define ERCV            12
 200
 201 /* Note that 9194 and 9196 have the smame chip id,
 202  * the 9196 will have revisions starting at 6 */
 203 #define CHIP_9190       3
 204 #define CHIP_9194       4
 205 #define CHIP_9195       5
 206 #define CHIP_9196       4
 207 #define CHIP_91100      7
 208 #define CHIP_91100FD    8
 209
 210 #define REV_9196        6
 211
 212 /*
 213  * Transmit status bits
 214  */
 215 #define TS_SUCCESS      0x0001
 216 #define TS_LOSTCAR      0x0400
 217 #define TS_LATCOL       0x0200
 218 #define TS_16COL        0x0010
 219
 220 /*
 221  * Receive status bits
 222  */
 223 #define RS_ALGNERR      0x8000
 224 #define RS_BADCRC       0x2000
 225 #define RS_ODDFRAME     0x1000
 226 #define RS_TOOLONG      0x0800
 227 #define RS_TOOSHORT     0x0400
 228 #define RS_MULTICAST    0x0001
 229 #define RS_ERRORS       (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
 230
 231 // Management Interface Register (MII)
 232 #define MII_REG         0x0008
 233 #define MII_MSK_CRS100  0x4000 // Disables CRS100 detection during tx half dup
 234 #define MII_MDOE        0x0008 // MII Output Enable
 235 #define MII_MCLK        0x0004 // MII Clock, pin MDCLK
 236 #define MII_MDI         0x0002 // MII Input, pin MDI
 237 #define MII_MDO         0x0001 // MII Output, pin MDO
 238
 239 // PHY Register Addresses (LAN91C111 Internal PHY)
 240
 241 // PHY Control Register
 242 #define PHY_CNTL_REG            0x00
 243 #define PHY_CNTL_RST            0x8000  // 1=PHY Reset
 244 #define PHY_CNTL_LPBK           0x4000  // 1=PHY Loopback
 245 #define PHY_CNTL_SPEED          0x2000  // 1=100Mbps, 0=10Mpbs
 246 #define PHY_CNTL_ANEG_EN        0x1000 // 1=Enable Auto negotiation
 247 #define PHY_CNTL_PDN            0x0800  // 1=PHY Power Down mode
 248 #define PHY_CNTL_MII_DIS        0x0400  // 1=MII 4 bit interface disabled
 249 #define PHY_CNTL_ANEG_RST       0x0200 // 1=Reset Auto negotiate
 250 #define PHY_CNTL_DPLX           0x0100  // 1=Full Duplex, 0=Half Duplex
 251 #define PHY_CNTL_COLTST         0x0080  // 1= MII Colision Test
 252
 253 // PHY Status Register
 254 #define PHY_STAT_REG            0x01
 255 #define PHY_STAT_CAP_T4         0x8000  // 1=100Base-T4 capable
 256 #define PHY_STAT_CAP_TXF        0x4000  // 1=100Base-X full duplex capable
 257 #define PHY_STAT_CAP_TXH        0x2000  // 1=100Base-X half duplex capable
 258 #define PHY_STAT_CAP_TF         0x1000  // 1=10Mbps full duplex capable
 259 #define PHY_STAT_CAP_TH         0x0800  // 1=10Mbps half duplex capable
 260 #define PHY_STAT_CAP_SUPR       0x0040  // 1=recv mgmt frames with not preamble
 261 #define PHY_STAT_ANEG_ACK       0x0020  // 1=ANEG has completed
 262 #define PHY_STAT_REM_FLT        0x0010  // 1=Remote Fault detected
 263 #define PHY_STAT_CAP_ANEG       0x0008  // 1=Auto negotiate capable
 264 #define PHY_STAT_LINK           0x0004  // 1=valid link
 265 #define PHY_STAT_JAB            0x0002  // 1=10Mbps jabber condition
 266 #define PHY_STAT_EXREG          0x0001  // 1=extended registers implemented
 267
 268 // PHY Identifier Registers
 269 #define PHY_ID1_REG             0x02    // PHY Identifier 1
 270 #define PHY_ID2_REG             0x03    // PHY Identifier 2
 271
 272 // PHY Auto-Negotiation Advertisement Register
 273 #define PHY_AD_REG              0x04
 274 #define PHY_AD_NP               0x8000  // 1=PHY requests exchange of Next Page
 275 #define PHY_AD_ACK              0x4000  // 1=got link code word from remote
 276 #define PHY_AD_RF               0x2000  // 1=advertise remote fault
 277 #define PHY_AD_T4               0x0200  // 1=PHY is capable of 100Base-T4
 278 #define PHY_AD_TX_FDX           0x0100  // 1=PHY is capable of 100Base-TX FDPLX
 279 #define PHY_AD_TX_HDX           0x0080  // 1=PHY is capable of 100Base-TX HDPLX
 280 #define PHY_AD_10_FDX           0x0040  // 1=PHY is capable of 10Base-T FDPLX
 281 #define PHY_AD_10_HDX           0x0020  // 1=PHY is capable of 10Base-T HDPLX
 282 #define PHY_AD_CSMA             0x0001  // 1=PHY is capable of 802.3 CMSA
 283
 284 // PHY Auto-negotiation Remote End Capability Register
 285 #define PHY_RMT_REG             0x05
 286 // Uses same bit definitions as PHY_AD_REG
 287
 288 // PHY Configuration Register 1
 289 #define PHY_CFG1_REG            0x10
 290 #define PHY_CFG1_LNKDIS         0x8000  // 1=Rx Link Detect Function disabled
 291 #define PHY_CFG1_XMTDIS         0x4000  // 1=TP Transmitter Disabled
 292 #define PHY_CFG1_XMTPDN         0x2000  // 1=TP Transmitter Powered Down
 293 #define PHY_CFG1_BYPSCR         0x0400  // 1=Bypass scrambler/descrambler
 294 #define PHY_CFG1_UNSCDS         0x0200  // 1=Unscramble Idle Reception Disable
 295 #define PHY_CFG1_EQLZR          0x0100  // 1=Rx Equalizer Disabled
 296 #define PHY_CFG1_CABLE          0x0080  // 1=STP(150ohm), 0=UTP(100ohm)
 297 #define PHY_CFG1_RLVL0          0x0040  // 1=Rx Squelch level reduced by 4.5db
 298 #define PHY_CFG1_TLVL_SHIFT     2       // Transmit Output Level Adjust
 299 #define PHY_CFG1_TLVL_MASK      0x003C
 300 #define PHY_CFG1_TRF_MASK       0x0003  // Transmitter Rise/Fall time
 301
 302
 303 // PHY Configuration Register 2
 304 #define PHY_CFG2_REG            0x11
 305 #define PHY_CFG2_APOLDIS        0x0020  // 1=Auto Polarity Correction disabled
 306 #define PHY_CFG2_JABDIS         0x0010  // 1=Jabber disabled
 307 #define PHY_CFG2_MREG           0x0008  // 1=Multiple register access (MII mgt)
 308 #define PHY_CFG2_INTMDIO        0x0004  // 1=Interrupt signaled with MDIO pulseo
 309
 310 // PHY Status Output (and Interrupt status) Register
 311 #define PHY_INT_REG             0x12    // Status Output (Interrupt Status)
 312 #define PHY_INT_INT             0x8000  // 1=bits have changed since last read
 313 #define PHY_INT_LNKFAIL         0x4000  // 1=Link Not detected
 314 #define PHY_INT_LOSSSYNC        0x2000  // 1=Descrambler has lost sync
 315 #define PHY_INT_CWRD            0x1000  // 1=Invalid 4B5B code detected on rx
 316 #define PHY_INT_SSD             0x0800  // 1=No Start Of Stream detected on rx
 317 #define PHY_INT_ESD             0x0400  // 1=No End Of Stream detected on rx
 318 #define PHY_INT_RPOL            0x0200  // 1=Reverse Polarity detected
 319 #define PHY_INT_JAB             0x0100  // 1=Jabber detected
 320 #define PHY_INT_SPDDET          0x0080  // 1=100Base-TX mode, 0=10Base-T mode
 321 #define PHY_INT_DPLXDET         0x0040  // 1=Device in Full Duplex
 322
 323 // PHY Interrupt/Status Mask Register
 324 #define PHY_MASK_REG            0x13    // Interrupt Mask
 325 // Uses the same bit definitions as PHY_INT_REG
 326
 327
 328 // PHY Register Addresses (LAN91C111 Internal PHY)
 329
 330 // PHY Control Register
 331 #define PHY_CNTL_REG            0x00
 332 #define PHY_CNTL_RST            0x8000  // 1=PHY Reset
 333 #define PHY_CNTL_LPBK           0x4000  // 1=PHY Loopback
 334 #define PHY_CNTL_SPEED          0x2000  // 1=100Mbps, 0=10Mpbs
 335 #define PHY_CNTL_ANEG_EN        0x1000 // 1=Enable Auto negotiation
 336 #define PHY_CNTL_PDN            0x0800  // 1=PHY Power Down mode
 337 #define PHY_CNTL_MII_DIS        0x0400  // 1=MII 4 bit interface disabled
 338 #define PHY_CNTL_ANEG_RST       0x0200 // 1=Reset Auto negotiate
 339 #define PHY_CNTL_DPLX           0x0100  // 1=Full Duplex, 0=Half Duplex
 340 #define PHY_CNTL_COLTST         0x0080  // 1= MII Colision Test
 341
 342 // PHY Status Register
 343 #define PHY_STAT_REG            0x01
 344 #define PHY_STAT_CAP_T4         0x8000  // 1=100Base-T4 capable
 345 #define PHY_STAT_CAP_TXF        0x4000  // 1=100Base-X full duplex capable
 346 #define PHY_STAT_CAP_TXH        0x2000  // 1=100Base-X half duplex capable
 347 #define PHY_STAT_CAP_TF         0x1000  // 1=10Mbps full duplex capable
 348 #define PHY_STAT_CAP_TH         0x0800  // 1=10Mbps half duplex capable
 349 #define PHY_STAT_CAP_SUPR       0x0040  // 1=recv mgmt frames with not preamble
 350 #define PHY_STAT_ANEG_ACK       0x0020  // 1=ANEG has completed
 351 #define PHY_STAT_REM_FLT        0x0010  // 1=Remote Fault detected
 352 #define PHY_STAT_CAP_ANEG       0x0008  // 1=Auto negotiate capable
 353 #define PHY_STAT_LINK           0x0004  // 1=valid link
 354 #define PHY_STAT_JAB            0x0002  // 1=10Mbps jabber condition
 355 #define PHY_STAT_EXREG          0x0001  // 1=extended registers implemented
 356
 357 // PHY Identifier Registers
 358 #define PHY_ID1_REG             0x02    // PHY Identifier 1
 359 #define PHY_ID2_REG             0x03    // PHY Identifier 2
 360
 361 // PHY Auto-Negotiation Advertisement Register
 362 #define PHY_AD_REG              0x04
 363 #define PHY_AD_NP               0x8000  // 1=PHY requests exchange of Next Page
 364 #define PHY_AD_ACK              0x4000  // 1=got link code word from remote
 365 #define PHY_AD_RF               0x2000  // 1=advertise remote fault
 366 #define PHY_AD_T4               0x0200  // 1=PHY is capable of 100Base-T4
 367 #define PHY_AD_TX_FDX           0x0100  // 1=PHY is capable of 100Base-TX FDPLX
 368 #define PHY_AD_TX_HDX           0x0080  // 1=PHY is capable of 100Base-TX HDPLX
 369 #define PHY_AD_10_FDX           0x0040  // 1=PHY is capable of 10Base-T FDPLX
 370 #define PHY_AD_10_HDX           0x0020  // 1=PHY is capable of 10Base-T HDPLX
 371 #define PHY_AD_CSMA             0x0001  // 1=PHY is capable of 802.3 CMSA
 372
 373 // PHY Auto-negotiation Remote End Capability Register
 374 #define PHY_RMT_REG             0x05
 375 // Uses same bit definitions as PHY_AD_REG
 376
 377 // PHY Configuration Register 1
 378 #define PHY_CFG1_REG            0x10
 379 #define PHY_CFG1_LNKDIS         0x8000  // 1=Rx Link Detect Function disabled
 380 #define PHY_CFG1_XMTDIS         0x4000  // 1=TP Transmitter Disabled
 381 #define PHY_CFG1_XMTPDN         0x2000  // 1=TP Transmitter Powered Down
 382 #define PHY_CFG1_BYPSCR         0x0400  // 1=Bypass scrambler/descrambler
 383 #define PHY_CFG1_UNSCDS         0x0200  // 1=Unscramble Idle Reception Disable
 384 #define PHY_CFG1_EQLZR          0x0100  // 1=Rx Equalizer Disabled
 385 #define PHY_CFG1_CABLE          0x0080  // 1=STP(150ohm), 0=UTP(100ohm)
 386 #define PHY_CFG1_RLVL0          0x0040  // 1=Rx Squelch level reduced by 4.5db
 387 #define PHY_CFG1_TLVL_SHIFT     2       // Transmit Output Level Adjust
 388 #define PHY_CFG1_TLVL_MASK      0x003C
 389 #define PHY_CFG1_TRF_MASK       0x0003  // Transmitter Rise/Fall time
 390
 391
 392 // PHY Configuration Register 2
 393 #define PHY_CFG2_REG            0x11
 394 #define PHY_CFG2_APOLDIS        0x0020  // 1=Auto Polarity Correction disabled
 395 #define PHY_CFG2_JABDIS         0x0010  // 1=Jabber disabled
 396 #define PHY_CFG2_MREG           0x0008  // 1=Multiple register access (MII mgt)
 397 #define PHY_CFG2_INTMDIO        0x0004  // 1=Interrupt signaled with MDIO pulseo
 398
 399 // PHY Status Output (and Interrupt status) Register
 400 #define PHY_INT_REG             0x12    // Status Output (Interrupt Status)
 401 #define PHY_INT_INT             0x8000  // 1=bits have changed since last read
 402 #define PHY_INT_LNKFAIL         0x4000  // 1=Link Not detected
 403 #define PHY_INT_LOSSSYNC        0x2000  // 1=Descrambler has lost sync
 404 #define PHY_INT_CWRD            0x1000  // 1=Invalid 4B5B code detected on rx
 405 #define PHY_INT_SSD             0x0800  // 1=No Start Of Stream detected on rx
 406 #define PHY_INT_ESD             0x0400  // 1=No End Of Stream detected on rx
 407 #define PHY_INT_RPOL            0x0200  // 1=Reverse Polarity detected
 408 #define PHY_INT_JAB             0x0100  // 1=Jabber detected
 409 #define PHY_INT_SPDDET          0x0080  // 1=100Base-TX mode, 0=10Base-T mode
 410 #define PHY_INT_DPLXDET         0x0040  // 1=Device in Full Duplex
 411
 412 // PHY Interrupt/Status Mask Register
 413 #define PHY_MASK_REG            0x13    // Interrupt Mask
 414 // Uses the same bit definitions as PHY_INT_REG
 415
 416
 417 /*-------------------------------------------------------------------------
 418  *  I define some macros to make it easier to do somewhat common
 419  * or slightly complicated, repeated tasks.
 420  --------------------------------------------------------------------------*/
 421
 422 /* select a register bank, 0 to 3  */
 423
 424 #define SMC_SELECT_BANK(x, y) { _outw( y, x + BANK_SELECT ); }
 425
 426 /* define a small delay for the reset */
 427 #define SMC_DELAY(x) { inw( x + RCR );\
 428                         inw( x + RCR );\
 429                         inw( x + RCR ); }
 430
 431
 432 #endif  /* _SMC_9000_H_ */
 433