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[uri] Special case NULL in churi()
[gpxe.git] / src / drivers / net / e1000 / e1000_82541.c
blobf1080f686033b0e9b6c5368e841c5d6b219b258e
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 FILE_LICENCE ( GPL2_OR_LATER );
30
31 /*
32 * 82541EI Gigabit Ethernet Controller
33 * 82541ER Gigabit Ethernet Controller
34 * 82541GI Gigabit Ethernet Controller
35 * 82541PI Gigabit Ethernet Controller
36 * 82547EI Gigabit Ethernet Controller
37 * 82547GI Gigabit Ethernet Controller
38 */
39
40 #include "e1000_api.h"
41
42 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw);
43 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw);
44 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw);
45 static s32 e1000_reset_hw_82541(struct e1000_hw *hw);
46 static s32 e1000_init_hw_82541(struct e1000_hw *hw);
47 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
48 u16 *duplex);
49 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw);
50 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw);
51 static s32 e1000_check_for_link_82541(struct e1000_hw *hw);
52 #if 0
53 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw);
54 #endif
55 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw,
56 bool active);
57 static s32 e1000_setup_led_82541(struct e1000_hw *hw);
58 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw);
59 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw);
60 #if 0
61 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
62 bool link_up);
63 #endif
64 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw);
65 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw);
66
67 #if 0
68 static const u16 e1000_igp_cable_length_table[] =
69 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
70 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
71 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
72 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
73 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
74 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
75 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
76 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
77 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE \
78 (sizeof(e1000_igp_cable_length_table) / \
79 sizeof(e1000_igp_cable_length_table[0]))
80 #endif
81 /**
82 * e1000_init_phy_params_82541 - Init PHY func ptrs.
83 * @hw: pointer to the HW structure
84 **/
85 static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
86 {
87 struct e1000_phy_info *phy = &hw->phy;
88 s32 ret_val = E1000_SUCCESS;
89
90 DEBUGFUNC("e1000_init_phy_params_82541");
91
92 phy->addr = 1;
93 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94 phy->reset_delay_us = 10000;
95 phy->type = e1000_phy_igp;
96
97 /* Function Pointers */
98 phy->ops.check_polarity = e1000_check_polarity_igp;
99 #if 0
100 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
101 #endif
102 #if 0
103 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541;
104 #endif
105 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
106 phy->ops.get_info = e1000_get_phy_info_igp;
107 phy->ops.read_reg = e1000_read_phy_reg_igp;
108 phy->ops.reset = e1000_phy_hw_reset_82541;
109 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541;
110 phy->ops.write_reg = e1000_write_phy_reg_igp;
111 phy->ops.power_up = e1000_power_up_phy_copper;
112 phy->ops.power_down = e1000_power_down_phy_copper_82541;
113
114 ret_val = e1000_get_phy_id(hw);
115 if (ret_val)
116 goto out;
117
118 /* Verify phy id */
119 if (phy->id != IGP01E1000_I_PHY_ID) {
120 ret_val = -E1000_ERR_PHY;
121 goto out;
122 }
123
124 out:
125 return ret_val;
126 }
127
128 /**
129 * e1000_init_nvm_params_82541 - Init NVM func ptrs.
130 * @hw: pointer to the HW structure
131 **/
132 static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw)
133 {
134 struct e1000_nvm_info *nvm = &hw->nvm;
135 s32 ret_val = E1000_SUCCESS;
136 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
137 u16 size;
138
139 DEBUGFUNC("e1000_init_nvm_params_82541");
140
141 switch (nvm->override) {
142 case e1000_nvm_override_spi_large:
143 nvm->type = e1000_nvm_eeprom_spi;
144 eecd |= E1000_EECD_ADDR_BITS;
145 break;
146 case e1000_nvm_override_spi_small:
147 nvm->type = e1000_nvm_eeprom_spi;
148 eecd &= ~E1000_EECD_ADDR_BITS;
149 break;
150 case e1000_nvm_override_microwire_large:
151 nvm->type = e1000_nvm_eeprom_microwire;
152 eecd |= E1000_EECD_SIZE;
153 break;
154 case e1000_nvm_override_microwire_small:
155 nvm->type = e1000_nvm_eeprom_microwire;
156 eecd &= ~E1000_EECD_SIZE;
157 break;
158 default:
159 nvm->type = eecd & E1000_EECD_TYPE
160 ? e1000_nvm_eeprom_spi
161 : e1000_nvm_eeprom_microwire;
162 break;
163 }
164
165 if (nvm->type == e1000_nvm_eeprom_spi) {
166 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
167 ? 16 : 8;
168 nvm->delay_usec = 1;
169 nvm->opcode_bits = 8;
170 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS)
171 ? 32 : 8;
172
173 /* Function Pointers */
174 nvm->ops.acquire = e1000_acquire_nvm_generic;
175 nvm->ops.read = e1000_read_nvm_spi;
176 nvm->ops.release = e1000_release_nvm_generic;
177 nvm->ops.update = e1000_update_nvm_checksum_generic;
178 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
179 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
180 nvm->ops.write = e1000_write_nvm_spi;
181
182 /*
183 * nvm->word_size must be discovered after the pointers
184 * are set so we can verify the size from the nvm image
185 * itself. Temporarily set it to a dummy value so the
186 * read will work.
187 */
188 nvm->word_size = 64;
189 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size);
190 if (ret_val)
191 goto out;
192 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT;
193 /*
194 * if size != 0, it can be added to a constant and become
195 * the left-shift value to set the word_size. Otherwise,
196 * word_size stays at 64.
197 */
198 if (size) {
199 size += NVM_WORD_SIZE_BASE_SHIFT_82541;
200 nvm->word_size = 1 << size;
201 }
202 } else {
203 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS)
204 ? 8 : 6;
205 nvm->delay_usec = 50;
206 nvm->opcode_bits = 3;
207 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS)
208 ? 256 : 64;
209
210 /* Function Pointers */
211 nvm->ops.acquire = e1000_acquire_nvm_generic;
212 nvm->ops.read = e1000_read_nvm_microwire;
213 nvm->ops.release = e1000_release_nvm_generic;
214 nvm->ops.update = e1000_update_nvm_checksum_generic;
215 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
216 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
217 nvm->ops.write = e1000_write_nvm_microwire;
218 }
219
220 out:
221 return ret_val;
222 }
223
224 /**
225 * e1000_init_mac_params_82541 - Init MAC func ptrs.
226 * @hw: pointer to the HW structure
227 **/
228 static s32 e1000_init_mac_params_82541(struct e1000_hw *hw)
229 {
230 struct e1000_mac_info *mac = &hw->mac;
231
232 DEBUGFUNC("e1000_init_mac_params_82541");
233
234 /* Set media type */
235 hw->phy.media_type = e1000_media_type_copper;
236 /* Set mta register count */
237 mac->mta_reg_count = 128;
238 /* Set rar entry count */
239 mac->rar_entry_count = E1000_RAR_ENTRIES;
240 /* Set if part includes ASF firmware */
241 mac->asf_firmware_present = true;
242
243 /* Function Pointers */
244
245 /* bus type/speed/width */
246 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
247 /* function id */
248 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
249 /* reset */
250 mac->ops.reset_hw = e1000_reset_hw_82541;
251 /* hw initialization */
252 mac->ops.init_hw = e1000_init_hw_82541;
253 /* link setup */
254 mac->ops.setup_link = e1000_setup_link_generic;
255 /* physical interface link setup */
256 mac->ops.setup_physical_interface = e1000_setup_copper_link_82541;
257 /* check for link */
258 mac->ops.check_for_link = e1000_check_for_link_82541;
259 /* link info */
260 mac->ops.get_link_up_info = e1000_get_link_up_info_82541;
261 /* multicast address update */
262 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
263 /* writing VFTA */
264 mac->ops.write_vfta = e1000_write_vfta_generic;
265 /* clearing VFTA */
266 mac->ops.clear_vfta = e1000_clear_vfta_generic;
267 /* setting MTA */
268 mac->ops.mta_set = e1000_mta_set_generic;
269 /* ID LED init */
270 mac->ops.id_led_init = e1000_id_led_init_generic;
271 /* setup LED */
272 mac->ops.setup_led = e1000_setup_led_82541;
273 /* cleanup LED */
274 mac->ops.cleanup_led = e1000_cleanup_led_82541;
275 /* turn on/off LED */
276 mac->ops.led_on = e1000_led_on_generic;
277 mac->ops.led_off = e1000_led_off_generic;
278 /* clear hardware counters */
279 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541;
280
281 return E1000_SUCCESS;
282 }
283
284 /**
285 * e1000_init_function_pointers_82541 - Init func ptrs.
286 * @hw: pointer to the HW structure
287 *
288 * Called to initialize all function pointers and parameters.
289 **/
290 void e1000_init_function_pointers_82541(struct e1000_hw *hw)
291 {
292 DEBUGFUNC("e1000_init_function_pointers_82541");
293
294 hw->mac.ops.init_params = e1000_init_mac_params_82541;
295 hw->nvm.ops.init_params = e1000_init_nvm_params_82541;
296 hw->phy.ops.init_params = e1000_init_phy_params_82541;
297 }
298
299 /**
300 * e1000_reset_hw_82541 - Reset hardware
301 * @hw: pointer to the HW structure
302 *
303 * This resets the hardware into a known state.
304 **/
305 static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
306 {
307 u32 ledctl, ctrl, icr, manc;
308
309 DEBUGFUNC("e1000_reset_hw_82541");
310
311 DEBUGOUT("Masking off all interrupts\n");
312 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
313
314 E1000_WRITE_REG(hw, E1000_RCTL, 0);
315 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
316 E1000_WRITE_FLUSH(hw);
317
318 /*
319 * Delay to allow any outstanding PCI transactions to complete
320 * before resetting the device.
321 */
322 msec_delay(10);
323
324 ctrl = E1000_READ_REG(hw, E1000_CTRL);
325
326 /* Must reset the Phy before resetting the MAC */
327 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
328 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
329 msec_delay(5);
330 }
331
332 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
333 switch (hw->mac.type) {
334 case e1000_82541:
335 case e1000_82541_rev_2:
336 /*
337 * These controllers can't ack the 64-bit write when
338 * issuing the reset, so we use IO-mapping as a
339 * workaround to issue the reset.
340 */
341 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
342 break;
343 default:
344 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
345 break;
346 }
347
348 /* Wait for NVM reload */
349 msec_delay(20);
350
351 /* Disable HW ARPs on ASF enabled adapters */
352 manc = E1000_READ_REG(hw, E1000_MANC);
353 manc &= ~E1000_MANC_ARP_EN;
354 E1000_WRITE_REG(hw, E1000_MANC, manc);
355
356 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
357 e1000_phy_init_script_82541(hw);
358
359 /* Configure activity LED after Phy reset */
360 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
361 ledctl &= IGP_ACTIVITY_LED_MASK;
362 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
363 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
364 }
365
366 /* Once again, mask the interrupts */
367 DEBUGOUT("Masking off all interrupts\n");
368 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
369
370 /* Clear any pending interrupt events. */
371 icr = E1000_READ_REG(hw, E1000_ICR);
372
373 return E1000_SUCCESS;
374 }
375
376 /**
377 * e1000_init_hw_82541 - Initialize hardware
378 * @hw: pointer to the HW structure
379 *
380 * This inits the hardware readying it for operation.
381 **/
382 static s32 e1000_init_hw_82541(struct e1000_hw *hw)
383 {
384 struct e1000_mac_info *mac = &hw->mac;
385 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
386 u32 i, txdctl;
387 s32 ret_val;
388
389 DEBUGFUNC("e1000_init_hw_82541");
390
391 /* Initialize identification LED */
392 ret_val = mac->ops.id_led_init(hw);
393 if (ret_val) {
394 DEBUGOUT("Error initializing identification LED\n");
395 /* This is not fatal and we should not stop init due to this */
396 }
397
398 /* Storing the Speed Power Down value for later use */
399 ret_val = hw->phy.ops.read_reg(hw,
400 IGP01E1000_GMII_FIFO,
401 &dev_spec->spd_default);
402 if (ret_val)
403 goto out;
404
405 /* Disabling VLAN filtering */
406 DEBUGOUT("Initializing the IEEE VLAN\n");
407 mac->ops.clear_vfta(hw);
408
409 /* Setup the receive address. */
410 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
411
412 /* Zero out the Multicast HASH table */
413 DEBUGOUT("Zeroing the MTA\n");
414 for (i = 0; i < mac->mta_reg_count; i++) {
415 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
416 /*
417 * Avoid back to back register writes by adding the register
418 * read (flush). This is to protect against some strange
419 * bridge configurations that may issue Memory Write Block
420 * (MWB) to our register space.
421 */
422 E1000_WRITE_FLUSH(hw);
423 }
424
425 /* Setup link and flow control */
426 ret_val = mac->ops.setup_link(hw);
427
428 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
429 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
430 E1000_TXDCTL_FULL_TX_DESC_WB;
431 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
432
433 /*
434 * Clear all of the statistics registers (clear on read). It is
435 * important that we do this after we have tried to establish link
436 * because the symbol error count will increment wildly if there
437 * is no link.
438 */
439 e1000_clear_hw_cntrs_82541(hw);
440
441 out:
442 return ret_val;
443 }
444
445 /**
446 * e1000_get_link_up_info_82541 - Report speed and duplex
447 * @hw: pointer to the HW structure
448 * @speed: pointer to speed buffer
449 * @duplex: pointer to duplex buffer
450 *
451 * Retrieve the current speed and duplex configuration.
452 **/
453 static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed,
454 u16 *duplex)
455 {
456 struct e1000_phy_info *phy = &hw->phy;
457 s32 ret_val;
458 u16 data;
459
460 DEBUGFUNC("e1000_get_link_up_info_82541");
461
462 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex);
463 if (ret_val)
464 goto out;
465
466 if (!phy->speed_downgraded)
467 goto out;
468
469 /*
470 * IGP01 PHY may advertise full duplex operation after speed
471 * downgrade even if it is operating at half duplex.
472 * Here we set the duplex settings to match the duplex in the
473 * link partner's capabilities.
474 */
475 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data);
476 if (ret_val)
477 goto out;
478
479 if (!(data & NWAY_ER_LP_NWAY_CAPS)) {
480 *duplex = HALF_DUPLEX;
481 } else {
482 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data);
483 if (ret_val)
484 goto out;
485
486 if (*speed == SPEED_100) {
487 if (!(data & NWAY_LPAR_100TX_FD_CAPS))
488 *duplex = HALF_DUPLEX;
489 } else if (*speed == SPEED_10) {
490 if (!(data & NWAY_LPAR_10T_FD_CAPS))
491 *duplex = HALF_DUPLEX;
492 }
493 }
494
495 out:
496 return ret_val;
497 }
498
499 /**
500 * e1000_phy_hw_reset_82541 - PHY hardware reset
501 * @hw: pointer to the HW structure
502 *
503 * Verify the reset block is not blocking us from resetting. Acquire
504 * semaphore (if necessary) and read/set/write the device control reset
505 * bit in the PHY. Wait the appropriate delay time for the device to
506 * reset and release the semaphore (if necessary).
507 **/
508 static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw)
509 {
510 s32 ret_val;
511 u32 ledctl;
512
513 DEBUGFUNC("e1000_phy_hw_reset_82541");
514
515 ret_val = e1000_phy_hw_reset_generic(hw);
516 if (ret_val)
517 goto out;
518
519 e1000_phy_init_script_82541(hw);
520
521 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
522 /* Configure activity LED after PHY reset */
523 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
524 ledctl &= IGP_ACTIVITY_LED_MASK;
525 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
526 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
527 }
528
529 out:
530 return ret_val;
531 }
532
533 /**
534 * e1000_setup_copper_link_82541 - Configure copper link settings
535 * @hw: pointer to the HW structure
536 *
537 * Calls the appropriate function to configure the link for auto-neg or forced
538 * speed and duplex. Then we check for link, once link is established calls
539 * to configure collision distance and flow control are called. If link is
540 * not established, we return -E1000_ERR_PHY (-2).
541 **/
542 static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw)
543 {
544 struct e1000_phy_info *phy = &hw->phy;
545 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
546 s32 ret_val;
547 u32 ctrl, ledctl;
548
549 DEBUGFUNC("e1000_setup_copper_link_82541");
550
551 ctrl = E1000_READ_REG(hw, E1000_CTRL);
552 ctrl |= E1000_CTRL_SLU;
553 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
554 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
555
556 hw->phy.reset_disable = false;
557
558 /* Earlier revs of the IGP phy require us to force MDI. */
559 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) {
560 dev_spec->dsp_config = e1000_dsp_config_disabled;
561 phy->mdix = 1;
562 } else {
563 dev_spec->dsp_config = e1000_dsp_config_enabled;
564 }
565
566 ret_val = e1000_copper_link_setup_igp(hw);
567 if (ret_val)
568 goto out;
569
570 if (hw->mac.autoneg) {
571 if (dev_spec->ffe_config == e1000_ffe_config_active)
572 dev_spec->ffe_config = e1000_ffe_config_enabled;
573 }
574
575 /* Configure activity LED after Phy reset */
576 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
577 ledctl &= IGP_ACTIVITY_LED_MASK;
578 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
579 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
580
581 ret_val = e1000_setup_copper_link_generic(hw);
582
583 out:
584 return ret_val;
585 }
586
587 /**
588 * e1000_check_for_link_82541 - Check/Store link connection
589 * @hw: pointer to the HW structure
590 *
591 * This checks the link condition of the adapter and stores the
592 * results in the hw->mac structure.
593 **/
594 static s32 e1000_check_for_link_82541(struct e1000_hw *hw)
595 {
596 struct e1000_mac_info *mac = &hw->mac;
597 s32 ret_val;
598 bool link;
599
600 DEBUGFUNC("e1000_check_for_link_82541");
601
602 /*
603 * We only want to go out to the PHY registers to see if Auto-Neg
604 * has completed and/or if our link status has changed. The
605 * get_link_status flag is set upon receiving a Link Status
606 * Change or Rx Sequence Error interrupt.
607 */
608 if (!mac->get_link_status) {
609 ret_val = E1000_SUCCESS;
610 goto out;
611 }
612
613 /*
614 * First we want to see if the MII Status Register reports
615 * link. If so, then we want to get the current speed/duplex
616 * of the PHY.
617 */
618 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
619 if (ret_val)
620 goto out;
621
622 if (!link) {
623 ret_val = -E1000_ERR_CONFIG;
624 #if 0
625 ret_val = e1000_config_dsp_after_link_change_82541(hw, false);
626 #endif
627 goto out; /* No link detected */
628 }
629
630 mac->get_link_status = false;
631
632 /*
633 * Check if there was DownShift, must be checked
634 * immediately after link-up
635 */
636 e1000_check_downshift_generic(hw);
637
638 /*
639 * If we are forcing speed/duplex, then we simply return since
640 * we have already determined whether we have link or not.
641 */
642 if (!mac->autoneg) {
643 ret_val = -E1000_ERR_CONFIG;
644 goto out;
645 }
646
647 #if 0
648 ret_val = e1000_config_dsp_after_link_change_82541(hw, true);
649 #endif
650
651 /*
652 * Auto-Neg is enabled. Auto Speed Detection takes care
653 * of MAC speed/duplex configuration. So we only need to
654 * configure Collision Distance in the MAC.
655 */
656 e1000_config_collision_dist_generic(hw);
657
658 /*
659 * Configure Flow Control now that Auto-Neg has completed.
660 * First, we need to restore the desired flow control
661 * settings because we may have had to re-autoneg with a
662 * different link partner.
663 */
664 ret_val = e1000_config_fc_after_link_up_generic(hw);
665 if (ret_val) {
666 DEBUGOUT("Error configuring flow control\n");
667 }
668
669 out:
670 return ret_val;
671 }
672
673 #if 0
674 /**
675 * e1000_config_dsp_after_link_change_82541 - Config DSP after link
676 * @hw: pointer to the HW structure
677 * @link_up: boolean flag for link up status
678 *
679 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS
680 * at any other case.
681 *
682 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
683 * gigabit link is achieved to improve link quality.
684 **/
685 static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw,
686 bool link_up)
687 {
688 struct e1000_phy_info *phy = &hw->phy;
689 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
690 s32 ret_val;
691 u32 idle_errs = 0;
692 u16 phy_data, phy_saved_data, speed, duplex, i;
693 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
694 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
695 {IGP01E1000_PHY_AGC_PARAM_A,
696 IGP01E1000_PHY_AGC_PARAM_B,
697 IGP01E1000_PHY_AGC_PARAM_C,
698 IGP01E1000_PHY_AGC_PARAM_D};
699
700 DEBUGFUNC("e1000_config_dsp_after_link_change_82541");
701
702 if (link_up) {
703 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
704 if (ret_val) {
705 DEBUGOUT("Error getting link speed and duplex\n");
706 goto out;
707 }
708
709 if (speed != SPEED_1000) {
710 ret_val = E1000_SUCCESS;
711 goto out;
712 }
713
714 #if 0
715 ret_val = phy->ops.get_cable_length(hw);
716 #endif
717 ret_val = -E1000_ERR_CONFIG;
718 if (ret_val)
719 goto out;
720
721 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) &&
722 phy->min_cable_length >= 50) {
723
724 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
725 ret_val = phy->ops.read_reg(hw,
726 dsp_reg_array[i],
727 &phy_data);
728 if (ret_val)
729 goto out;
730
731 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
732
733 ret_val = phy->ops.write_reg(hw,
734 dsp_reg_array[i],
735 phy_data);
736 if (ret_val)
737 goto out;
738 }
739 dev_spec->dsp_config = e1000_dsp_config_activated;
740 }
741
742 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) ||
743 (phy->min_cable_length >= 50)) {
744 ret_val = E1000_SUCCESS;
745 goto out;
746 }
747
748 /* clear previous idle error counts */
749 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
750 if (ret_val)
751 goto out;
752
753 for (i = 0; i < ffe_idle_err_timeout; i++) {
754 usec_delay(1000);
755 ret_val = phy->ops.read_reg(hw,
756 PHY_1000T_STATUS,
757 &phy_data);
758 if (ret_val)
759 goto out;
760
761 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
762 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
763 dev_spec->ffe_config = e1000_ffe_config_active;
764
765 ret_val = phy->ops.write_reg(hw,
766 IGP01E1000_PHY_DSP_FFE,
767 IGP01E1000_PHY_DSP_FFE_CM_CP);
768 if (ret_val)
769 goto out;
770 break;
771 }
772
773 if (idle_errs)
774 ffe_idle_err_timeout =
775 FFE_IDLE_ERR_COUNT_TIMEOUT_100;
776 }
777 } else {
778 if (dev_spec->dsp_config == e1000_dsp_config_activated) {
779 /*
780 * Save off the current value of register 0x2F5B
781 * to be restored at the end of the routines.
782 */
783 ret_val = phy->ops.read_reg(hw,
784 0x2F5B,
785 &phy_saved_data);
786 if (ret_val)
787 goto out;
788
789 /* Disable the PHY transmitter */
790 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
791 if (ret_val)
792 goto out;
793
794 msec_delay_irq(20);
795
796 ret_val = phy->ops.write_reg(hw,
797 0x0000,
798 IGP01E1000_IEEE_FORCE_GIG);
799 if (ret_val)
800 goto out;
801 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
802 ret_val = phy->ops.read_reg(hw,
803 dsp_reg_array[i],
804 &phy_data);
805 if (ret_val)
806 goto out;
807
808 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
809 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
810
811 ret_val = phy->ops.write_reg(hw,
812 dsp_reg_array[i],
813 phy_data);
814 if (ret_val)
815 goto out;
816 }
817
818 ret_val = phy->ops.write_reg(hw,
819 0x0000,
820 IGP01E1000_IEEE_RESTART_AUTONEG);
821 if (ret_val)
822 goto out;
823
824 msec_delay_irq(20);
825
826 /* Now enable the transmitter */
827 ret_val = phy->ops.write_reg(hw,
828 0x2F5B,
829 phy_saved_data);
830 if (ret_val)
831 goto out;
832
833 dev_spec->dsp_config = e1000_dsp_config_enabled;
834 }
835
836 if (dev_spec->ffe_config != e1000_ffe_config_active) {
837 ret_val = E1000_SUCCESS;
838 goto out;
839 }
840
841 /*
842 * Save off the current value of register 0x2F5B
843 * to be restored at the end of the routines.
844 */
845 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data);
846 if (ret_val)
847 goto out;
848
849 /* Disable the PHY transmitter */
850 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003);
851 if (ret_val)
852 goto out;
853
854 msec_delay_irq(20);
855
856 ret_val = phy->ops.write_reg(hw,
857 0x0000,
858 IGP01E1000_IEEE_FORCE_GIG);
859 if (ret_val)
860 goto out;
861
862 ret_val = phy->ops.write_reg(hw,
863 IGP01E1000_PHY_DSP_FFE,
864 IGP01E1000_PHY_DSP_FFE_DEFAULT);
865 if (ret_val)
866 goto out;
867
868 ret_val = phy->ops.write_reg(hw,
869 0x0000,
870 IGP01E1000_IEEE_RESTART_AUTONEG);
871 if (ret_val)
872 goto out;
873
874 msec_delay_irq(20);
875
876 /* Now enable the transmitter */
877 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data);
878
879 if (ret_val)
880 goto out;
881
882 dev_spec->ffe_config = e1000_ffe_config_enabled;
883 }
884
885 out:
886 return ret_val;
887 }
888 #endif
889
890 #if 0
891 /**
892 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY
893 * @hw: pointer to the HW structure
894 *
895 * The automatic gain control (agc) normalizes the amplitude of the
896 * received signal, adjusting for the attenuation produced by the
897 * cable. By reading the AGC registers, which represent the
898 * combination of coarse and fine gain value, the value can be put
899 * into a lookup table to obtain the approximate cable length
900 * for each channel.
901 **/
902 static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw)
903 {
904 struct e1000_phy_info *phy = &hw->phy;
905 s32 ret_val = E1000_SUCCESS;
906 u16 i, data;
907 u16 cur_agc_value, agc_value = 0;
908 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
909 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
910 {IGP01E1000_PHY_AGC_A,
911 IGP01E1000_PHY_AGC_B,
912 IGP01E1000_PHY_AGC_C,
913 IGP01E1000_PHY_AGC_D};
914
915 DEBUGFUNC("e1000_get_cable_length_igp_82541");
916
917 /* Read the AGC registers for all channels */
918 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
919 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data);
920 if (ret_val)
921 goto out;
922
923 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT;
924
925 /* Bounds checking */
926 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) ||
927 (cur_agc_value == 0)) {
928 ret_val = -E1000_ERR_PHY;
929 goto out;
930 }
931
932 agc_value += cur_agc_value;
933
934 if (min_agc_value > cur_agc_value)
935 min_agc_value = cur_agc_value;
936 }
937
938 /* Remove the minimal AGC result for length < 50m */
939 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) {
940 agc_value -= min_agc_value;
941 /* Average the three remaining channels for the length. */
942 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
943 } else {
944 /* Average the channels for the length. */
945 agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
946 }
947
948 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] >
949 IGP01E1000_AGC_RANGE)
950 ? (e1000_igp_cable_length_table[agc_value] -
951 IGP01E1000_AGC_RANGE)
952 : 0;
953 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] +
954 IGP01E1000_AGC_RANGE;
955
956 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
957
958 out:
959 return ret_val;
960 }
961 #endif
962
963 /**
964 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3
965 * @hw: pointer to the HW structure
966 * @active: boolean used to enable/disable lplu
967 *
968 * Success returns 0, Failure returns 1
969 *
970 * The low power link up (lplu) state is set to the power management level D3
971 * and SmartSpeed is disabled when active is true, else clear lplu for D3
972 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
973 * is used during Dx states where the power conservation is most important.
974 * During driver activity, SmartSpeed should be enabled so performance is
975 * maintained.
976 **/
977 static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active)
978 {
979 struct e1000_phy_info *phy = &hw->phy;
980 s32 ret_val;
981 u16 data;
982
983 DEBUGFUNC("e1000_set_d3_lplu_state_82541");
984
985 switch (hw->mac.type) {
986 case e1000_82541_rev_2:
987 case e1000_82547_rev_2:
988 break;
989 default:
990 ret_val = e1000_set_d3_lplu_state_generic(hw, active);
991 goto out;
992 break;
993 }
994
995 ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data);
996 if (ret_val)
997 goto out;
998
999 if (!active) {
1000 data &= ~IGP01E1000_GMII_FLEX_SPD;
1001 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1002 if (ret_val)
1003 goto out;
1004
1005 /*
1006 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1007 * during Dx states where the power conservation is most
1008 * important. During driver activity we should enable
1009 * SmartSpeed, so performance is maintained.
1010 */
1011 if (phy->smart_speed == e1000_smart_speed_on) {
1012 ret_val = phy->ops.read_reg(hw,
1013 IGP01E1000_PHY_PORT_CONFIG,
1014 &data);
1015 if (ret_val)
1016 goto out;
1017
1018 data |= IGP01E1000_PSCFR_SMART_SPEED;
1019 ret_val = phy->ops.write_reg(hw,
1020 IGP01E1000_PHY_PORT_CONFIG,
1021 data);
1022 if (ret_val)
1023 goto out;
1024 } else if (phy->smart_speed == e1000_smart_speed_off) {
1025 ret_val = phy->ops.read_reg(hw,
1026 IGP01E1000_PHY_PORT_CONFIG,
1027 &data);
1028 if (ret_val)
1029 goto out;
1030
1031 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1032 ret_val = phy->ops.write_reg(hw,
1033 IGP01E1000_PHY_PORT_CONFIG,
1034 data);
1035 if (ret_val)
1036 goto out;
1037 }
1038 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1039 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1040 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1041 data |= IGP01E1000_GMII_FLEX_SPD;
1042 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data);
1043 if (ret_val)
1044 goto out;
1045
1046 /* When LPLU is enabled, we should disable SmartSpeed */
1047 ret_val = phy->ops.read_reg(hw,
1048 IGP01E1000_PHY_PORT_CONFIG,
1049 &data);
1050 if (ret_val)
1051 goto out;
1052
1053 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1054 ret_val = phy->ops.write_reg(hw,
1055 IGP01E1000_PHY_PORT_CONFIG,
1056 data);
1057 }
1058
1059 out:
1060 return ret_val;
1061 }
1062
1063 /**
1064 * e1000_setup_led_82541 - Configures SW controllable LED
1065 * @hw: pointer to the HW structure
1066 *
1067 * This prepares the SW controllable LED for use and saves the current state
1068 * of the LED so it can be later restored.
1069 **/
1070 static s32 e1000_setup_led_82541(struct e1000_hw *hw __unused)
1071 {
1072 #if 0
1073 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1074 s32 ret_val;
1075
1076 DEBUGFUNC("e1000_setup_led_82541");
1077
1078 ret_val = hw->phy.ops.read_reg(hw,
1079 IGP01E1000_GMII_FIFO,
1080 &dev_spec->spd_default);
1081 if (ret_val)
1082 goto out;
1083
1084 ret_val = hw->phy.ops.write_reg(hw,
1085 IGP01E1000_GMII_FIFO,
1086 (u16)(dev_spec->spd_default &
1087 ~IGP01E1000_GMII_SPD));
1088 if (ret_val)
1089 goto out;
1090
1091 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1092
1093 out:
1094 return ret_val;
1095 #endif
1096 return 0;
1097 }
1098
1099 /**
1100 * e1000_cleanup_led_82541 - Set LED config to default operation
1101 * @hw: pointer to the HW structure
1102 *
1103 * Remove the current LED configuration and set the LED configuration
1104 * to the default value, saved from the EEPROM.
1105 **/
1106 static s32 e1000_cleanup_led_82541(struct e1000_hw *hw __unused)
1107 {
1108 #if 0
1109 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1110 s32 ret_val;
1111
1112 DEBUGFUNC("e1000_cleanup_led_82541");
1113
1114 ret_val = hw->phy.ops.write_reg(hw,
1115 IGP01E1000_GMII_FIFO,
1116 dev_spec->spd_default);
1117 if (ret_val)
1118 goto out;
1119
1120 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1121
1122 out:
1123 return ret_val;
1124 #endif
1125 return 0;
1126 }
1127
1128 /**
1129 * e1000_phy_init_script_82541 - Initialize GbE PHY
1130 * @hw: pointer to the HW structure
1131 *
1132 * Initializes the IGP PHY.
1133 **/
1134 static s32 e1000_phy_init_script_82541(struct e1000_hw *hw)
1135 {
1136 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541;
1137 u32 ret_val;
1138 u16 phy_saved_data;
1139
1140 DEBUGFUNC("e1000_phy_init_script_82541");
1141
1142 if (!dev_spec->phy_init_script) {
1143 ret_val = E1000_SUCCESS;
1144 goto out;
1145 }
1146
1147 /* Delay after phy reset to enable NVM configuration to load */
1148 msec_delay(20);
1149
1150 /*
1151 * Save off the current value of register 0x2F5B to be restored at
1152 * the end of this routine.
1153 */
1154 ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data);
1155
1156 /* Disabled the PHY transmitter */
1157 hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003);
1158
1159 msec_delay(20);
1160
1161 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
1162
1163 msec_delay(5);
1164
1165 switch (hw->mac.type) {
1166 case e1000_82541:
1167 case e1000_82547:
1168 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001);
1169
1170 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21);
1171
1172 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018);
1173
1174 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600);
1175
1176 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014);
1177
1178 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C);
1179
1180 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003);
1181
1182 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F);
1183
1184 hw->phy.ops.write_reg(hw, 0x2010, 0x0008);
1185 break;
1186 case e1000_82541_rev_2:
1187 case e1000_82547_rev_2:
1188 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099);
1189 break;
1190 default:
1191 break;
1192 }
1193
1194 hw->phy.ops.write_reg(hw, 0x0000, 0x3300);
1195
1196 msec_delay(20);
1197
1198 /* Now enable the transmitter */
1199 hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data);
1200
1201 if (hw->mac.type == e1000_82547) {
1202 u16 fused, fine, coarse;
1203
1204 /* Move to analog registers page */
1205 hw->phy.ops.read_reg(hw,
1206 IGP01E1000_ANALOG_SPARE_FUSE_STATUS,
1207 &fused);
1208
1209 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
1210 hw->phy.ops.read_reg(hw,
1211 IGP01E1000_ANALOG_FUSE_STATUS,
1212 &fused);
1213
1214 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
1215 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
1216
1217 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
1218 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
1219 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
1220 } else if (coarse ==
1221 IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
1222 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
1223
1224 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
1225 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
1226 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
1227
1228 hw->phy.ops.write_reg(hw,
1229 IGP01E1000_ANALOG_FUSE_CONTROL,
1230 fused);
1231 hw->phy.ops.write_reg(hw,
1232 IGP01E1000_ANALOG_FUSE_BYPASS,
1233 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
1234 }
1235 }
1236
1237 out:
1238 return ret_val;
1239 }
1240
1241 /**
1242 * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down
1243 * @hw: pointer to the HW structure
1244 *
1245 * In the case of a PHY power down to save power, or to turn off link during a
1246 * driver unload, or wake on lan is not enabled, remove the link.
1247 **/
1248 static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw)
1249 {
1250 /* If the management interface is not enabled, then power down */
1251 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
1252 e1000_power_down_phy_copper(hw);
1253
1254 return;
1255 }
1256
1257 /**
1258 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters
1259 * @hw: pointer to the HW structure
1260 *
1261 * Clears the hardware counters by reading the counter registers.
1262 **/
1263 static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw)
1264 {
1265 DEBUGFUNC("e1000_clear_hw_cntrs_82541");
1266
1267 e1000_clear_hw_cntrs_base_generic(hw);
1268
1269 #if 0
1270 E1000_READ_REG(hw, E1000_PRC64);
1271 E1000_READ_REG(hw, E1000_PRC127);
1272 E1000_READ_REG(hw, E1000_PRC255);
1273 E1000_READ_REG(hw, E1000_PRC511);
1274 E1000_READ_REG(hw, E1000_PRC1023);
1275 E1000_READ_REG(hw, E1000_PRC1522);
1276 E1000_READ_REG(hw, E1000_PTC64);
1277 E1000_READ_REG(hw, E1000_PTC127);
1278 E1000_READ_REG(hw, E1000_PTC255);
1279 E1000_READ_REG(hw, E1000_PTC511);
1280 E1000_READ_REG(hw, E1000_PTC1023);
1281 E1000_READ_REG(hw, E1000_PTC1522);
1282
1283 E1000_READ_REG(hw, E1000_ALGNERRC);
1284 E1000_READ_REG(hw, E1000_RXERRC);
1285 E1000_READ_REG(hw, E1000_TNCRS);
1286 E1000_READ_REG(hw, E1000_CEXTERR);
1287 E1000_READ_REG(hw, E1000_TSCTC);
1288 E1000_READ_REG(hw, E1000_TSCTFC);
1289
1290 E1000_READ_REG(hw, E1000_MGTPRC);
1291 E1000_READ_REG(hw, E1000_MGTPDC);
1292 E1000_READ_REG(hw, E1000_MGTPTC);
1293 #endif
1294 }
1295
1296 static struct pci_device_id e1000_82541_nics[] = {
1297 PCI_ROM(0x8086, 0x1013, "E1000_DEV_ID_82541EI", "E1000_DEV_ID_82541EI", e1000_82541),
1298 PCI_ROM(0x8086, 0x1014, "E1000_DEV_ID_82541ER_LOM", "E1000_DEV_ID_82541ER_LOM", e1000_82541),
1299 PCI_ROM(0x8086, 0x1018, "E1000_DEV_ID_82541EI_MOBILE", "E1000_DEV_ID_82541EI_MOBILE", e1000_82541),
1300 PCI_ROM(0x8086, 0x1019, "E1000_DEV_ID_82547EI", "E1000_DEV_ID_82547EI", e1000_82547),
1301 PCI_ROM(0x8086, 0x101A, "E1000_DEV_ID_82547EI_MOBILE", "E1000_DEV_ID_82547EI_MOBILE", e1000_82547),
1302 PCI_ROM(0x8086, 0x1075, "E1000_DEV_ID_82547GI", "E1000_DEV_ID_82547GI", e1000_82547_rev_2),
1303 PCI_ROM(0x8086, 0x1076, "E1000_DEV_ID_82541GI", "E1000_DEV_ID_82541GI", e1000_82541_rev_2),
1304 PCI_ROM(0x8086, 0x1077, "E1000_DEV_ID_82541GI_MOBILE", "E1000_DEV_ID_82541GI_MOBILE", e1000_82541_rev_2),
1305 PCI_ROM(0x8086, 0x1078, "E1000_DEV_ID_82541ER", "E1000_DEV_ID_82541ER", e1000_82541_rev_2),
1306 PCI_ROM(0x8086, 0x107C, "E1000_DEV_ID_82541GI_LF", "E1000_DEV_ID_82541GI_LF", e1000_82541_rev_2),
1307 };
1308
1309 struct pci_driver e1000_82541_driver __pci_driver = {
1310 .ids = e1000_82541_nics,
1311 .id_count = (sizeof (e1000_82541_nics) / sizeof (e1000_82541_nics[0])),
1312 .probe = e1000_probe,
1313 .remove = e1000_remove,
1314 };
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