src/drivers/net/e1000/e1000_82542.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 FILE_LICENCE ( GPL2_OR_LATER );
  30
  31 /*
  32  * 82542 Gigabit Ethernet Controller
  33  */
  34
  35 #include "e1000_api.h"
  36
  37 static s32  e1000_init_phy_params_82542(struct e1000_hw *hw);
  38 static s32  e1000_init_nvm_params_82542(struct e1000_hw *hw);
  39 static s32  e1000_init_mac_params_82542(struct e1000_hw *hw);
  40 static s32  e1000_get_bus_info_82542(struct e1000_hw *hw);
  41 static s32  e1000_reset_hw_82542(struct e1000_hw *hw);
  42 static s32  e1000_init_hw_82542(struct e1000_hw *hw);
  43 static s32  e1000_setup_link_82542(struct e1000_hw *hw);
  44 static s32  e1000_led_on_82542(struct e1000_hw *hw);
  45 static s32  e1000_led_off_82542(struct e1000_hw *hw);
  46 static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
  47 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
  48
  49 /**
  50  *  e1000_init_phy_params_82542 - Init PHY func ptrs.
  51  *  @hw: pointer to the HW structure
  52  **/
  53 static s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
  54 {
  55         struct e1000_phy_info *phy = &hw->phy;
  56         s32 ret_val = E1000_SUCCESS;
  57
  58         DEBUGFUNC("e1000_init_phy_params_82542");
  59
  60         phy->type               = e1000_phy_none;
  61
  62         return ret_val;
  63 }
  64
  65 /**
  66  *  e1000_init_nvm_params_82542 - Init NVM func ptrs.
  67  *  @hw: pointer to the HW structure
  68  **/
  69 static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
  70 {
  71         struct e1000_nvm_info *nvm = &hw->nvm;
  72
  73         DEBUGFUNC("e1000_init_nvm_params_82542");
  74
  75         nvm->address_bits       =  6;
  76         nvm->delay_usec         = 50;
  77         nvm->opcode_bits        =  3;
  78         nvm->type               = e1000_nvm_eeprom_microwire;
  79         nvm->word_size          = 64;
  80
  81         /* Function Pointers */
  82         nvm->ops.read           = e1000_read_nvm_microwire;
  83         nvm->ops.release        = e1000_stop_nvm;
  84         nvm->ops.write          = e1000_write_nvm_microwire;
  85         nvm->ops.update         = e1000_update_nvm_checksum_generic;
  86         nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
  87
  88         return E1000_SUCCESS;
  89 }
  90
  91 /**
  92  *  e1000_init_mac_params_82542 - Init MAC func ptrs.
  93  *  @hw: pointer to the HW structure
  94  **/
  95 static s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
  96 {
  97         struct e1000_mac_info *mac = &hw->mac;
  98
  99         DEBUGFUNC("e1000_init_mac_params_82542");
 100
 101         /* Set media type */
 102         hw->phy.media_type = e1000_media_type_fiber;
 103
 104         /* Set mta register count */
 105         mac->mta_reg_count = 128;
 106         /* Set rar entry count */
 107         mac->rar_entry_count = E1000_RAR_ENTRIES;
 108
 109         /* Function pointers */
 110
 111         /* bus type/speed/width */
 112         mac->ops.get_bus_info = e1000_get_bus_info_82542;
 113         /* function id */
 114         mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
 115         /* reset */
 116         mac->ops.reset_hw = e1000_reset_hw_82542;
 117         /* hw initialization */
 118         mac->ops.init_hw = e1000_init_hw_82542;
 119         /* link setup */
 120         mac->ops.setup_link = e1000_setup_link_82542;
 121         /* phy/fiber/serdes setup */
 122         mac->ops.setup_physical_interface = e1000_setup_fiber_serdes_link_generic;
 123         /* check for link */
 124         mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 125         /* multicast address update */
 126         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
 127         /* writing VFTA */
 128         mac->ops.write_vfta = e1000_write_vfta_generic;
 129         /* clearing VFTA */
 130         mac->ops.clear_vfta = e1000_clear_vfta_generic;
 131         /* setting MTA */
 132         mac->ops.mta_set = e1000_mta_set_generic;
 133         /* set RAR */
 134         mac->ops.rar_set = e1000_rar_set_82542;
 135         /* turn on/off LED */
 136         mac->ops.led_on = e1000_led_on_82542;
 137         mac->ops.led_off = e1000_led_off_82542;
 138         /* clear hardware counters */
 139         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;
 140         /* link info */
 141         mac->ops.get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes_generic;
 142
 143         return E1000_SUCCESS;
 144 }
 145
 146 /**
 147  *  e1000_init_function_pointers_82542 - Init func ptrs.
 148  *  @hw: pointer to the HW structure
 149  *
 150  *  Called to initialize all function pointers and parameters.
 151  **/
 152 void e1000_init_function_pointers_82542(struct e1000_hw *hw)
 153 {
 154         DEBUGFUNC("e1000_init_function_pointers_82542");
 155
 156         hw->mac.ops.init_params = e1000_init_mac_params_82542;
 157         hw->nvm.ops.init_params = e1000_init_nvm_params_82542;
 158         hw->phy.ops.init_params = e1000_init_phy_params_82542;
 159 }
 160
 161 /**
 162  *  e1000_get_bus_info_82542 - Obtain bus information for adapter
 163  *  @hw: pointer to the HW structure
 164  *
 165  *  This will obtain information about the HW bus for which the
 166  *  adapter is attached and stores it in the hw structure.
 167  **/
 168 static s32 e1000_get_bus_info_82542(struct e1000_hw *hw)
 169 {
 170         DEBUGFUNC("e1000_get_bus_info_82542");
 171
 172         hw->bus.type = e1000_bus_type_pci;
 173         hw->bus.speed = e1000_bus_speed_unknown;
 174         hw->bus.width = e1000_bus_width_unknown;
 175
 176         return E1000_SUCCESS;
 177 }
 178
 179 /**
 180  *  e1000_reset_hw_82542 - Reset hardware
 181  *  @hw: pointer to the HW structure
 182  *
 183  *  This resets the hardware into a known state.
 184  **/
 185 static s32 e1000_reset_hw_82542(struct e1000_hw *hw)
 186 {
 187         struct e1000_bus_info *bus = &hw->bus;
 188         s32 ret_val = E1000_SUCCESS;
 189         u32 ctrl, icr;
 190
 191         DEBUGFUNC("e1000_reset_hw_82542");
 192
 193         if (hw->revision_id == E1000_REVISION_2) {
 194                 DEBUGOUT("Disabling MWI on 82542 rev 2\n");
 195                 e1000_pci_clear_mwi(hw);
 196         }
 197
 198         DEBUGOUT("Masking off all interrupts\n");
 199         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 200
 201         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 202         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 203         E1000_WRITE_FLUSH(hw);
 204
 205         /*
 206          * Delay to allow any outstanding PCI transactions to complete before
 207          * resetting the device
 208          */
 209         msec_delay(10);
 210
 211         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 212
 213         DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n");
 214         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 215
 216         hw->nvm.ops.reload(hw);
 217         msec_delay(2);
 218
 219         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 220         icr = E1000_READ_REG(hw, E1000_ICR);
 221
 222         if (hw->revision_id == E1000_REVISION_2) {
 223                 if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
 224                         e1000_pci_set_mwi(hw);
 225         }
 226
 227         return ret_val;
 228 }
 229
 230 /**
 231  *  e1000_init_hw_82542 - Initialize hardware
 232  *  @hw: pointer to the HW structure
 233  *
 234  *  This inits the hardware readying it for operation.
 235  **/
 236 static s32 e1000_init_hw_82542(struct e1000_hw *hw)
 237 {
 238         struct e1000_mac_info *mac = &hw->mac;
 239         struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;
 240         s32 ret_val = E1000_SUCCESS;
 241         u32 ctrl;
 242         u16 i;
 243
 244         DEBUGFUNC("e1000_init_hw_82542");
 245
 246         /* Disabling VLAN filtering */
 247         E1000_WRITE_REG(hw, E1000_VET, 0);
 248         mac->ops.clear_vfta(hw);
 249
 250         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
 251         if (hw->revision_id == E1000_REVISION_2) {
 252                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
 253                 e1000_pci_clear_mwi(hw);
 254                 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
 255                 E1000_WRITE_FLUSH(hw);
 256                 msec_delay(5);
 257         }
 258
 259         /* Setup the receive address. */
 260         e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
 261
 262         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
 263         if (hw->revision_id == E1000_REVISION_2) {
 264                 E1000_WRITE_REG(hw, E1000_RCTL, 0);
 265                 E1000_WRITE_FLUSH(hw);
 266                 msec_delay(1);
 267                 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
 268                         e1000_pci_set_mwi(hw);
 269         }
 270
 271         /* Zero out the Multicast HASH table */
 272         DEBUGOUT("Zeroing the MTA\n");
 273         for (i = 0; i < mac->mta_reg_count; i++)
 274                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 275
 276         /*
 277          * Set the PCI priority bit correctly in the CTRL register.  This
 278          * determines if the adapter gives priority to receives, or if it
 279          * gives equal priority to transmits and receives.
 280          */
 281         if (dev_spec->dma_fairness) {
 282                 ctrl = E1000_READ_REG(hw, E1000_CTRL);
 283                 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
 284         }
 285
 286         /* Setup link and flow control */
 287         ret_val = e1000_setup_link_82542(hw);
 288
 289         /*
 290          * Clear all of the statistics registers (clear on read).  It is
 291          * important that we do this after we have tried to establish link
 292          * because the symbol error count will increment wildly if there
 293          * is no link.
 294          */
 295         e1000_clear_hw_cntrs_82542(hw);
 296
 297         return ret_val;
 298 }
 299
 300 /**
 301  *  e1000_setup_link_82542 - Setup flow control and link settings
 302  *  @hw: pointer to the HW structure
 303  *
 304  *  Determines which flow control settings to use, then configures flow
 305  *  control.  Calls the appropriate media-specific link configuration
 306  *  function.  Assuming the adapter has a valid link partner, a valid link
 307  *  should be established.  Assumes the hardware has previously been reset
 308  *  and the transmitter and receiver are not enabled.
 309  **/
 310 static s32 e1000_setup_link_82542(struct e1000_hw *hw)
 311 {
 312         struct e1000_mac_info *mac = &hw->mac;
 313         s32 ret_val = E1000_SUCCESS;
 314
 315         DEBUGFUNC("e1000_setup_link_82542");
 316
 317         ret_val = e1000_set_default_fc_generic(hw);
 318         if (ret_val)
 319                 goto out;
 320
 321         hw->fc.requested_mode &= ~e1000_fc_tx_pause;
 322
 323         if (mac->report_tx_early == 1)
 324                 hw->fc.requested_mode &= ~e1000_fc_rx_pause;
 325
 326         /*
 327          * Save off the requested flow control mode for use later.  Depending
 328          * on the link partner's capabilities, we may or may not use this mode.
 329          */
 330         hw->fc.current_mode = hw->fc.requested_mode;
 331
 332         DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
 333                                                      hw->fc.current_mode);
 334
 335         /* Call the necessary subroutine to configure the link. */
 336         ret_val = mac->ops.setup_physical_interface(hw);
 337         if (ret_val)
 338                 goto out;
 339
 340         /*
 341          * Initialize the flow control address, type, and PAUSE timer
 342          * registers to their default values.  This is done even if flow
 343          * control is disabled, because it does not hurt anything to
 344          * initialize these registers.
 345          */
 346         DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
 347
 348         E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
 349         E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
 350         E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
 351
 352         E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
 353
 354         ret_val = e1000_set_fc_watermarks_generic(hw);
 355
 356 out:
 357         return ret_val;
 358 }
 359
 360 /**
 361  *  e1000_led_on_82542 - Turn on SW controllable LED
 362  *  @hw: pointer to the HW structure
 363  *
 364  *  Turns the SW defined LED on.
 365  **/
 366 static s32 e1000_led_on_82542(struct e1000_hw *hw __unused)
 367 {
 368 #if 0
 369         u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
 370
 371         DEBUGFUNC("e1000_led_on_82542");
 372
 373         ctrl |= E1000_CTRL_SWDPIN0;
 374         ctrl |= E1000_CTRL_SWDPIO0;
 375         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 376
 377         return E1000_SUCCESS;
 378 #endif
 379         return 0;
 380 }
 381
 382 /**
 383  *  e1000_led_off_82542 - Turn off SW controllable LED
 384  *  @hw: pointer to the HW structure
 385  *
 386  *  Turns the SW defined LED off.
 387  **/
 388 static s32 e1000_led_off_82542(struct e1000_hw *hw __unused)
 389 {
 390 #if 0
 391         u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
 392
 393         DEBUGFUNC("e1000_led_off_82542");
 394
 395         ctrl &= ~E1000_CTRL_SWDPIN0;
 396         ctrl |= E1000_CTRL_SWDPIO0;
 397         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
 398
 399         return E1000_SUCCESS;
 400 #endif
 401         return 0;
 402 }
 403
 404 /**
 405  *  e1000_rar_set_82542 - Set receive address register
 406  *  @hw: pointer to the HW structure
 407  *  @addr: pointer to the receive address
 408  *  @index: receive address array register
 409  *
 410  *  Sets the receive address array register at index to the address passed
 411  *  in by addr.
 412  **/
 413 static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
 414 {
 415         u32 rar_low, rar_high;
 416
 417         DEBUGFUNC("e1000_rar_set_82542");
 418
 419         /*
 420          * HW expects these in little endian so we reverse the byte order
 421          * from network order (big endian) to little endian
 422          */
 423         rar_low = ((u32) addr[0] |
 424                    ((u32) addr[1] << 8) |
 425                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 426
 427         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
 428
 429         /* If MAC address zero, no need to set the AV bit */
 430         if (rar_low || rar_high)
 431                 rar_high |= E1000_RAH_AV;
 432
 433         E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
 434         E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
 435 }
 436
 437 /**
 438  *  e1000_translate_register_82542 - Translate the proper register offset
 439  *  @reg: e1000 register to be read
 440  *
 441  *  Registers in 82542 are located in different offsets than other adapters
 442  *  even though they function in the same manner.  This function takes in
 443  *  the name of the register to read and returns the correct offset for
 444  *  82542 silicon.
 445  **/
 446 u32 e1000_translate_register_82542(u32 reg)
 447 {
 448         /*
 449          * Some of the 82542 registers are located at different
 450          * offsets than they are in newer adapters.
 451          * Despite the difference in location, the registers
 452          * function in the same manner.
 453          */
 454         switch (reg) {
 455         case E1000_RA:
 456                 reg = 0x00040;
 457                 break;
 458         case E1000_RDTR:
 459                 reg = 0x00108;
 460                 break;
 461         case E1000_RDBAL(0):
 462                 reg = 0x00110;
 463                 break;
 464         case E1000_RDBAH(0):
 465                 reg = 0x00114;
 466                 break;
 467         case E1000_RDLEN(0):
 468                 reg = 0x00118;
 469                 break;
 470         case E1000_RDH(0):
 471                 reg = 0x00120;
 472                 break;
 473         case E1000_RDT(0):
 474                 reg = 0x00128;
 475                 break;
 476         case E1000_RDBAL(1):
 477                 reg = 0x00138;
 478                 break;
 479         case E1000_RDBAH(1):
 480                 reg = 0x0013C;
 481                 break;
 482         case E1000_RDLEN(1):
 483                 reg = 0x00140;
 484                 break;
 485         case E1000_RDH(1):
 486                 reg = 0x00148;
 487                 break;
 488         case E1000_RDT(1):
 489                 reg = 0x00150;
 490                 break;
 491         case E1000_FCRTH:
 492                 reg = 0x00160;
 493                 break;
 494         case E1000_FCRTL:
 495                 reg = 0x00168;
 496                 break;
 497         case E1000_MTA:
 498                 reg = 0x00200;
 499                 break;
 500         case E1000_TDBAL(0):
 501                 reg = 0x00420;
 502                 break;
 503         case E1000_TDBAH(0):
 504                 reg = 0x00424;
 505                 break;
 506         case E1000_TDLEN(0):
 507                 reg = 0x00428;
 508                 break;
 509         case E1000_TDH(0):
 510                 reg = 0x00430;
 511                 break;
 512         case E1000_TDT(0):
 513                 reg = 0x00438;
 514                 break;
 515         case E1000_TIDV:
 516                 reg = 0x00440;
 517                 break;
 518         case E1000_VFTA:
 519                 reg = 0x00600;
 520                 break;
 521         case E1000_TDFH:
 522                 reg = 0x08010;
 523                 break;
 524         case E1000_TDFT:
 525                 reg = 0x08018;
 526                 break;
 527         default:
 528                 break;
 529         }
 530
 531         return reg;
 532 }
 533
 534 /**
 535  *  e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters
 536  *  @hw: pointer to the HW structure
 537  *
 538  *  Clears the hardware counters by reading the counter registers.
 539  **/
 540 static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
 541 {
 542         DEBUGFUNC("e1000_clear_hw_cntrs_82542");
 543
 544         e1000_clear_hw_cntrs_base_generic(hw);
 545
 546 #if 0
 547         E1000_READ_REG(hw, E1000_PRC64);
 548         E1000_READ_REG(hw, E1000_PRC127);
 549         E1000_READ_REG(hw, E1000_PRC255);
 550         E1000_READ_REG(hw, E1000_PRC511);
 551         E1000_READ_REG(hw, E1000_PRC1023);
 552         E1000_READ_REG(hw, E1000_PRC1522);
 553         E1000_READ_REG(hw, E1000_PTC64);
 554         E1000_READ_REG(hw, E1000_PTC127);
 555         E1000_READ_REG(hw, E1000_PTC255);
 556         E1000_READ_REG(hw, E1000_PTC511);
 557         E1000_READ_REG(hw, E1000_PTC1023);
 558         E1000_READ_REG(hw, E1000_PTC1522);
 559 #endif
 560 }
 561
 562 static struct pci_device_id e1000_82542_nics[] = {
 563      PCI_ROM(0x8086, 0x1000, "E1000_DEV_ID_82542", "E1000_DEV_ID_82542", e1000_82542),
 564 };
 565
 566 struct pci_driver e1000_82542_driver __pci_driver = {
 567         .ids = e1000_82542_nics,
 568         .id_count = (sizeof (e1000_82542_nics) / sizeof (e1000_82542_nics[0])),
 569         .probe = e1000_probe,
 570         .remove = e1000_remove,
 571 };