src/drivers/net/e1000e/e1000e_hw.h

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 FILE_LICENCE ( GPL2_OR_LATER );
  30
  31 #ifndef _E1000E_HW_H_
  32 #define _E1000E_HW_H_
  33
  34 #include "e1000e_regs.h"
  35 #include "e1000e_defines.h"
  36
  37 struct e1000_hw;
  38
  39 #define E1000_DEV_ID_82571EB_COPPER           0x105E
  40 #define E1000_DEV_ID_82571EB_FIBER            0x105F
  41 #define E1000_DEV_ID_82571EB_SERDES           0x1060
  42 #define E1000_DEV_ID_82571EB_SERDES_DUAL      0x10D9
  43 #define E1000_DEV_ID_82571EB_SERDES_QUAD      0x10DA
  44 #define E1000_DEV_ID_82571EB_QUAD_COPPER      0x10A4
  45 #define E1000_DEV_ID_82571PT_QUAD_COPPER      0x10D5
  46 #define E1000_DEV_ID_82571EB_QUAD_FIBER       0x10A5
  47 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP   0x10BC
  48 #define E1000_DEV_ID_82572EI_COPPER           0x107D
  49 #define E1000_DEV_ID_82572EI_FIBER            0x107E
  50 #define E1000_DEV_ID_82572EI_SERDES           0x107F
  51 #define E1000_DEV_ID_82572EI                  0x10B9
  52 #define E1000_DEV_ID_82573E                   0x108B
  53 #define E1000_DEV_ID_82573E_IAMT              0x108C
  54 #define E1000_DEV_ID_82573L                   0x109A
  55 #define E1000_DEV_ID_82574L                   0x10D3
  56 #define E1000_DEV_ID_82574LA                  0x10F6
  57 #define E1000_DEV_ID_82583V                   0x150C
  58 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT   0x1096
  59 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT   0x1098
  60 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT   0x10BA
  61 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT   0x10BB
  62 #define E1000_DEV_ID_ICH8_82567V_3            0x1501
  63 #define E1000_DEV_ID_ICH8_IGP_M_AMT           0x1049
  64 #define E1000_DEV_ID_ICH8_IGP_AMT             0x104A
  65 #define E1000_DEV_ID_ICH8_IGP_C               0x104B
  66 #define E1000_DEV_ID_ICH8_IFE                 0x104C
  67 #define E1000_DEV_ID_ICH8_IFE_GT              0x10C4
  68 #define E1000_DEV_ID_ICH8_IFE_G               0x10C5
  69 #define E1000_DEV_ID_ICH8_IGP_M               0x104D
  70 #define E1000_DEV_ID_ICH9_IGP_M               0x10BF
  71 #define E1000_DEV_ID_ICH9_IGP_M_AMT           0x10F5
  72 #define E1000_DEV_ID_ICH9_IGP_M_V             0x10CB
  73 #define E1000_DEV_ID_ICH9_IGP_AMT             0x10BD
  74 #define E1000_DEV_ID_ICH9_BM                  0x10E5
  75 #define E1000_DEV_ID_ICH9_IGP_C               0x294C
  76 #define E1000_DEV_ID_ICH9_IFE                 0x10C0
  77 #define E1000_DEV_ID_ICH9_IFE_GT              0x10C3
  78 #define E1000_DEV_ID_ICH9_IFE_G               0x10C2
  79 #define E1000_DEV_ID_ICH10_R_BM_LM            0x10CC
  80 #define E1000_DEV_ID_ICH10_R_BM_LF            0x10CD
  81 #define E1000_DEV_ID_ICH10_R_BM_V             0x10CE
  82 #define E1000_DEV_ID_ICH10_D_BM_LM            0x10DE
  83 #define E1000_DEV_ID_ICH10_D_BM_LF            0x10DF
  84 #define E1000_DEV_ID_PCH_M_HV_LM              0x10EA
  85 #define E1000_DEV_ID_PCH_M_HV_LC              0x10EB
  86 #define E1000_DEV_ID_PCH_D_HV_DM              0x10EF
  87 #define E1000_DEV_ID_PCH_D_HV_DC              0x10F0
  88 #define E1000_REVISION_0 0
  89 #define E1000_REVISION_1 1
  90 #define E1000_REVISION_2 2
  91 #define E1000_REVISION_3 3
  92 #define E1000_REVISION_4 4
  93
  94 #define E1000_FUNC_0     0
  95 #define E1000_FUNC_1     1
  96
  97 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
  98 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
  99
 100 enum e1000_mac_type {
 101         e1000_undefined = 0,
 102         e1000_82571,
 103         e1000_82572,
 104         e1000_82573,
 105         e1000_82574,
 106         e1000_82583,
 107         e1000_80003es2lan,
 108         e1000_ich8lan,
 109         e1000_ich9lan,
 110         e1000_ich10lan,
 111         e1000_pchlan,
 112         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
 113 };
 114
 115 enum e1000_media_type {
 116         e1000_media_type_unknown = 0,
 117         e1000_media_type_copper = 1,
 118         e1000_media_type_fiber = 2,
 119         e1000_media_type_internal_serdes = 3,
 120         e1000_num_media_types
 121 };
 122
 123 enum e1000_nvm_type {
 124         e1000_nvm_unknown = 0,
 125         e1000_nvm_none,
 126         e1000_nvm_eeprom_spi,
 127         e1000_nvm_flash_hw,
 128         e1000_nvm_flash_sw
 129 };
 130
 131 enum e1000_nvm_override {
 132         e1000_nvm_override_none = 0,
 133         e1000_nvm_override_spi_small,
 134         e1000_nvm_override_spi_large,
 135 };
 136
 137 enum e1000_phy_type {
 138         e1000_phy_unknown = 0,
 139         e1000_phy_none,
 140         e1000_phy_m88,
 141         e1000_phy_igp,
 142         e1000_phy_igp_2,
 143         e1000_phy_gg82563,
 144         e1000_phy_igp_3,
 145         e1000_phy_ife,
 146         e1000_phy_bm,
 147         e1000_phy_82578,
 148         e1000_phy_82577,
 149 };
 150
 151 enum e1000_bus_type {
 152         e1000_bus_type_unknown = 0,
 153         e1000_bus_type_pci,
 154         e1000_bus_type_pcix,
 155         e1000_bus_type_pci_express,
 156         e1000_bus_type_reserved
 157 };
 158
 159 enum e1000_bus_speed {
 160         e1000_bus_speed_unknown = 0,
 161         e1000_bus_speed_33,
 162         e1000_bus_speed_66,
 163         e1000_bus_speed_100,
 164         e1000_bus_speed_120,
 165         e1000_bus_speed_133,
 166         e1000_bus_speed_2500,
 167         e1000_bus_speed_5000,
 168         e1000_bus_speed_reserved
 169 };
 170
 171 enum e1000_bus_width {
 172         e1000_bus_width_unknown = 0,
 173         e1000_bus_width_pcie_x1,
 174         e1000_bus_width_pcie_x2,
 175         e1000_bus_width_pcie_x4 = 4,
 176         e1000_bus_width_pcie_x8 = 8,
 177         e1000_bus_width_32,
 178         e1000_bus_width_64,
 179         e1000_bus_width_reserved
 180 };
 181
 182 enum e1000_1000t_rx_status {
 183         e1000_1000t_rx_status_not_ok = 0,
 184         e1000_1000t_rx_status_ok,
 185         e1000_1000t_rx_status_undefined = 0xFF
 186 };
 187
 188 enum e1000_rev_polarity {
 189         e1000_rev_polarity_normal = 0,
 190         e1000_rev_polarity_reversed,
 191         e1000_rev_polarity_undefined = 0xFF
 192 };
 193
 194 enum e1000_fc_mode {
 195         e1000_fc_none = 0,
 196         e1000_fc_rx_pause,
 197         e1000_fc_tx_pause,
 198         e1000_fc_full,
 199         e1000_fc_default = 0xFF
 200 };
 201
 202 enum e1000_ms_type {
 203         e1000_ms_hw_default = 0,
 204         e1000_ms_force_master,
 205         e1000_ms_force_slave,
 206         e1000_ms_auto
 207 };
 208
 209 enum e1000_smart_speed {
 210         e1000_smart_speed_default = 0,
 211         e1000_smart_speed_on,
 212         e1000_smart_speed_off
 213 };
 214
 215 enum e1000_serdes_link_state {
 216         e1000_serdes_link_down = 0,
 217         e1000_serdes_link_autoneg_progress,
 218         e1000_serdes_link_autoneg_complete,
 219         e1000_serdes_link_forced_up
 220 };
 221
 222 /* Receive Descriptor */
 223 struct e1000_rx_desc {
 224         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 225         __le16 length;      /* Length of data DMAed into data buffer */
 226         __le16 csum;        /* Packet checksum */
 227         u8  status;         /* Descriptor status */
 228         u8  errors;         /* Descriptor Errors */
 229         __le16 special;
 230 };
 231
 232 /* Receive Descriptor - Extended */
 233 union e1000_rx_desc_extended {
 234         struct {
 235                 __le64 buffer_addr;
 236                 __le64 reserved;
 237         } read;
 238         struct {
 239                 struct {
 240                         __le32 mrq;           /* Multiple Rx Queues */
 241                         union {
 242                                 __le32 rss;         /* RSS Hash */
 243                                 struct {
 244                                         __le16 ip_id;  /* IP id */
 245                                         __le16 csum;   /* Packet Checksum */
 246                                 } csum_ip;
 247                         } hi_dword;
 248                 } lower;
 249                 struct {
 250                         __le32 status_error;  /* ext status/error */
 251                         __le16 length;
 252                         __le16 vlan;          /* VLAN tag */
 253                 } upper;
 254         } wb;  /* writeback */
 255 };
 256
 257 #define MAX_PS_BUFFERS 4
 258 /* Receive Descriptor - Packet Split */
 259 union e1000_rx_desc_packet_split {
 260         struct {
 261                 /* one buffer for protocol header(s), three data buffers */
 262                 __le64 buffer_addr[MAX_PS_BUFFERS];
 263         } read;
 264         struct {
 265                 struct {
 266                         __le32 mrq;           /* Multiple Rx Queues */
 267                         union {
 268                                 __le32 rss;           /* RSS Hash */
 269                                 struct {
 270                                         __le16 ip_id;    /* IP id */
 271                                         __le16 csum;     /* Packet Checksum */
 272                                 } csum_ip;
 273                         } hi_dword;
 274                 } lower;
 275                 struct {
 276                         __le32 status_error;  /* ext status/error */
 277                         __le16 length0;       /* length of buffer 0 */
 278                         __le16 vlan;          /* VLAN tag */
 279                 } middle;
 280                 struct {
 281                         __le16 header_status;
 282                         __le16 length[3];     /* length of buffers 1-3 */
 283                 } upper;
 284                 __le64 reserved;
 285         } wb; /* writeback */
 286 };
 287
 288 /* Transmit Descriptor */
 289 struct e1000_tx_desc {
 290         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 291         union {
 292                 __le32 data;
 293                 struct {
 294                         __le16 length;    /* Data buffer length */
 295                         u8 cso;           /* Checksum offset */
 296                         u8 cmd;           /* Descriptor control */
 297                 } flags;
 298         } lower;
 299         union {
 300                 __le32 data;
 301                 struct {
 302                         u8 status;        /* Descriptor status */
 303                         u8 css;           /* Checksum start */
 304                         __le16 special;
 305                 } fields;
 306         } upper;
 307 };
 308
 309 /* Offload Context Descriptor */
 310 struct e1000_context_desc {
 311         union {
 312                 __le32 ip_config;
 313                 struct {
 314                         u8 ipcss;         /* IP checksum start */
 315                         u8 ipcso;         /* IP checksum offset */
 316                         __le16 ipcse;     /* IP checksum end */
 317                 } ip_fields;
 318         } lower_setup;
 319         union {
 320                 __le32 tcp_config;
 321                 struct {
 322                         u8 tucss;         /* TCP checksum start */
 323                         u8 tucso;         /* TCP checksum offset */
 324                         __le16 tucse;     /* TCP checksum end */
 325                 } tcp_fields;
 326         } upper_setup;
 327         __le32 cmd_and_length;
 328         union {
 329                 __le32 data;
 330                 struct {
 331                         u8 status;        /* Descriptor status */
 332                         u8 hdr_len;       /* Header length */
 333                         __le16 mss;       /* Maximum segment size */
 334                 } fields;
 335         } tcp_seg_setup;
 336 };
 337
 338 /* Offload data descriptor */
 339 struct e1000_data_desc {
 340         __le64 buffer_addr;   /* Address of the descriptor's buffer address */
 341         union {
 342                 __le32 data;
 343                 struct {
 344                         __le16 length;    /* Data buffer length */
 345                         u8 typ_len_ext;
 346                         u8 cmd;
 347                 } flags;
 348         } lower;
 349         union {
 350                 __le32 data;
 351                 struct {
 352                         u8 status;        /* Descriptor status */
 353                         u8 popts;         /* Packet Options */
 354                         __le16 special;
 355                 } fields;
 356         } upper;
 357 };
 358
 359 /* Statistics counters collected by the MAC */
 360 struct e1000_hw_stats {
 361         u64 crcerrs;
 362         u64 algnerrc;
 363         u64 symerrs;
 364         u64 rxerrc;
 365         u64 mpc;
 366         u64 scc;
 367         u64 ecol;
 368         u64 mcc;
 369         u64 latecol;
 370         u64 colc;
 371         u64 dc;
 372         u64 tncrs;
 373         u64 sec;
 374         u64 cexterr;
 375         u64 rlec;
 376         u64 xonrxc;
 377         u64 xontxc;
 378         u64 xoffrxc;
 379         u64 xofftxc;
 380         u64 fcruc;
 381         u64 prc64;
 382         u64 prc127;
 383         u64 prc255;
 384         u64 prc511;
 385         u64 prc1023;
 386         u64 prc1522;
 387         u64 gprc;
 388         u64 bprc;
 389         u64 mprc;
 390         u64 gptc;
 391         u64 gorc;
 392         u64 gotc;
 393         u64 rnbc;
 394         u64 ruc;
 395         u64 rfc;
 396         u64 roc;
 397         u64 rjc;
 398         u64 mgprc;
 399         u64 mgpdc;
 400         u64 mgptc;
 401         u64 tor;
 402         u64 tot;
 403         u64 tpr;
 404         u64 tpt;
 405         u64 ptc64;
 406         u64 ptc127;
 407         u64 ptc255;
 408         u64 ptc511;
 409         u64 ptc1023;
 410         u64 ptc1522;
 411         u64 mptc;
 412         u64 bptc;
 413         u64 tsctc;
 414         u64 tsctfc;
 415         u64 iac;
 416         u64 icrxptc;
 417         u64 icrxatc;
 418         u64 ictxptc;
 419         u64 ictxatc;
 420         u64 ictxqec;
 421         u64 ictxqmtc;
 422         u64 icrxdmtc;
 423         u64 icrxoc;
 424         u64 doosync;
 425 };
 426
 427
 428 struct e1000_phy_stats {
 429         u32 idle_errors;
 430         u32 receive_errors;
 431 };
 432
 433 struct e1000_host_mng_dhcp_cookie {
 434         u32 signature;
 435         u8  status;
 436         u8  reserved0;
 437         u16 vlan_id;
 438         u32 reserved1;
 439         u16 reserved2;
 440         u8  reserved3;
 441         u8  checksum;
 442 };
 443
 444 /* Host Interface "Rev 1" */
 445 struct e1000_host_command_header {
 446         u8 command_id;
 447         u8 command_length;
 448         u8 command_options;
 449         u8 checksum;
 450 };
 451
 452 #define E1000_HI_MAX_DATA_LENGTH     252
 453 struct e1000_host_command_info {
 454         struct e1000_host_command_header command_header;
 455         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 456 };
 457
 458 /* Host Interface "Rev 2" */
 459 struct e1000_host_mng_command_header {
 460         u8  command_id;
 461         u8  checksum;
 462         u16 reserved1;
 463         u16 reserved2;
 464         u16 command_length;
 465 };
 466
 467 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
 468 struct e1000_host_mng_command_info {
 469         struct e1000_host_mng_command_header command_header;
 470         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 471 };
 472
 473 #include "e1000e_mac.h"
 474 #include "e1000e_phy.h"
 475 #include "e1000e_nvm.h"
 476 #include "e1000e_manage.h"
 477
 478 struct e1000_mac_operations {
 479         /* Function pointers for the MAC. */
 480         s32  (*init_params)(struct e1000_hw *);
 481         s32  (*id_led_init)(struct e1000_hw *);
 482         s32  (*blink_led)(struct e1000_hw *);
 483         s32  (*check_for_link)(struct e1000_hw *);
 484         bool (*check_mng_mode)(struct e1000_hw *hw);
 485         s32  (*cleanup_led)(struct e1000_hw *);
 486         void (*clear_hw_cntrs)(struct e1000_hw *);
 487         void (*clear_vfta)(struct e1000_hw *);
 488         s32  (*get_bus_info)(struct e1000_hw *);
 489         void (*set_lan_id)(struct e1000_hw *);
 490         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 491         s32  (*led_on)(struct e1000_hw *);
 492         s32  (*led_off)(struct e1000_hw *);
 493         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 494         s32  (*reset_hw)(struct e1000_hw *);
 495         s32  (*init_hw)(struct e1000_hw *);
 496         s32  (*setup_link)(struct e1000_hw *);
 497         s32  (*setup_physical_interface)(struct e1000_hw *);
 498         s32  (*setup_led)(struct e1000_hw *);
 499         void (*write_vfta)(struct e1000_hw *, u32, u32);
 500         void (*mta_set)(struct e1000_hw *, u32);
 501         void (*config_collision_dist)(struct e1000_hw *);
 502         void (*rar_set)(struct e1000_hw *, u8*, u32);
 503         s32  (*read_mac_addr)(struct e1000_hw *);
 504         s32  (*validate_mdi_setting)(struct e1000_hw *);
 505         s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
 506         s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
 507                       struct e1000_host_mng_command_header*);
 508         s32  (*mng_enable_host_if)(struct e1000_hw *);
 509         s32  (*wait_autoneg)(struct e1000_hw *);
 510 };
 511
 512 struct e1000_phy_operations {
 513         s32  (*init_params)(struct e1000_hw *);
 514         s32  (*acquire)(struct e1000_hw *);
 515         s32  (*cfg_on_link_up)(struct e1000_hw *);
 516         s32  (*check_polarity)(struct e1000_hw *);
 517         s32  (*check_reset_block)(struct e1000_hw *);
 518         s32  (*commit)(struct e1000_hw *);
 519 #if 0
 520         s32  (*force_speed_duplex)(struct e1000_hw *);
 521 #endif
 522         s32  (*get_cfg_done)(struct e1000_hw *hw);
 523 #if 0
 524         s32  (*get_cable_length)(struct e1000_hw *);
 525 #endif
 526         s32  (*get_info)(struct e1000_hw *);
 527         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 528         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 529         void (*release)(struct e1000_hw *);
 530         s32  (*reset)(struct e1000_hw *);
 531         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 532         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 533         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 534         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 535         void (*power_up)(struct e1000_hw *);
 536         void (*power_down)(struct e1000_hw *);
 537 };
 538
 539 struct e1000_nvm_operations {
 540         s32  (*init_params)(struct e1000_hw *);
 541         s32  (*acquire)(struct e1000_hw *);
 542         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 543         void (*release)(struct e1000_hw *);
 544         void (*reload)(struct e1000_hw *);
 545         s32  (*update)(struct e1000_hw *);
 546         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 547         s32  (*validate)(struct e1000_hw *);
 548         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 549 };
 550
 551 struct e1000_mac_info {
 552         struct e1000_mac_operations ops;
 553         u8 addr[6];
 554         u8 perm_addr[6];
 555
 556         enum e1000_mac_type type;
 557
 558         u32 collision_delta;
 559         u32 ledctl_default;
 560         u32 ledctl_mode1;
 561         u32 ledctl_mode2;
 562         u32 mc_filter_type;
 563         u32 tx_packet_delta;
 564         u32 txcw;
 565
 566         u16 current_ifs_val;
 567         u16 ifs_max_val;
 568         u16 ifs_min_val;
 569         u16 ifs_ratio;
 570         u16 ifs_step_size;
 571         u16 mta_reg_count;
 572
 573         /* Maximum size of the MTA register table in all supported adapters */
 574         #define MAX_MTA_REG 128
 575         u32 mta_shadow[MAX_MTA_REG];
 576         u16 rar_entry_count;
 577
 578         u8  forced_speed_duplex;
 579
 580         bool adaptive_ifs;
 581         bool arc_subsystem_valid;
 582         bool asf_firmware_present;
 583         bool autoneg;
 584         bool autoneg_failed;
 585         bool get_link_status;
 586         bool in_ifs_mode;
 587         enum e1000_serdes_link_state serdes_link_state;
 588         bool serdes_has_link;
 589         bool tx_pkt_filtering;
 590 };
 591
 592 struct e1000_phy_info {
 593         struct e1000_phy_operations ops;
 594         enum e1000_phy_type type;
 595
 596         enum e1000_1000t_rx_status local_rx;
 597         enum e1000_1000t_rx_status remote_rx;
 598         enum e1000_ms_type ms_type;
 599         enum e1000_ms_type original_ms_type;
 600         enum e1000_rev_polarity cable_polarity;
 601         enum e1000_smart_speed smart_speed;
 602
 603         u32 addr;
 604         u32 id;
 605         u32 reset_delay_us; /* in usec */
 606         u32 revision;
 607
 608         enum e1000_media_type media_type;
 609
 610         u16 autoneg_advertised;
 611         u16 autoneg_mask;
 612         u16 cable_length;
 613         u16 max_cable_length;
 614         u16 min_cable_length;
 615
 616         u8 mdix;
 617
 618         bool disable_polarity_correction;
 619         bool is_mdix;
 620         bool polarity_correction;
 621         bool reset_disable;
 622         bool speed_downgraded;
 623         bool autoneg_wait_to_complete;
 624 };
 625
 626 struct e1000_nvm_info {
 627         struct e1000_nvm_operations ops;
 628         enum e1000_nvm_type type;
 629         enum e1000_nvm_override override;
 630
 631         u32 flash_bank_size;
 632         u32 flash_base_addr;
 633
 634         u16 word_size;
 635         u16 delay_usec;
 636         u16 address_bits;
 637         u16 opcode_bits;
 638         u16 page_size;
 639 };
 640
 641 struct e1000_bus_info {
 642         enum e1000_bus_type type;
 643         enum e1000_bus_speed speed;
 644         enum e1000_bus_width width;
 645
 646         u16 func;
 647         u16 pci_cmd_word;
 648 };
 649
 650 struct e1000_fc_info {
 651         u32 high_water;          /* Flow control high-water mark */
 652         u32 low_water;           /* Flow control low-water mark */
 653         u16 pause_time;          /* Flow control pause timer */
 654         bool send_xon;           /* Flow control send XON */
 655         bool strict_ieee;        /* Strict IEEE mode */
 656         enum e1000_fc_mode current_mode; /* FC mode in effect */
 657         enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
 658 };
 659
 660 struct e1000_dev_spec_82571 {
 661         bool laa_is_present;
 662         u32 smb_counter;
 663 };
 664
 665 struct e1000_dev_spec_80003es2lan {
 666         bool  mdic_wa_enable;
 667 };
 668
 669 struct e1000_shadow_ram {
 670         u16  value;
 671         bool modified;
 672 };
 673
 674 #define E1000_ICH8_SHADOW_RAM_WORDS             2048
 675
 676 struct e1000_dev_spec_ich8lan {
 677         bool kmrn_lock_loss_workaround_enabled;
 678         struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
 679         bool nvm_k1_enabled;
 680 };
 681
 682 struct e1000_hw {
 683         struct e1000_adapter *adapter;
 684
 685         u8 __iomem *hw_addr;
 686         u8 __iomem *flash_address;
 687
 688         void *back;
 689         unsigned long io_base;
 690
 691         struct e1000_mac_info  mac;
 692         struct e1000_fc_info   fc;
 693         struct e1000_phy_info  phy;
 694         struct e1000_nvm_info  nvm;
 695         struct e1000_bus_info  bus;
 696         struct e1000_host_mng_dhcp_cookie mng_cookie;
 697
 698         union {
 699                 struct e1000_dev_spec_82571     _82571;
 700                 struct e1000_dev_spec_80003es2lan _80003es2lan;
 701                 struct e1000_dev_spec_ich8lan   ich8lan;
 702         } dev_spec;
 703
 704         u16 device_id;
 705         u16 subsystem_vendor_id;
 706         u16 subsystem_device_id;
 707         u16 vendor_id;
 708
 709         u8  revision_id;
 710 };
 711
 712 #include "e1000e_82571.h"
 713 #include "e1000e_80003es2lan.h"
 714 #include "e1000e_ich8lan.h"
 715
 716 /* These functions must be implemented by drivers */
 717 s32  e1000e_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 718
 719 #endif