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[uri] Special case NULL in churi()
[gpxe.git] / src / drivers / net / sky2.h
blob7963fbe7d1f2ccf95d3716dff37bc8dfce4e7fd9
1 /*
2 * Definitions for the new Marvell Yukon 2 driver.
3 */
4 #ifndef _SKY2_H
5 #define _SKY2_H
6
7 FILE_LICENCE ( GPL2_ONLY );
8
9 /* Added for gPXE ------------------ */
10
11 /* These were defined in Linux ethtool.h. Their values are arbitrary;
12 they aid only in bookkeeping for the driver. */
13
14 #define AUTONEG_DISABLE 0x00
15 #define AUTONEG_ENABLE 0x01
16
17 #define DUPLEX_HALF 0x00
18 #define DUPLEX_FULL 0x01
19
20 #define SPEED_10 10
21 #define SPEED_100 100
22 #define SPEED_1000 1000
23
24 #define ADVERTISED_10baseT_Half (1 << 0)
25 #define ADVERTISED_10baseT_Full (1 << 1)
26 #define ADVERTISED_100baseT_Half (1 << 2)
27 #define ADVERTISED_100baseT_Full (1 << 3)
28 #define ADVERTISED_1000baseT_Half (1 << 4)
29 #define ADVERTISED_1000baseT_Full (1 << 5)
30
31 #define SUPPORTED_10baseT_Half (1 << 0)
32 #define SUPPORTED_10baseT_Full (1 << 1)
33 #define SUPPORTED_100baseT_Half (1 << 2)
34 #define SUPPORTED_100baseT_Full (1 << 3)
35 #define SUPPORTED_1000baseT_Half (1 << 4)
36 #define SUPPORTED_1000baseT_Full (1 << 5)
37 #define SUPPORTED_Autoneg (1 << 6)
38 #define SUPPORTED_TP (1 << 7)
39 #define SUPPORTED_FIBRE (1 << 10)
40
41 /* ----------------------------------- */
42
43 /* PCI config registers */
44 enum {
45 PCI_DEV_REG1 = 0x40,
46 PCI_DEV_REG2 = 0x44,
47 PCI_DEV_STATUS = 0x7c,
48 PCI_DEV_REG3 = 0x80,
49 PCI_DEV_REG4 = 0x84,
50 PCI_DEV_REG5 = 0x88,
51 PCI_CFG_REG_0 = 0x90,
52 PCI_CFG_REG_1 = 0x94,
53 };
54
55 /* Yukon-2 */
56 enum pci_dev_reg_1 {
57 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
58 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
59 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
60 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
61 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
62 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
63 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
64 PCI_Y2_PME_LEGACY= 1<<15, /* PCI Express legacy power management mode */
65
66 PCI_PHY_LNK_TIM_MSK= 3L<<8,/* Bit 9.. 8: GPHY Link Trigger Timer */
67 PCI_ENA_L1_EVENT = 1<<7, /* Enable PEX L1 Event */
68 PCI_ENA_GPHY_LNK = 1<<6, /* Enable PEX L1 on GPHY Link down */
69 PCI_FORCE_PEX_L1 = 1<<5, /* Force to PEX L1 */
70 };
71
72 enum pci_dev_reg_2 {
73 PCI_VPD_WR_THR = 0xffL<<24, /* Bit 31..24: VPD Write Threshold */
74 PCI_DEV_SEL = 0x7fL<<17, /* Bit 23..17: EEPROM Device Select */
75 PCI_VPD_ROM_SZ = 7L<<14, /* Bit 16..14: VPD ROM Size */
76
77 PCI_PATCH_DIR = 0xfL<<8, /* Bit 11.. 8: Ext Patches dir 3..0 */
78 PCI_EXT_PATCHS = 0xfL<<4, /* Bit 7.. 4: Extended Patches 3..0 */
79 PCI_EN_DUMMY_RD = 1<<3, /* Enable Dummy Read */
80 PCI_REV_DESC = 1<<2, /* Reverse Desc. Bytes */
81
82 PCI_USEDATA64 = 1<<0, /* Use 64Bit Data bus ext */
83 };
84
85 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
86 enum pci_dev_reg_4 {
87 /* (Link Training & Status State Machine) */
88 P_PEX_LTSSM_STAT_MSK = 0x7fL<<25, /* Bit 31..25: PEX LTSSM Mask */
89 #define P_PEX_LTSSM_STAT(x) ((x << 25) & P_PEX_LTSSM_STAT_MSK)
90 P_PEX_LTSSM_L1_STAT = 0x34,
91 P_PEX_LTSSM_DET_STAT = 0x01,
92 P_TIMER_VALUE_MSK = 0xffL<<16, /* Bit 23..16: Timer Value Mask */
93 /* (Active State Power Management) */
94 P_FORCE_ASPM_REQUEST = 1<<15, /* Force ASPM Request (A1 only) */
95 P_ASPM_GPHY_LINK_DOWN = 1<<14, /* GPHY Link Down (A1 only) */
96 P_ASPM_INT_FIFO_EMPTY = 1<<13, /* Internal FIFO Empty (A1 only) */
97 P_ASPM_CLKRUN_REQUEST = 1<<12, /* CLKRUN Request (A1 only) */
98
99 P_ASPM_FORCE_CLKREQ_ENA = 1<<4, /* Force CLKREQ Enable (A1b only) */
100 P_ASPM_CLKREQ_PAD_CTL = 1<<3, /* CLKREQ PAD Control (A1 only) */
101 P_ASPM_A1_MODE_SELECT = 1<<2, /* A1 Mode Select (A1 only) */
102 P_CLK_GATE_PEX_UNIT_ENA = 1<<1, /* Enable Gate PEX Unit Clock */
103 P_CLK_GATE_ROOT_COR_ENA = 1<<0, /* Enable Gate Root Core Clock */
104 P_ASPM_CONTROL_MSK = P_FORCE_ASPM_REQUEST | P_ASPM_GPHY_LINK_DOWN
105 | P_ASPM_CLKRUN_REQUEST | P_ASPM_INT_FIFO_EMPTY,
106 };
107
108 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
109 enum pci_dev_reg_5 {
110 /* Bit 31..27: for A3 & later */
111 P_CTL_DIV_CORE_CLK_ENA = 1<<31, /* Divide Core Clock Enable */
112 P_CTL_SRESET_VMAIN_AV = 1<<30, /* Soft Reset for Vmain_av De-Glitch */
113 P_CTL_BYPASS_VMAIN_AV = 1<<29, /* Bypass En. for Vmain_av De-Glitch */
114 P_CTL_TIM_VMAIN_AV_MSK = 3<<27, /* Bit 28..27: Timer Vmain_av Mask */
115 /* Bit 26..16: Release Clock on Event */
116 P_REL_PCIE_RST_DE_ASS = 1<<26, /* PCIe Reset De-Asserted */
117 P_REL_GPHY_REC_PACKET = 1<<25, /* GPHY Received Packet */
118 P_REL_INT_FIFO_N_EMPTY = 1<<24, /* Internal FIFO Not Empty */
119 P_REL_MAIN_PWR_AVAIL = 1<<23, /* Main Power Available */
120 P_REL_CLKRUN_REQ_REL = 1<<22, /* CLKRUN Request Release */
121 P_REL_PCIE_RESET_ASS = 1<<21, /* PCIe Reset Asserted */
122 P_REL_PME_ASSERTED = 1<<20, /* PME Asserted */
123 P_REL_PCIE_EXIT_L1_ST = 1<<19, /* PCIe Exit L1 State */
124 P_REL_LOADER_NOT_FIN = 1<<18, /* EPROM Loader Not Finished */
125 P_REL_PCIE_RX_EX_IDLE = 1<<17, /* PCIe Rx Exit Electrical Idle State */
126 P_REL_GPHY_LINK_UP = 1<<16, /* GPHY Link Up */
127
128 /* Bit 10.. 0: Mask for Gate Clock */
129 P_GAT_PCIE_RST_ASSERTED = 1<<10,/* PCIe Reset Asserted */
130 P_GAT_GPHY_N_REC_PACKET = 1<<9, /* GPHY Not Received Packet */
131 P_GAT_INT_FIFO_EMPTY = 1<<8, /* Internal FIFO Empty */
132 P_GAT_MAIN_PWR_N_AVAIL = 1<<7, /* Main Power Not Available */
133 P_GAT_CLKRUN_REQ_REL = 1<<6, /* CLKRUN Not Requested */
134 P_GAT_PCIE_RESET_ASS = 1<<5, /* PCIe Reset Asserted */
135 P_GAT_PME_DE_ASSERTED = 1<<4, /* PME De-Asserted */
136 P_GAT_PCIE_ENTER_L1_ST = 1<<3, /* PCIe Enter L1 State */
137 P_GAT_LOADER_FINISHED = 1<<2, /* EPROM Loader Finished */
138 P_GAT_PCIE_RX_EL_IDLE = 1<<1, /* PCIe Rx Electrical Idle State */
139 P_GAT_GPHY_LINK_DOWN = 1<<0, /* GPHY Link Down */
140
141 PCIE_OUR5_EVENT_CLK_D3_SET = P_REL_GPHY_REC_PACKET |
142 P_REL_INT_FIFO_N_EMPTY |
143 P_REL_PCIE_EXIT_L1_ST |
144 P_REL_PCIE_RX_EX_IDLE |
145 P_GAT_GPHY_N_REC_PACKET |
146 P_GAT_INT_FIFO_EMPTY |
147 P_GAT_PCIE_ENTER_L1_ST |
148 P_GAT_PCIE_RX_EL_IDLE,
149 };
150
151 #/* PCI_CFG_REG_1 32 bit Config Register 1 (Yukon-Ext only) */
152 enum pci_cfg_reg1 {
153 P_CF1_DIS_REL_EVT_RST = 1<<24, /* Dis. Rel. Event during PCIE reset */
154 /* Bit 23..21: Release Clock on Event */
155 P_CF1_REL_LDR_NOT_FIN = 1<<23, /* EEPROM Loader Not Finished */
156 P_CF1_REL_VMAIN_AVLBL = 1<<22, /* Vmain available */
157 P_CF1_REL_PCIE_RESET = 1<<21, /* PCI-E reset */
158 /* Bit 20..18: Gate Clock on Event */
159 P_CF1_GAT_LDR_NOT_FIN = 1<<20, /* EEPROM Loader Finished */
160 P_CF1_GAT_PCIE_RX_IDLE = 1<<19, /* PCI-E Rx Electrical idle */
161 P_CF1_GAT_PCIE_RESET = 1<<18, /* PCI-E Reset */
162 P_CF1_PRST_PHY_CLKREQ = 1<<17, /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
163 P_CF1_PCIE_RST_CLKREQ = 1<<16, /* Enable PCI-E rst generate CLKREQ */
164
165 P_CF1_ENA_CFG_LDR_DONE = 1<<8, /* Enable core level Config loader done */
166
167 P_CF1_ENA_TXBMU_RD_IDLE = 1<<1, /* Enable TX BMU Read IDLE for ASPM */
168 P_CF1_ENA_TXBMU_WR_IDLE = 1<<0, /* Enable TX BMU Write IDLE for ASPM */
169
170 PCIE_CFG1_EVENT_CLK_D3_SET = P_CF1_DIS_REL_EVT_RST |
171 P_CF1_REL_LDR_NOT_FIN |
172 P_CF1_REL_VMAIN_AVLBL |
173 P_CF1_REL_PCIE_RESET |
174 P_CF1_GAT_LDR_NOT_FIN |
175 P_CF1_GAT_PCIE_RESET |
176 P_CF1_PRST_PHY_CLKREQ |
177 P_CF1_ENA_CFG_LDR_DONE |
178 P_CF1_ENA_TXBMU_RD_IDLE |
179 P_CF1_ENA_TXBMU_WR_IDLE,
180 };
181
182
183 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
184 PCI_STATUS_SIG_SYSTEM_ERROR | \
185 PCI_STATUS_REC_MASTER_ABORT | \
186 PCI_STATUS_REC_TARGET_ABORT | \
187 PCI_STATUS_PARITY)
188
189 enum csr_regs {
190 B0_RAP = 0x0000,
191 B0_CTST = 0x0004,
192 B0_Y2LED = 0x0005,
193 B0_POWER_CTRL = 0x0007,
194 B0_ISRC = 0x0008,
195 B0_IMSK = 0x000c,
196 B0_HWE_ISRC = 0x0010,
197 B0_HWE_IMSK = 0x0014,
198
199 /* Special ISR registers (Yukon-2 only) */
200 B0_Y2_SP_ISRC2 = 0x001c,
201 B0_Y2_SP_ISRC3 = 0x0020,
202 B0_Y2_SP_EISR = 0x0024,
203 B0_Y2_SP_LISR = 0x0028,
204 B0_Y2_SP_ICR = 0x002c,
205
206 B2_MAC_1 = 0x0100,
207 B2_MAC_2 = 0x0108,
208 B2_MAC_3 = 0x0110,
209 B2_CONN_TYP = 0x0118,
210 B2_PMD_TYP = 0x0119,
211 B2_MAC_CFG = 0x011a,
212 B2_CHIP_ID = 0x011b,
213 B2_E_0 = 0x011c,
214
215 B2_Y2_CLK_GATE = 0x011d,
216 B2_Y2_HW_RES = 0x011e,
217 B2_E_3 = 0x011f,
218 B2_Y2_CLK_CTRL = 0x0120,
219
220 B2_TI_INI = 0x0130,
221 B2_TI_VAL = 0x0134,
222 B2_TI_CTRL = 0x0138,
223 B2_TI_TEST = 0x0139,
224
225 B2_TST_CTRL1 = 0x0158,
226 B2_TST_CTRL2 = 0x0159,
227 B2_GP_IO = 0x015c,
228
229 B2_I2C_CTRL = 0x0160,
230 B2_I2C_DATA = 0x0164,
231 B2_I2C_IRQ = 0x0168,
232 B2_I2C_SW = 0x016c,
233
234 B3_RAM_ADDR = 0x0180,
235 B3_RAM_DATA_LO = 0x0184,
236 B3_RAM_DATA_HI = 0x0188,
237
238 /* RAM Interface Registers */
239 /* Yukon-2: use RAM_BUFFER() to access the RAM buffer */
240 /*
241 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
242 * not usable in SW. Please notice these are NOT real timeouts, these are
243 * the number of qWords transferred continuously.
244 */
245 #define RAM_BUFFER(port, reg) (reg | (port <<6))
246
247 B3_RI_WTO_R1 = 0x0190,
248 B3_RI_WTO_XA1 = 0x0191,
249 B3_RI_WTO_XS1 = 0x0192,
250 B3_RI_RTO_R1 = 0x0193,
251 B3_RI_RTO_XA1 = 0x0194,
252 B3_RI_RTO_XS1 = 0x0195,
253 B3_RI_WTO_R2 = 0x0196,
254 B3_RI_WTO_XA2 = 0x0197,
255 B3_RI_WTO_XS2 = 0x0198,
256 B3_RI_RTO_R2 = 0x0199,
257 B3_RI_RTO_XA2 = 0x019a,
258 B3_RI_RTO_XS2 = 0x019b,
259 B3_RI_TO_VAL = 0x019c,
260 B3_RI_CTRL = 0x01a0,
261 B3_RI_TEST = 0x01a2,
262 B3_MA_TOINI_RX1 = 0x01b0,
263 B3_MA_TOINI_RX2 = 0x01b1,
264 B3_MA_TOINI_TX1 = 0x01b2,
265 B3_MA_TOINI_TX2 = 0x01b3,
266 B3_MA_TOVAL_RX1 = 0x01b4,
267 B3_MA_TOVAL_RX2 = 0x01b5,
268 B3_MA_TOVAL_TX1 = 0x01b6,
269 B3_MA_TOVAL_TX2 = 0x01b7,
270 B3_MA_TO_CTRL = 0x01b8,
271 B3_MA_TO_TEST = 0x01ba,
272 B3_MA_RCINI_RX1 = 0x01c0,
273 B3_MA_RCINI_RX2 = 0x01c1,
274 B3_MA_RCINI_TX1 = 0x01c2,
275 B3_MA_RCINI_TX2 = 0x01c3,
276 B3_MA_RCVAL_RX1 = 0x01c4,
277 B3_MA_RCVAL_RX2 = 0x01c5,
278 B3_MA_RCVAL_TX1 = 0x01c6,
279 B3_MA_RCVAL_TX2 = 0x01c7,
280 B3_MA_RC_CTRL = 0x01c8,
281 B3_MA_RC_TEST = 0x01ca,
282 B3_PA_TOINI_RX1 = 0x01d0,
283 B3_PA_TOINI_RX2 = 0x01d4,
284 B3_PA_TOINI_TX1 = 0x01d8,
285 B3_PA_TOINI_TX2 = 0x01dc,
286 B3_PA_TOVAL_RX1 = 0x01e0,
287 B3_PA_TOVAL_RX2 = 0x01e4,
288 B3_PA_TOVAL_TX1 = 0x01e8,
289 B3_PA_TOVAL_TX2 = 0x01ec,
290 B3_PA_CTRL = 0x01f0,
291 B3_PA_TEST = 0x01f2,
292
293 Y2_CFG_SPC = 0x1c00, /* PCI config space region */
294 Y2_CFG_AER = 0x1d00, /* PCI Advanced Error Report region */
295 };
296
297 /* B0_CTST 16 bit Control/Status register */
298 enum {
299 Y2_VMAIN_AVAIL = 1<<17,/* VMAIN available (YUKON-2 only) */
300 Y2_VAUX_AVAIL = 1<<16,/* VAUX available (YUKON-2 only) */
301 Y2_HW_WOL_ON = 1<<15,/* HW WOL On (Yukon-EC Ultra A1 only) */
302 Y2_HW_WOL_OFF = 1<<14,/* HW WOL On (Yukon-EC Ultra A1 only) */
303 Y2_ASF_ENABLE = 1<<13,/* ASF Unit Enable (YUKON-2 only) */
304 Y2_ASF_DISABLE = 1<<12,/* ASF Unit Disable (YUKON-2 only) */
305 Y2_CLK_RUN_ENA = 1<<11,/* CLK_RUN Enable (YUKON-2 only) */
306 Y2_CLK_RUN_DIS = 1<<10,/* CLK_RUN Disable (YUKON-2 only) */
307 Y2_LED_STAT_ON = 1<<9, /* Status LED On (YUKON-2 only) */
308 Y2_LED_STAT_OFF = 1<<8, /* Status LED Off (YUKON-2 only) */
309
310 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
311 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
312 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
313 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
314 CS_MRST_CLR = 1<<3, /* Clear Master reset */
315 CS_MRST_SET = 1<<2, /* Set Master reset */
316 CS_RST_CLR = 1<<1, /* Clear Software reset */
317 CS_RST_SET = 1, /* Set Software reset */
318 };
319
320 /* B0_LED 8 Bit LED register */
321 enum {
322 /* Bit 7.. 2: reserved */
323 LED_STAT_ON = 1<<1, /* Status LED on */
324 LED_STAT_OFF = 1, /* Status LED off */
325 };
326
327 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
328 enum {
329 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
330 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
331 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
332 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
333 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
334 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
335 PC_VCC_ON = 1<<1, /* Switch VCC On */
336 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
337 };
338
339 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
340
341 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */
342 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */
343 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */
344 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */
345 enum {
346 Y2_IS_HW_ERR = 1<<31, /* Interrupt HW Error */
347 Y2_IS_STAT_BMU = 1<<30, /* Status BMU Interrupt */
348 Y2_IS_ASF = 1<<29, /* ASF subsystem Interrupt */
349
350 Y2_IS_POLL_CHK = 1<<27, /* Check IRQ from polling unit */
351 Y2_IS_TWSI_RDY = 1<<26, /* IRQ on end of TWSI Tx */
352 Y2_IS_IRQ_SW = 1<<25, /* SW forced IRQ */
353 Y2_IS_TIMINT = 1<<24, /* IRQ from Timer */
354
355 Y2_IS_IRQ_PHY2 = 1<<12, /* Interrupt from PHY 2 */
356 Y2_IS_IRQ_MAC2 = 1<<11, /* Interrupt from MAC 2 */
357 Y2_IS_CHK_RX2 = 1<<10, /* Descriptor error Rx 2 */
358 Y2_IS_CHK_TXS2 = 1<<9, /* Descriptor error TXS 2 */
359 Y2_IS_CHK_TXA2 = 1<<8, /* Descriptor error TXA 2 */
360
361 Y2_IS_IRQ_PHY1 = 1<<4, /* Interrupt from PHY 1 */
362 Y2_IS_IRQ_MAC1 = 1<<3, /* Interrupt from MAC 1 */
363 Y2_IS_CHK_RX1 = 1<<2, /* Descriptor error Rx 1 */
364 Y2_IS_CHK_TXS1 = 1<<1, /* Descriptor error TXS 1 */
365 Y2_IS_CHK_TXA1 = 1<<0, /* Descriptor error TXA 1 */
366
367 Y2_IS_BASE = Y2_IS_HW_ERR | Y2_IS_STAT_BMU,
368 Y2_IS_PORT_1 = Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1
369 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1,
370 Y2_IS_PORT_2 = Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2
371 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
372 Y2_IS_ERROR = Y2_IS_HW_ERR |
373 Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1 |
374 Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2,
375 };
376
377 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
378 enum {
379 IS_ERR_MSK = 0x00003fff,/* All Error bits */
380
381 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
382 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
383 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
384 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
385 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
386 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
387 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
388 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
389 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
390 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
391 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
392 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
393 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
394 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
395 };
396
397 /* Hardware error interrupt mask for Yukon 2 */
398 enum {
399 Y2_IS_TIST_OV = 1<<29,/* Time Stamp Timer overflow interrupt */
400 Y2_IS_SENSOR = 1<<28, /* Sensor interrupt */
401 Y2_IS_MST_ERR = 1<<27, /* Master error interrupt */
402 Y2_IS_IRQ_STAT = 1<<26, /* Status exception interrupt */
403 Y2_IS_PCI_EXP = 1<<25, /* PCI-Express interrupt */
404 Y2_IS_PCI_NEXP = 1<<24, /* PCI-Express error similar to PCI error */
405 /* Link 2 */
406 Y2_IS_PAR_RD2 = 1<<13, /* Read RAM parity error interrupt */
407 Y2_IS_PAR_WR2 = 1<<12, /* Write RAM parity error interrupt */
408 Y2_IS_PAR_MAC2 = 1<<11, /* MAC hardware fault interrupt */
409 Y2_IS_PAR_RX2 = 1<<10, /* Parity Error Rx Queue 2 */
410 Y2_IS_TCP_TXS2 = 1<<9, /* TCP length mismatch sync Tx queue IRQ */
411 Y2_IS_TCP_TXA2 = 1<<8, /* TCP length mismatch async Tx queue IRQ */
412 /* Link 1 */
413 Y2_IS_PAR_RD1 = 1<<5, /* Read RAM parity error interrupt */
414 Y2_IS_PAR_WR1 = 1<<4, /* Write RAM parity error interrupt */
415 Y2_IS_PAR_MAC1 = 1<<3, /* MAC hardware fault interrupt */
416 Y2_IS_PAR_RX1 = 1<<2, /* Parity Error Rx Queue 1 */
417 Y2_IS_TCP_TXS1 = 1<<1, /* TCP length mismatch sync Tx queue IRQ */
418 Y2_IS_TCP_TXA1 = 1<<0, /* TCP length mismatch async Tx queue IRQ */
419
420 Y2_HWE_L1_MASK = Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |
421 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1,
422 Y2_HWE_L2_MASK = Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |
423 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2,
424
425 Y2_HWE_ALL_MASK = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT |
426 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK,
427 };
428
429 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */
430 enum {
431 DPT_START = 1<<1,
432 DPT_STOP = 1<<0,
433 };
434
435 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
436 enum {
437 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
438 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
439 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
440 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
441 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
442 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
443 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
444 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
445 };
446
447 /* B2_GPIO */
448 enum {
449 GLB_GPIO_CLK_DEB_ENA = 1<<31, /* Clock Debug Enable */
450 GLB_GPIO_CLK_DBG_MSK = 0xf<<26, /* Clock Debug */
451
452 GLB_GPIO_INT_RST_D3_DIS = 1<<15, /* Disable Internal Reset After D3 to D0 */
453 GLB_GPIO_LED_PAD_SPEED_UP = 1<<14, /* LED PAD Speed Up */
454 GLB_GPIO_STAT_RACE_DIS = 1<<13, /* Status Race Disable */
455 GLB_GPIO_TEST_SEL_MSK = 3<<11, /* Testmode Select */
456 GLB_GPIO_TEST_SEL_BASE = 1<<11,
457 GLB_GPIO_RAND_ENA = 1<<10, /* Random Enable */
458 GLB_GPIO_RAND_BIT_1 = 1<<9, /* Random Bit 1 */
459 };
460
461 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
462 enum {
463 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
464 /* Bit 3.. 2: reserved */
465 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
466 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
467 };
468
469 /* B2_CHIP_ID 8 bit Chip Identification Number */
470 enum {
471 CHIP_ID_YUKON_XL = 0xb3, /* YUKON-2 XL */
472 CHIP_ID_YUKON_EC_U = 0xb4, /* YUKON-2 EC Ultra */
473 CHIP_ID_YUKON_EX = 0xb5, /* YUKON-2 Extreme */
474 CHIP_ID_YUKON_EC = 0xb6, /* YUKON-2 EC */
475 CHIP_ID_YUKON_FE = 0xb7, /* YUKON-2 FE */
476 CHIP_ID_YUKON_FE_P = 0xb8, /* YUKON-2 FE+ */
477 CHIP_ID_YUKON_SUPR = 0xb9, /* YUKON-2 Supreme */
478 CHIP_ID_YUKON_UL_2 = 0xba, /* YUKON-2 Ultra 2 */
479 };
480 enum yukon_ec_rev {
481 CHIP_REV_YU_EC_A1 = 0, /* Chip Rev. for Yukon-EC A1/A0 */
482 CHIP_REV_YU_EC_A2 = 1, /* Chip Rev. for Yukon-EC A2 */
483 CHIP_REV_YU_EC_A3 = 2, /* Chip Rev. for Yukon-EC A3 */
484 };
485 enum yukon_ec_u_rev {
486 CHIP_REV_YU_EC_U_A0 = 1,
487 CHIP_REV_YU_EC_U_A1 = 2,
488 CHIP_REV_YU_EC_U_B0 = 3,
489 };
490 enum yukon_fe_rev {
491 CHIP_REV_YU_FE_A1 = 1,
492 CHIP_REV_YU_FE_A2 = 2,
493 };
494 enum yukon_fe_p_rev {
495 CHIP_REV_YU_FE2_A0 = 0,
496 };
497 enum yukon_ex_rev {
498 CHIP_REV_YU_EX_A0 = 1,
499 CHIP_REV_YU_EX_B0 = 2,
500 };
501 enum yukon_supr_rev {
502 CHIP_REV_YU_SU_A0 = 0,
503 };
504
505
506 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
507 enum {
508 Y2_STATUS_LNK2_INAC = 1<<7, /* Status Link 2 inactive (0 = active) */
509 Y2_CLK_GAT_LNK2_DIS = 1<<6, /* Disable clock gating Link 2 */
510 Y2_COR_CLK_LNK2_DIS = 1<<5, /* Disable Core clock Link 2 */
511 Y2_PCI_CLK_LNK2_DIS = 1<<4, /* Disable PCI clock Link 2 */
512 Y2_STATUS_LNK1_INAC = 1<<3, /* Status Link 1 inactive (0 = active) */
513 Y2_CLK_GAT_LNK1_DIS = 1<<2, /* Disable clock gating Link 1 */
514 Y2_COR_CLK_LNK1_DIS = 1<<1, /* Disable Core clock Link 1 */
515 Y2_PCI_CLK_LNK1_DIS = 1<<0, /* Disable PCI clock Link 1 */
516 };
517
518 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
519 enum {
520 CFG_LED_MODE_MSK = 7<<2, /* Bit 4.. 2: LED Mode Mask */
521 CFG_LINK_2_AVAIL = 1<<1, /* Link 2 available */
522 CFG_LINK_1_AVAIL = 1<<0, /* Link 1 available */
523 };
524 #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2)
525 #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL)
526
527
528 /* B2_Y2_CLK_CTRL 32 bit Clock Frequency Control Register (Yukon-2/EC) */
529 enum {
530 Y2_CLK_DIV_VAL_MSK = 0xff<<16,/* Bit 23..16: Clock Divisor Value */
531 #define Y2_CLK_DIV_VAL(x) (((x)<<16) & Y2_CLK_DIV_VAL_MSK)
532 Y2_CLK_DIV_VAL2_MSK = 7<<21, /* Bit 23..21: Clock Divisor Value */
533 Y2_CLK_SELECT2_MSK = 0x1f<<16,/* Bit 20..16: Clock Select */
534 #define Y2_CLK_DIV_VAL_2(x) (((x)<<21) & Y2_CLK_DIV_VAL2_MSK)
535 #define Y2_CLK_SEL_VAL_2(x) (((x)<<16) & Y2_CLK_SELECT2_MSK)
536 Y2_CLK_DIV_ENA = 1<<1, /* Enable Core Clock Division */
537 Y2_CLK_DIV_DIS = 1<<0, /* Disable Core Clock Division */
538 };
539
540 /* B2_TI_CTRL 8 bit Timer control */
541 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
542 enum {
543 TIM_START = 1<<2, /* Start Timer */
544 TIM_STOP = 1<<1, /* Stop Timer */
545 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
546 };
547
548 /* B2_TI_TEST 8 Bit Timer Test */
549 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
550 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
551 enum {
552 TIM_T_ON = 1<<2, /* Test mode on */
553 TIM_T_OFF = 1<<1, /* Test mode off */
554 TIM_T_STEP = 1<<0, /* Test step */
555 };
556
557 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
558 /* Bit 31..19: reserved */
559 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
560 /* RAM Interface Registers */
561
562 /* B3_RI_CTRL 16 bit RAM Interface Control Register */
563 enum {
564 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
565 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
566
567 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
568 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
569 };
570
571 #define SK_RI_TO_53 36 /* RAM interface timeout */
572
573
574 /* Port related registers FIFO, and Arbiter */
575 #define SK_REG(port,reg) (((port)<<7)+(reg))
576
577 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
578 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
579 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
580 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
581 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
582
583 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
584
585 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
586 enum {
587 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
588 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
589 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
590 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
591 TXA_START_RC = 1<<3, /* Start sync Rate Control */
592 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
593 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
594 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
595 };
596
597 /*
598 * Bank 4 - 5
599 */
600 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
601 enum {
602 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
603 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
604 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
605 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
606 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
607 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
608 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
609 };
610
611
612 enum {
613 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
614 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
615 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
616 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
617 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
618 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
619 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
620 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
621 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
622 };
623
624 /* Queue Register Offsets, use Q_ADDR() to access */
625 enum {
626 B8_Q_REGS = 0x0400, /* base of Queue registers */
627 Q_D = 0x00, /* 8*32 bit Current Descriptor */
628 Q_VLAN = 0x20, /* 16 bit Current VLAN Tag */
629 Q_DONE = 0x24, /* 16 bit Done Index */
630 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
631 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
632 Q_BC = 0x30, /* 32 bit Current Byte Counter */
633 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
634 Q_TEST = 0x38, /* 32 bit Test/Control Register */
635
636 /* Yukon-2 */
637 Q_WM = 0x40, /* 16 bit FIFO Watermark */
638 Q_AL = 0x42, /* 8 bit FIFO Alignment */
639 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
640 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
641 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
642 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
643 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
644 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
645 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
646 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
647 };
648 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
649
650 /* Q_TEST 32 bit Test Register */
651 enum {
652 /* Transmit */
653 F_TX_CHK_AUTO_OFF = 1<<31, /* Tx checksum auto calc off (Yukon EX) */
654 F_TX_CHK_AUTO_ON = 1<<30, /* Tx checksum auto calc off (Yukon EX) */
655
656 /* Receive */
657 F_M_RX_RAM_DIS = 1<<24, /* MAC Rx RAM Read Port disable */
658
659 /* Hardware testbits not used */
660 };
661
662 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
663 enum {
664 Y2_B8_PREF_REGS = 0x0450,
665
666 PREF_UNIT_CTRL = 0x00, /* 32 bit Control register */
667 PREF_UNIT_LAST_IDX = 0x04, /* 16 bit Last Index */
668 PREF_UNIT_ADDR_LO = 0x08, /* 32 bit List start addr, low part */
669 PREF_UNIT_ADDR_HI = 0x0c, /* 32 bit List start addr, high part*/
670 PREF_UNIT_GET_IDX = 0x10, /* 16 bit Get Index */
671 PREF_UNIT_PUT_IDX = 0x14, /* 16 bit Put Index */
672 PREF_UNIT_FIFO_WP = 0x20, /* 8 bit FIFO write pointer */
673 PREF_UNIT_FIFO_RP = 0x24, /* 8 bit FIFO read pointer */
674 PREF_UNIT_FIFO_WM = 0x28, /* 8 bit FIFO watermark */
675 PREF_UNIT_FIFO_LEV = 0x2c, /* 8 bit FIFO level */
676
677 PREF_UNIT_MASK_IDX = 0x0fff,
678 };
679 #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
680
681 /* RAM Buffer Register Offsets */
682 enum {
683
684 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
685 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
686 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
687 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
688 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
689 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
690 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
691 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
692 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
693 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
694 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
695 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
696 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
697 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
698 };
699
700 /* Receive and Transmit Queues */
701 enum {
702 Q_R1 = 0x0000, /* Receive Queue 1 */
703 Q_R2 = 0x0080, /* Receive Queue 2 */
704 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
705 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
706 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
707 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
708 };
709
710 /* Different PHY Types */
711 enum {
712 PHY_ADDR_MARV = 0,
713 };
714
715 #define RB_ADDR(offs, queue) ((u16) B16_RAM_REGS + (queue) + (offs))
716
717
718 enum {
719 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
720 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
721 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
722 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
723
724 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
725
726 /* Receive GMAC FIFO (YUKON and Yukon-2) */
727
728 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
729 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
730 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
731 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
732 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
733 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
734 RX_GMF_UP_THR = 0x0c58,/* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */
735 RX_GMF_LP_THR = 0x0c5a,/* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */
736 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
737 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
738
739 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
740
741 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
742
743 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
744 };
745
746
747 /* Q_BC 32 bit Current Byte Counter */
748
749 /* BMU Control Status Registers */
750 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
751 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
752 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
753 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
754 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
755 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
756 /* Q_CSR 32 bit BMU Control/Status Register */
757
758 /* Rx BMU Control / Status Registers (Yukon-2) */
759 enum {
760 BMU_IDLE = 1<<31, /* BMU Idle State */
761 BMU_RX_TCP_PKT = 1<<30, /* Rx TCP Packet (when RSS Hash enabled) */
762 BMU_RX_IP_PKT = 1<<29, /* Rx IP Packet (when RSS Hash enabled) */
763
764 BMU_ENA_RX_RSS_HASH = 1<<15, /* Enable Rx RSS Hash */
765 BMU_DIS_RX_RSS_HASH = 1<<14, /* Disable Rx RSS Hash */
766 BMU_ENA_RX_CHKSUM = 1<<13, /* Enable Rx TCP/IP Checksum Check */
767 BMU_DIS_RX_CHKSUM = 1<<12, /* Disable Rx TCP/IP Checksum Check */
768 BMU_CLR_IRQ_PAR = 1<<11, /* Clear IRQ on Parity errors (Rx) */
769 BMU_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment. error (Tx) */
770 BMU_CLR_IRQ_CHK = 1<<10, /* Clear IRQ Check */
771 BMU_STOP = 1<<9, /* Stop Rx/Tx Queue */
772 BMU_START = 1<<8, /* Start Rx/Tx Queue */
773 BMU_FIFO_OP_ON = 1<<7, /* FIFO Operational On */
774 BMU_FIFO_OP_OFF = 1<<6, /* FIFO Operational Off */
775 BMU_FIFO_ENA = 1<<5, /* Enable FIFO */
776 BMU_FIFO_RST = 1<<4, /* Reset FIFO */
777 BMU_OP_ON = 1<<3, /* BMU Operational On */
778 BMU_OP_OFF = 1<<2, /* BMU Operational Off */
779 BMU_RST_CLR = 1<<1, /* Clear BMU Reset (Enable) */
780 BMU_RST_SET = 1<<0, /* Set BMU Reset */
781
782 BMU_CLR_RESET = BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR,
783 BMU_OPER_INIT = BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | BMU_START |
784 BMU_FIFO_ENA | BMU_OP_ON,
785
786 BMU_WM_DEFAULT = 0x600,
787 BMU_WM_PEX = 0x80,
788 };
789
790 /* Tx BMU Control / Status Registers (Yukon-2) */
791 /* Bit 31: same as for Rx */
792 enum {
793 BMU_TX_IPIDINCR_ON = 1<<13, /* Enable IP ID Increment */
794 BMU_TX_IPIDINCR_OFF = 1<<12, /* Disable IP ID Increment */
795 BMU_TX_CLR_IRQ_TCP = 1<<11, /* Clear IRQ on TCP segment length mismatch */
796 };
797
798 /* Queue Prefetch Unit Offsets, use Y2_QADDR() to address (Yukon-2 only)*/
799 /* PREF_UNIT_CTRL 32 bit Prefetch Control register */
800 enum {
801 PREF_UNIT_OP_ON = 1<<3, /* prefetch unit operational */
802 PREF_UNIT_OP_OFF = 1<<2, /* prefetch unit not operational */
803 PREF_UNIT_RST_CLR = 1<<1, /* Clear Prefetch Unit Reset */
804 PREF_UNIT_RST_SET = 1<<0, /* Set Prefetch Unit Reset */
805 };
806
807 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
808 /* RB_START 32 bit RAM Buffer Start Address */
809 /* RB_END 32 bit RAM Buffer End Address */
810 /* RB_WP 32 bit RAM Buffer Write Pointer */
811 /* RB_RP 32 bit RAM Buffer Read Pointer */
812 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
813 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
814 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
815 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
816 /* RB_PC 32 bit RAM Buffer Packet Counter */
817 /* RB_LEV 32 bit RAM Buffer Level Register */
818
819 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
820 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
821 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
822
823 /* RB_CTRL 8 bit RAM Buffer Control Register */
824 enum {
825 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
826 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
827 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
828 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
829 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
830 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
831 };
832
833
834 /* Transmit GMAC FIFO (YUKON only) */
835 enum {
836 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
837 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
838 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
839
840 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
841 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
842 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
843
844 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
845 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
846 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
847
848 /* Threshold values for Yukon-EC Ultra and Extreme */
849 ECU_AE_THR = 0x0070, /* Almost Empty Threshold */
850 ECU_TXFF_LEV = 0x01a0, /* Tx BMU FIFO Level */
851 ECU_JUMBO_WM = 0x0080, /* Jumbo Mode Watermark */
852 };
853
854 /* Descriptor Poll Timer Registers */
855 enum {
856 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
857 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
858 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
859
860 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
861 };
862
863 /* Time Stamp Timer Registers (YUKON only) */
864 enum {
865 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
866 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
867 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
868 };
869
870 /* Polling Unit Registers (Yukon-2 only) */
871 enum {
872 POLL_CTRL = 0x0e20, /* 32 bit Polling Unit Control Reg */
873 POLL_LAST_IDX = 0x0e24,/* 16 bit Polling Unit List Last Index */
874
875 POLL_LIST_ADDR_LO= 0x0e28,/* 32 bit Poll. List Start Addr (low) */
876 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
877 };
878
879 enum {
880 SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */
881 SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */
882 };
883
884 enum {
885 CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */
886 CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */
887 CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */
888 CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */
889 CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */
890 CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */
891 HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */
892 CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */
893 HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */
894 HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */
895 };
896
897 /* ASF Subsystem Registers (Yukon-2 only) */
898 enum {
899 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
900 B28_Y2_SMB_CSD_REG = 0x0e44,/* 32 bit ASF SMB Control/Status/Data */
901 B28_Y2_ASF_IRQ_V_BASE=0x0e60,/* 32 bit ASF IRQ Vector Base */
902
903 B28_Y2_ASF_STAT_CMD= 0x0e68,/* 32 bit ASF Status and Command Reg */
904 B28_Y2_ASF_HOST_COM= 0x0e6c,/* 32 bit ASF Host Communication Reg */
905 B28_Y2_DATA_REG_1 = 0x0e70,/* 32 bit ASF/Host Data Register 1 */
906 B28_Y2_DATA_REG_2 = 0x0e74,/* 32 bit ASF/Host Data Register 2 */
907 B28_Y2_DATA_REG_3 = 0x0e78,/* 32 bit ASF/Host Data Register 3 */
908 B28_Y2_DATA_REG_4 = 0x0e7c,/* 32 bit ASF/Host Data Register 4 */
909 };
910
911 /* Status BMU Registers (Yukon-2 only)*/
912 enum {
913 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
914 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
915
916 STAT_LIST_ADDR_LO= 0x0e88,/* 32 bit Status List Start Addr (low) */
917 STAT_LIST_ADDR_HI= 0x0e8c,/* 32 bit Status List Start Addr (high) */
918 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
919 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
920 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
921 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
922 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
923 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
924
925 /* FIFO Control/Status Registers (Yukon-2 only)*/
926 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
927 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
928 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
929 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
930 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
931 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
932 STAT_FIFO_ISR_WM= 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
933
934 /* Level and ISR Timer Registers (Yukon-2 only)*/
935 STAT_LEV_TIMER_INI= 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
936 STAT_LEV_TIMER_CNT= 0x0eb4,/* 32 bit Level Timer Counter Reg */
937 STAT_LEV_TIMER_CTRL= 0x0eb8,/* 8 bit Level Timer Control Reg */
938 STAT_LEV_TIMER_TEST= 0x0eb9,/* 8 bit Level Timer Test Reg */
939 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
940 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
941 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
942 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
943 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
944 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
945 STAT_ISR_TIMER_CTRL= 0x0ed8,/* 8 bit ISR Timer Control Reg */
946 STAT_ISR_TIMER_TEST= 0x0ed9,/* 8 bit ISR Timer Test Reg */
947 };
948
949 enum {
950 LINKLED_OFF = 0x01,
951 LINKLED_ON = 0x02,
952 LINKLED_LINKSYNC_OFF = 0x04,
953 LINKLED_LINKSYNC_ON = 0x08,
954 LINKLED_BLINK_OFF = 0x10,
955 LINKLED_BLINK_ON = 0x20,
956 };
957
958 /* GMAC and GPHY Control Registers (YUKON only) */
959 enum {
960 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
961 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
962 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
963 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
964 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
965
966 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
967 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
968 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
969 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
970 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
971 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
972
973 /* WOL Pattern Length Registers (YUKON only) */
974 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
975 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
976
977 /* WOL Pattern Counter Registers (YUKON only) */
978 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
979 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
980 };
981 #define WOL_REGS(port, x) (x + (port)*0x80)
982
983 enum {
984 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
985 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
986 };
987 #define WOL_PATT_RAM_BASE(port) (WOL_PATT_RAM_1 + (port)*0x400)
988
989 enum {
990 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
991 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
992 };
993
994 /*
995 * Marvel-PHY Registers, indirect addressed over GMAC
996 */
997 enum {
998 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
999 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1000 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1001 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1002 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1003 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1004 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1005 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1006 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1007 /* Marvel-specific registers */
1008 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1009 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1010 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1011 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
1012 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
1013 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
1014 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
1015 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
1016 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
1017 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1018 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1019 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1020 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1021 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1022 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1023 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1024 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1025 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1026
1027 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1028 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1029 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1030 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1031 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1032 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1033 };
1034
1035 enum {
1036 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1037 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1038 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1039 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1040 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1041 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1042 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1043 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1044 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
1045 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1046 };
1047
1048 enum {
1049 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1050 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
1051 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
1052 };
1053
1054 enum {
1055 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
1056
1057 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
1058 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1059 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
1060 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1061 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
1062 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
1063 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
1064 };
1065
1066 enum {
1067 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1068 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
1069 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
1070 };
1071
1072 /* different Marvell PHY Ids */
1073 enum {
1074 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1075
1076 PHY_BCOM_ID1_A1 = 0x6041,
1077 PHY_BCOM_ID1_B2 = 0x6043,
1078 PHY_BCOM_ID1_C0 = 0x6044,
1079 PHY_BCOM_ID1_C5 = 0x6047,
1080
1081 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
1082 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1083 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1084 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1085 PHY_MARV_ID1_FE = 0x0C83, /* Yukon-FE (PHY 88E3082 Rev.A1) */
1086 PHY_MARV_ID1_ECU= 0x0CB0, /* Yukon-ECU (PHY 88E1149 Rev.B2?) */
1087 };
1088
1089 /* Advertisement register bits */
1090 enum {
1091 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1092 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1093 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
1094
1095 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1096 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
1097 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
1098 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1099 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1100 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1101 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1102 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
1103 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1104 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1105 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
1106 PHY_AN_100HALF | PHY_AN_100FULL,
1107 };
1108
1109 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1110 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1111 enum {
1112 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1113 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1114 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1115 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1116 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1117 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1118 /* Bit 9..8: reserved */
1119 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1120 };
1121
1122 /** Marvell-Specific */
1123 enum {
1124 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
1125 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
1126 PHY_M_AN_RF = 1<<13, /* Remote Fault */
1127
1128 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1129 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
1130 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1131 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1132 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1133 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1134 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1135 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1136 };
1137
1138 /* special defines for FIBER (88E1011S only) */
1139 enum {
1140 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1141 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1142 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1143 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1144 };
1145
1146 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1147 enum {
1148 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1149 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1150 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1151 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1152 };
1153
1154 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1155 enum {
1156 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1157 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1158 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1159 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1160 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1161 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1162 };
1163
1164 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1165 enum {
1166 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1167 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1168 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1169 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1170 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1171 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1172 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1173 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1174 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1175 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1176 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1177 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1178 };
1179
1180 enum {
1181 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1182 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1183 };
1184
1185 #define PHY_M_PC_MDI_XMODE(x) (((u16)(x)<<5) & PHY_M_PC_MDIX_MSK)
1186
1187 enum {
1188 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1189 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1190 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1191 };
1192
1193 /* for Yukon-EC Ultra Gigabit Ethernet PHY (88E1149 only) */
1194 enum {
1195 PHY_M_PC_COP_TX_DIS = 1<<3, /* Copper Transmitter Disable */
1196 PHY_M_PC_POW_D_ENA = 1<<2, /* Power Down Enable */
1197 };
1198
1199 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1200 enum {
1201 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1202 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1203 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1204 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1205 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1206
1207 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1208 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1209
1210 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1211 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1212 };
1213
1214 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1215 enum {
1216 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1217 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1218 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1219 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1220 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1221 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1222 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1223 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1224 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1225 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1226 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1227 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1228 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1229 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1230 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1231 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1232 };
1233
1234 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1235
1236 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1237 enum {
1238 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1239 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1240 };
1241
1242 enum {
1243 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1244 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1245 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1246 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1247 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1248 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1249 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1250 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1251 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1252 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1253 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1254 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1255
1256 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1257 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1258 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1259
1260 PHY_M_DEF_MSK = PHY_M_IS_LSP_CHANGE | PHY_M_IS_LST_CHANGE
1261 | PHY_M_IS_DUP_CHANGE,
1262 PHY_M_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1263 };
1264
1265
1266 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1267 enum {
1268 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1269 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1270
1271 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1272 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1273 /* (88E1011 only) */
1274 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1275 /* (88E1011 only) */
1276 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1277 /* (88E1111 only) */
1278 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1279 /* !!! Errata in spec. (1 = disable) */
1280 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1281 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1282 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1283 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1284 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1285 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1286
1287 #define PHY_M_EC_M_DSC(x) ((u16)(x)<<10 & PHY_M_EC_M_DSC_MSK)
1288 /* 00=1x; 01=2x; 10=3x; 11=4x */
1289 #define PHY_M_EC_S_DSC(x) ((u16)(x)<<8 & PHY_M_EC_S_DSC_MSK)
1290 /* 00=dis; 01=1x; 10=2x; 11=3x */
1291 #define PHY_M_EC_DSC_2(x) ((u16)(x)<<9 & PHY_M_EC_M_DSC_MSK2)
1292 /* 000=1x; 001=2x; 010=3x; 011=4x */
1293 #define PHY_M_EC_MAC_S(x) ((u16)(x)<<4 & PHY_M_EC_MAC_S_MSK)
1294 /* 01X=0; 110=2.5; 111=25 (MHz) */
1295
1296 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1297 enum {
1298 PHY_M_PC_DIS_LINK_Pa = 1<<15,/* Disable Link Pulses */
1299 PHY_M_PC_DSC_MSK = 7<<12,/* Bit 14..12: Downshift Counter */
1300 PHY_M_PC_DOWN_S_ENA = 1<<11,/* Downshift Enable */
1301 };
1302 /* !!! Errata in spec. (1 = disable) */
1303
1304 #define PHY_M_PC_DSC(x) (((u16)(x)<<12) & PHY_M_PC_DSC_MSK)
1305 /* 100=5x; 101=6x; 110=7x; 111=8x */
1306 enum {
1307 MAC_TX_CLK_0_MHZ = 2,
1308 MAC_TX_CLK_2_5_MHZ = 6,
1309 MAC_TX_CLK_25_MHZ = 7,
1310 };
1311
1312 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1313 enum {
1314 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1315 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1316 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1317 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1318 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1319 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1320 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1321 /* (88E1111 only) */
1322 };
1323
1324 enum {
1325 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1326 /* (88E1011 only) */
1327 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1328 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1329 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1330 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1331 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1332 };
1333
1334 #define PHY_M_LED_PULS_DUR(x) (((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
1335
1336 /***** PHY_MARV_PHY_STAT (page 3)16 bit r/w Polarity Control Reg. *****/
1337 enum {
1338 PHY_M_POLC_LS1M_MSK = 0xf<<12, /* Bit 15..12: LOS,STAT1 Mix % Mask */
1339 PHY_M_POLC_IS0M_MSK = 0xf<<8, /* Bit 11.. 8: INIT,STAT0 Mix % Mask */
1340 PHY_M_POLC_LOS_MSK = 0x3<<6, /* Bit 7.. 6: LOS Pol. Ctrl. Mask */
1341 PHY_M_POLC_INIT_MSK = 0x3<<4, /* Bit 5.. 4: INIT Pol. Ctrl. Mask */
1342 PHY_M_POLC_STA1_MSK = 0x3<<2, /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */
1343 PHY_M_POLC_STA0_MSK = 0x3, /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */
1344 };
1345
1346 #define PHY_M_POLC_LS1_P_MIX(x) (((x)<<12) & PHY_M_POLC_LS1M_MSK)
1347 #define PHY_M_POLC_IS0_P_MIX(x) (((x)<<8) & PHY_M_POLC_IS0M_MSK)
1348 #define PHY_M_POLC_LOS_CTRL(x) (((x)<<6) & PHY_M_POLC_LOS_MSK)
1349 #define PHY_M_POLC_INIT_CTRL(x) (((x)<<4) & PHY_M_POLC_INIT_MSK)
1350 #define PHY_M_POLC_STA1_CTRL(x) (((x)<<2) & PHY_M_POLC_STA1_MSK)
1351 #define PHY_M_POLC_STA0_CTRL(x) (((x)<<0) & PHY_M_POLC_STA0_MSK)
1352
1353 enum {
1354 PULS_NO_STR = 0,/* no pulse stretching */
1355 PULS_21MS = 1,/* 21 ms to 42 ms */
1356 PULS_42MS = 2,/* 42 ms to 84 ms */
1357 PULS_84MS = 3,/* 84 ms to 170 ms */
1358 PULS_170MS = 4,/* 170 ms to 340 ms */
1359 PULS_340MS = 5,/* 340 ms to 670 ms */
1360 PULS_670MS = 6,/* 670 ms to 1.3 s */
1361 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1362 };
1363
1364 #define PHY_M_LED_BLINK_RT(x) (((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
1365
1366 enum {
1367 BLINK_42MS = 0,/* 42 ms */
1368 BLINK_84MS = 1,/* 84 ms */
1369 BLINK_170MS = 2,/* 170 ms */
1370 BLINK_340MS = 3,/* 340 ms */
1371 BLINK_670MS = 4,/* 670 ms */
1372 };
1373
1374 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1375 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1376
1377 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1378 #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1379 #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1380 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1381 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1382 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1383
1384 enum led_mode {
1385 MO_LED_NORM = 0,
1386 MO_LED_BLINK = 1,
1387 MO_LED_OFF = 2,
1388 MO_LED_ON = 3,
1389 };
1390
1391 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1392 enum {
1393 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1394 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1395 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1396 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1397 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1398 };
1399
1400 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1401 enum {
1402 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1403 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1404 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1405 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1406 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1407 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1408 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1409 /* (88E1111 only) */
1410
1411 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1412 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1413 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1414 };
1415
1416 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1417 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1418 /* Bit 15..12: reserved (used internally) */
1419 enum {
1420 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1421 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1422 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1423 };
1424
1425 #define PHY_M_FELP_LED2_CTRL(x) (((u16)(x)<<8) & PHY_M_FELP_LED2_MSK)
1426 #define PHY_M_FELP_LED1_CTRL(x) (((u16)(x)<<4) & PHY_M_FELP_LED1_MSK)
1427 #define PHY_M_FELP_LED0_CTRL(x) (((u16)(x)<<0) & PHY_M_FELP_LED0_MSK)
1428
1429 enum {
1430 LED_PAR_CTRL_COLX = 0x00,
1431 LED_PAR_CTRL_ERROR = 0x01,
1432 LED_PAR_CTRL_DUPLEX = 0x02,
1433 LED_PAR_CTRL_DP_COL = 0x03,
1434 LED_PAR_CTRL_SPEED = 0x04,
1435 LED_PAR_CTRL_LINK = 0x05,
1436 LED_PAR_CTRL_TX = 0x06,
1437 LED_PAR_CTRL_RX = 0x07,
1438 LED_PAR_CTRL_ACT = 0x08,
1439 LED_PAR_CTRL_LNK_RX = 0x09,
1440 LED_PAR_CTRL_LNK_AC = 0x0a,
1441 LED_PAR_CTRL_ACT_BL = 0x0b,
1442 LED_PAR_CTRL_TX_BL = 0x0c,
1443 LED_PAR_CTRL_RX_BL = 0x0d,
1444 LED_PAR_CTRL_COL_BL = 0x0e,
1445 LED_PAR_CTRL_INACT = 0x0f
1446 };
1447
1448 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1449 enum {
1450 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1451 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1452 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1453 };
1454
1455 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1456 /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/
1457 enum {
1458 PHY_M_FIB_FORCE_LNK = 1<<10,/* Force Link Good */
1459 PHY_M_FIB_SIGD_POL = 1<<9, /* SIGDET Polarity */
1460 PHY_M_FIB_TX_DIS = 1<<3, /* Transmitter Disable */
1461 };
1462
1463 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1464 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1465 enum {
1466 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1467 PHY_M_MAC_GMIF_PUP = 1<<3, /* GMII Power Up (88E1149 only) */
1468 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1469 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1470 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1471 };
1472 #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1473
1474 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1475 enum {
1476 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1477 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1478 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1479 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1480 };
1481
1482 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1483 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1484 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1485 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1486
1487 /* GMAC registers */
1488 /* Port Registers */
1489 enum {
1490 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1491 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1492 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1493 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1494 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1495 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1496 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1497 /* Source Address Registers */
1498 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1499 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1500 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1501 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1502 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1503 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1504
1505 /* Multicast Address Hash Registers */
1506 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1507 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1508 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1509 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1510
1511 /* Interrupt Source Registers */
1512 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1513 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1514 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1515
1516 /* Interrupt Mask Registers */
1517 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1518 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1519 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1520
1521 /* Serial Management Interface (SMI) Registers */
1522 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1523 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1524 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1525 /* MIB Counters */
1526 GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */
1527 GM_MIB_CNT_END = 0x025C, /* Last MIB counter */
1528 };
1529
1530
1531 /*
1532 * MIB Counters base address definitions (low word) -
1533 * use offset 4 for access to high word (32 bit r/o)
1534 */
1535 enum {
1536 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1537 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1538 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1539 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1540 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1541
1542 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1543 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1544 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1545 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1546 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1547 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1548 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1549 GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */
1550 GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */
1551 GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */
1552 GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */
1553 GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */
1554 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */
1555 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */
1556 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */
1557
1558 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */
1559 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */
1560 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */
1561 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */
1562 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */
1563 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */
1564 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */
1565 GM_TXF_64B = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */
1566 GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */
1567 GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */
1568 GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */
1569 GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */
1570 GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */
1571 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */
1572
1573 GM_TXF_COL = GM_MIB_CNT_BASE + 304,/* Tx Collision */
1574 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */
1575 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */
1576 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */
1577 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */
1578 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */
1579 };
1580
1581 /* GMAC Bit Definitions */
1582 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1583 enum {
1584 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1585 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1586 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1587 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1588 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1589 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1590 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
1591 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
1592
1593 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1594 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1595 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1596 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1597 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1598 };
1599
1600 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1601 enum {
1602 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1603 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1604 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1605 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1606 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1607 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1608 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1609 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1610 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1611 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1612 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1613 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1614 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1615 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1616 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1617 };
1618
1619 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1620 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1621
1622 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1623 enum {
1624 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1625 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1626 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1627 GM_TXCR_COL_THR_MSK = 7<<10, /* Bit 12..10: Collision Threshold */
1628 };
1629
1630 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1631 #define TX_COL_DEF 0x04
1632
1633 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1634 enum {
1635 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1636 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1637 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1638 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1639 };
1640
1641 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1642 enum {
1643 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1644 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1645 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1646 GM_TXPA_BO_LIM_MSK = 0x0f, /* Bit 3.. 0: Backoff Limit Mask */
1647
1648 TX_JAM_LEN_DEF = 0x03,
1649 TX_JAM_IPG_DEF = 0x0b,
1650 TX_IPG_JAM_DEF = 0x1c,
1651 TX_BOF_LIM_DEF = 0x04,
1652 };
1653
1654 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1655 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1656 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1657 #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK)
1658
1659
1660 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1661 enum {
1662 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1663 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1664 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1665 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1666 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1667 };
1668
1669 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1670 #define DATA_BLIND_DEF 0x04
1671
1672 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1673 #define IPG_DATA_DEF 0x1e
1674
1675 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1676 enum {
1677 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
1678 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
1679 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1680 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1681 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1682 };
1683
1684 #define GM_SMI_CT_PHY_AD(x) (((u16)(x)<<11) & GM_SMI_CT_PHY_A_MSK)
1685 #define GM_SMI_CT_REG_AD(x) (((u16)(x)<<6) & GM_SMI_CT_REG_A_MSK)
1686
1687 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1688 enum {
1689 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1690 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1691 };
1692
1693 /* Receive Frame Status Encoding */
1694 enum {
1695 GMR_FS_LEN = 0x7fff<<16, /* Bit 30..16: Rx Frame Length */
1696 GMR_FS_VLAN = 1<<13, /* VLAN Packet */
1697 GMR_FS_JABBER = 1<<12, /* Jabber Packet */
1698 GMR_FS_UN_SIZE = 1<<11, /* Undersize Packet */
1699 GMR_FS_MC = 1<<10, /* Multicast Packet */
1700 GMR_FS_BC = 1<<9, /* Broadcast Packet */
1701 GMR_FS_RX_OK = 1<<8, /* Receive OK (Good Packet) */
1702 GMR_FS_GOOD_FC = 1<<7, /* Good Flow-Control Packet */
1703 GMR_FS_BAD_FC = 1<<6, /* Bad Flow-Control Packet */
1704 GMR_FS_MII_ERR = 1<<5, /* MII Error */
1705 GMR_FS_LONG_ERR = 1<<4, /* Too Long Packet */
1706 GMR_FS_FRAGMENT = 1<<3, /* Fragment */
1707
1708 GMR_FS_CRC_ERR = 1<<1, /* CRC Error */
1709 GMR_FS_RX_FF_OV = 1<<0, /* Rx FIFO Overflow */
1710
1711 GMR_FS_ANY_ERR = GMR_FS_RX_FF_OV | GMR_FS_CRC_ERR |
1712 GMR_FS_FRAGMENT | GMR_FS_LONG_ERR |
1713 GMR_FS_MII_ERR | GMR_FS_BAD_FC |
1714 GMR_FS_UN_SIZE | GMR_FS_JABBER,
1715 };
1716
1717 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1718 enum {
1719 RX_TRUNC_ON = 1<<27, /* enable packet truncation */
1720 RX_TRUNC_OFF = 1<<26, /* disable packet truncation */
1721 RX_VLAN_STRIP_ON = 1<<25, /* enable VLAN stripping */
1722 RX_VLAN_STRIP_OFF = 1<<24, /* disable VLAN stripping */
1723
1724 RX_MACSEC_FLUSH_ON = 1<<23,
1725 RX_MACSEC_FLUSH_OFF = 1<<22,
1726 RX_MACSEC_ASF_FLUSH_ON = 1<<21,
1727 RX_MACSEC_ASF_FLUSH_OFF = 1<<20,
1728
1729 GMF_RX_OVER_ON = 1<<19, /* enable flushing on receive overrun */
1730 GMF_RX_OVER_OFF = 1<<18, /* disable flushing on receive overrun */
1731 GMF_ASF_RX_OVER_ON = 1<<17, /* enable flushing of ASF when overrun */
1732 GMF_ASF_RX_OVER_OFF = 1<<16, /* disable flushing of ASF when overrun */
1733
1734 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1735 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1736 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1737
1738 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1739 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1740 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1741 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1742 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1743 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1744 GMF_CLI_RX_C = 1<<4, /* Clear IRQ Rx Frame Complete */
1745
1746 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1747 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1748 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1749 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1750
1751 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1752
1753 GMF_RX_CTRL_DEF = GMF_OPER_ON | GMF_RX_F_FL_ON,
1754 };
1755
1756 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */
1757 enum {
1758 TX_DYN_WM_ENA = 3, /* Yukon-FE+ specific */
1759 };
1760
1761 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1762 enum {
1763 TX_STFW_DIS = 1<<31,/* Disable Store & Forward (Yukon-EC Ultra) */
1764 TX_STFW_ENA = 1<<30,/* Enable Store & Forward (Yukon-EC Ultra) */
1765
1766 TX_VLAN_TAG_ON = 1<<25,/* enable VLAN tagging */
1767 TX_VLAN_TAG_OFF = 1<<24,/* disable VLAN tagging */
1768
1769 TX_JUMBO_ENA = 1<<23,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
1770 TX_JUMBO_DIS = 1<<22,/* PCI Jumbo Mode enable (Yukon-EC Ultra) */
1771
1772 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
1773 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
1774 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
1775
1776 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1777 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1778 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1779 };
1780
1781 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1782 enum {
1783 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1784 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1785 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1786 };
1787
1788 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */
1789 enum {
1790 Y2_ASF_OS_PRES = 1<<4, /* ASF operation system present */
1791 Y2_ASF_RESET = 1<<3, /* ASF system in reset state */
1792 Y2_ASF_RUNNING = 1<<2, /* ASF system operational */
1793 Y2_ASF_CLR_HSTI = 1<<1, /* Clear ASF IRQ */
1794 Y2_ASF_IRQ = 1<<0, /* Issue an IRQ to ASF system */
1795
1796 Y2_ASF_UC_STATE = 3<<2, /* ASF uC State */
1797 Y2_ASF_CLK_HALT = 0, /* ASF system clock stopped */
1798 };
1799
1800 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */
1801 enum {
1802 Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
1803 Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
1804 };
1805 /* HCU_CCSR CPU Control and Status Register */
1806 enum {
1807 HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */
1808 HCU_CCSR_CPU_SLEEP = 1<<26, /* CPU sleep status */
1809 /* Clock Stretching Timeout */
1810 HCU_CCSR_CS_TO = 1<<25,
1811 HCU_CCSR_WDOG = 1<<24, /* Watchdog Reset */
1812
1813 HCU_CCSR_CLR_IRQ_HOST = 1<<17, /* Clear IRQ_HOST */
1814 HCU_CCSR_SET_IRQ_HCU = 1<<16, /* Set IRQ_HCU */
1815
1816 HCU_CCSR_AHB_RST = 1<<9, /* Reset AHB bridge */
1817 HCU_CCSR_CPU_RST_MODE = 1<<8, /* CPU Reset Mode */
1818
1819 HCU_CCSR_SET_SYNC_CPU = 1<<5,
1820 HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */
1821 HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3,
1822 HCU_CCSR_OS_PRSNT = 1<<2, /* ASF OS Present */
1823 /* Microcontroller State */
1824 HCU_CCSR_UC_STATE_MSK = 3,
1825 HCU_CCSR_UC_STATE_BASE = 1<<0,
1826 HCU_CCSR_ASF_RESET = 0,
1827 HCU_CCSR_ASF_HALTED = 1<<1,
1828 HCU_CCSR_ASF_RUNNING = 1<<0,
1829 };
1830
1831 /* HCU_HCSR Host Control and Status Register */
1832 enum {
1833 HCU_HCSR_SET_IRQ_CPU = 1<<16, /* Set IRQ_CPU */
1834
1835 HCU_HCSR_CLR_IRQ_HCU = 1<<1, /* Clear IRQ_HCU */
1836 HCU_HCSR_SET_IRQ_HOST = 1<<0, /* Set IRQ_HOST */
1837 };
1838
1839 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
1840 enum {
1841 SC_STAT_CLR_IRQ = 1<<4, /* Status Burst IRQ clear */
1842 SC_STAT_OP_ON = 1<<3, /* Operational Mode On */
1843 SC_STAT_OP_OFF = 1<<2, /* Operational Mode Off */
1844 SC_STAT_RST_CLR = 1<<1, /* Clear Status Unit Reset (Enable) */
1845 SC_STAT_RST_SET = 1<<0, /* Set Status Unit Reset */
1846 };
1847
1848 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1849 enum {
1850 GMC_SET_RST = 1<<15,/* MAC SEC RST */
1851 GMC_SEC_RST_OFF = 1<<14,/* MAC SEC RSt OFF */
1852 GMC_BYP_MACSECRX_ON = 1<<13,/* Bypass macsec RX */
1853 GMC_BYP_MACSECRX_OFF= 1<<12,/* Bypass macsec RX off */
1854 GMC_BYP_MACSECTX_ON = 1<<11,/* Bypass macsec TX */
1855 GMC_BYP_MACSECTX_OFF= 1<<10,/* Bypass macsec TX off*/
1856 GMC_BYP_RETR_ON = 1<<9, /* Bypass retransmit FIFO On */
1857 GMC_BYP_RETR_OFF= 1<<8, /* Bypass retransmit FIFO Off */
1858
1859 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1860 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1861 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1862 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1863 GMC_PAUSE_ON = 1<<3, /* Pause On */
1864 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1865 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1866 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1867 };
1868
1869 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1870 enum {
1871 GPC_TX_PAUSE = 1<<30, /* Tx pause enabled (ro) */
1872 GPC_RX_PAUSE = 1<<29, /* Rx pause enabled (ro) */
1873 GPC_SPEED = 3<<27, /* PHY speed (ro) */
1874 GPC_LINK = 1<<26, /* Link up (ro) */
1875 GPC_DUPLEX = 1<<25, /* Duplex (ro) */
1876 GPC_CLOCK = 1<<24, /* 125Mhz clock stable (ro) */
1877
1878 GPC_PDOWN = 1<<23, /* Internal regulator 2.5 power down */
1879 GPC_TSTMODE = 1<<22, /* Test mode */
1880 GPC_REG18 = 1<<21, /* Reg18 Power down */
1881 GPC_REG12SEL = 3<<19, /* Reg12 power setting */
1882 GPC_REG18SEL = 3<<17, /* Reg18 power setting */
1883 GPC_SPILOCK = 1<<16, /* SPI lock (ASF) */
1884
1885 GPC_LEDMUX = 3<<14, /* LED Mux */
1886 GPC_INTPOL = 1<<13, /* Interrupt polarity */
1887 GPC_DETECT = 1<<12, /* Energy detect */
1888 GPC_1000HD = 1<<11, /* Enable 1000Mbit HD */
1889 GPC_SLAVE = 1<<10, /* Slave mode */
1890 GPC_PAUSE = 1<<9, /* Pause enable */
1891 GPC_LEDCTL = 3<<6, /* GPHY Leds */
1892
1893 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1894 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1895 };
1896
1897 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1898 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
1899 enum {
1900 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
1901 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
1902 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
1903 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
1904 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
1905 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
1906
1907 #define GMAC_DEF_MSK GM_IS_TX_FF_UR
1908 };
1909
1910 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
1911 enum { /* Bits 15.. 2: reserved */
1912 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
1913 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
1914 };
1915
1916
1917 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1918 enum {
1919 WOL_CTL_LINK_CHG_OCC = 1<<15,
1920 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
1921 WOL_CTL_PATTERN_OCC = 1<<13,
1922 WOL_CTL_CLEAR_RESULT = 1<<12,
1923 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
1924 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
1925 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
1926 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
1927 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
1928 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
1929 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
1930 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
1931 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
1932 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
1933 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
1934 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
1935 };
1936
1937
1938 /* Control flags */
1939 enum {
1940 UDPTCP = 1<<0,
1941 CALSUM = 1<<1,
1942 WR_SUM = 1<<2,
1943 INIT_SUM= 1<<3,
1944 LOCK_SUM= 1<<4,
1945 INS_VLAN= 1<<5,
1946 EOP = 1<<7,
1947 };
1948
1949 enum {
1950 HW_OWNER = 1<<7,
1951 OP_TCPWRITE = 0x11,
1952 OP_TCPSTART = 0x12,
1953 OP_TCPINIT = 0x14,
1954 OP_TCPLCK = 0x18,
1955 OP_TCPCHKSUM = OP_TCPSTART,
1956 OP_TCPIS = OP_TCPINIT | OP_TCPSTART,
1957 OP_TCPLW = OP_TCPLCK | OP_TCPWRITE,
1958 OP_TCPLSW = OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE,
1959 OP_TCPLISW = OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE,
1960
1961 OP_ADDR64 = 0x21,
1962 OP_VLAN = 0x22,
1963 OP_ADDR64VLAN = OP_ADDR64 | OP_VLAN,
1964 OP_LRGLEN = 0x24,
1965 OP_LRGLENVLAN = OP_LRGLEN | OP_VLAN,
1966 OP_MSS = 0x28,
1967 OP_MSSVLAN = OP_MSS | OP_VLAN,
1968
1969 OP_BUFFER = 0x40,
1970 OP_PACKET = 0x41,
1971 OP_LARGESEND = 0x43,
1972 OP_LSOV2 = 0x45,
1973
1974 /* YUKON-2 STATUS opcodes defines */
1975 OP_RXSTAT = 0x60,
1976 OP_RXTIMESTAMP = 0x61,
1977 OP_RXVLAN = 0x62,
1978 OP_RXCHKS = 0x64,
1979 OP_RXCHKSVLAN = OP_RXCHKS | OP_RXVLAN,
1980 OP_RXTIMEVLAN = OP_RXTIMESTAMP | OP_RXVLAN,
1981 OP_RSS_HASH = 0x65,
1982 OP_TXINDEXLE = 0x68,
1983 OP_MACSEC = 0x6c,
1984 OP_PUTIDX = 0x70,
1985 };
1986
1987 enum status_css {
1988 CSS_TCPUDPCSOK = 1<<7, /* TCP / UDP checksum is ok */
1989 CSS_ISUDP = 1<<6, /* packet is a UDP packet */
1990 CSS_ISTCP = 1<<5, /* packet is a TCP packet */
1991 CSS_ISIPFRAG = 1<<4, /* packet is a TCP/UDP frag, CS calc not done */
1992 CSS_ISIPV6 = 1<<3, /* packet is a IPv6 packet */
1993 CSS_IPV4CSUMOK = 1<<2, /* IP v4: TCP header checksum is ok */
1994 CSS_ISIPV4 = 1<<1, /* packet is a IPv4 packet */
1995 CSS_LINK_BIT = 1<<0, /* port number (legacy) */
1996 };
1997
1998 /* Yukon 2 hardware interface */
1999 struct sky2_tx_le {
2000 u32 addr;
2001 u16 length; /* also vlan tag or checksum start */
2002 u8 ctrl;
2003 u8 opcode;
2004 } __attribute((packed));
2005
2006 struct sky2_rx_le {
2007 u32 addr;
2008 u16 length;
2009 u8 ctrl;
2010 u8 opcode;
2011 } __attribute((packed));
2012
2013 struct sky2_status_le {
2014 u32 status; /* also checksum */
2015 u16 length; /* also vlan tag */
2016 u8 css;
2017 u8 opcode;
2018 } __attribute((packed));
2019
2020 struct tx_ring_info {
2021 struct io_buffer *iob;
2022 u32 mapaddr;
2023 u32 maplen;
2024 };
2025
2026 struct rx_ring_info {
2027 struct io_buffer *iob;
2028 u32 data_addr;
2029 u32 data_size;
2030 };
2031
2032 enum flow_control {
2033 FC_NONE = 0,
2034 FC_TX = 1,
2035 FC_RX = 2,
2036 FC_BOTH = 3,
2037 };
2038
2039 struct sky2_port {
2040 struct sky2_hw *hw;
2041 struct net_device *netdev;
2042 unsigned port;
2043
2044 struct tx_ring_info *tx_ring;
2045 struct sky2_tx_le *tx_le;
2046 u16 tx_cons; /* next le to check */
2047 u16 tx_prod; /* next le to use */
2048
2049 struct rx_ring_info *rx_ring;
2050 struct sky2_rx_le *rx_le;
2051
2052 u16 rx_next; /* next re to check */
2053 u16 rx_put; /* next le index to use */
2054 u16 rx_data_size;
2055
2056 u32 rx_le_map;
2057 u32 tx_le_map;
2058 u16 advertising; /* ADVERTISED_ bits */
2059 u16 speed; /* SPEED_1000, SPEED_100, ... */
2060 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
2061 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
2062 enum flow_control flow_mode;
2063 enum flow_control flow_status;
2064 };
2065
2066 struct sky2_hw {
2067 unsigned long regs;
2068 struct pci_device *pdev;
2069 struct net_device *dev[2];
2070 unsigned long flags;
2071 #define SKY2_HW_USE_MSI 0x00000001
2072 #define SKY2_HW_FIBRE_PHY 0x00000002
2073 #define SKY2_HW_GIGABIT 0x00000004
2074 #define SKY2_HW_NEWER_PHY 0x00000008
2075 #define SKY2_HW_RAM_BUFFER 0x00000010
2076 #define SKY2_HW_NEW_LE 0x00000020 /* new LSOv2 format */
2077 #define SKY2_HW_AUTO_TX_SUM 0x00000040 /* new IP decode for Tx */
2078 #define SKY2_HW_ADV_POWER_CTL 0x00000080 /* additional PHY power regs */
2079
2080 u8 chip_id;
2081 u8 chip_rev;
2082 u8 pmd_type;
2083 u8 ports;
2084
2085 struct sky2_status_le *st_le;
2086 u32 st_idx;
2087 u32 st_dma;
2088 };
2089
2090 static inline int sky2_is_copper(const struct sky2_hw *hw)
2091 {
2092 return !(hw->flags & SKY2_HW_FIBRE_PHY);
2093 }
2094
2095 /* Register accessor for memory mapped device */
2096 static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
2097 {
2098 return readl(hw->regs + reg);
2099 }
2100
2101 static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
2102 {
2103 return readw(hw->regs + reg);
2104 }
2105
2106 static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
2107 {
2108 return readb(hw->regs + reg);
2109 }
2110
2111 static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
2112 {
2113 writel(val, hw->regs + reg);
2114 }
2115
2116 static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
2117 {
2118 writew(val, hw->regs + reg);
2119 }
2120
2121 static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
2122 {
2123 writeb(val, hw->regs + reg);
2124 }
2125
2126 /* Yukon PHY related registers */
2127 #define SK_GMAC_REG(port,reg) \
2128 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2129 #define GM_PHY_RETRIES 100
2130
2131 static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
2132 {
2133 return sky2_read16(hw, SK_GMAC_REG(port,reg));
2134 }
2135
2136 static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
2137 {
2138 unsigned base = SK_GMAC_REG(port, reg);
2139 return (u32) sky2_read16(hw, base)
2140 | (u32) sky2_read16(hw, base+4) << 16;
2141 }
2142
2143 static inline void gma_write16(const struct sky2_hw *hw, unsigned port, int r, u16 v)
2144 {
2145 sky2_write16(hw, SK_GMAC_REG(port,r), v);
2146 }
2147
2148 static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
2149 const u8 *addr)
2150 {
2151 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
2152 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2153 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
2154 }
2155
2156 /* PCI config space access */
2157 static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
2158 {
2159 return sky2_read32(hw, Y2_CFG_SPC + reg);
2160 }
2161
2162 static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
2163 {
2164 return sky2_read16(hw, Y2_CFG_SPC + reg);
2165 }
2166
2167 static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
2168 {
2169 sky2_write32(hw, Y2_CFG_SPC + reg, val);
2170 }
2171
2172 static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
2173 {
2174 sky2_write16(hw, Y2_CFG_SPC + reg, val);
2175 }
2176 #endif
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