src/drivers/net/e1000e/e1000e_ich8lan.h

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 FILE_LICENCE ( GPL2_OR_LATER );
  30
  31 #ifndef _E1000E_ICH8LAN_H_
  32 #define _E1000E_ICH8LAN_H_
  33
  34 #define ICH_FLASH_GFPREG                 0x0000
  35 #define ICH_FLASH_HSFSTS                 0x0004
  36 #define ICH_FLASH_HSFCTL                 0x0006
  37 #define ICH_FLASH_FADDR                  0x0008
  38 #define ICH_FLASH_FDATA0                 0x0010
  39
  40 /* Requires up to 10 seconds when MNG might be accessing part. */
  41 #define ICH_FLASH_READ_COMMAND_TIMEOUT   10000000
  42 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT  10000000
  43 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT  10000000
  44 #define ICH_FLASH_LINEAR_ADDR_MASK       0x00FFFFFF
  45 #define ICH_FLASH_CYCLE_REPEAT_COUNT     10
  46
  47 #define ICH_CYCLE_READ                   0
  48 #define ICH_CYCLE_WRITE                  2
  49 #define ICH_CYCLE_ERASE                  3
  50
  51 #define FLASH_GFPREG_BASE_MASK           0x1FFF
  52 #define FLASH_SECTOR_ADDR_SHIFT          12
  53
  54 #define ICH_FLASH_SEG_SIZE_256           256
  55 #define ICH_FLASH_SEG_SIZE_4K            4096
  56 #define ICH_FLASH_SEG_SIZE_8K            8192
  57 #define ICH_FLASH_SEG_SIZE_64K           65536
  58 #define ICH_FLASH_SECTOR_SIZE            4096
  59
  60 #define ICH_FLASH_REG_MAPSIZE            0x00A0
  61
  62 #define E1000_ICH_FWSM_RSPCIPHY          0x00000040 /* Reset PHY on PCI Reset */
  63 #define E1000_ICH_FWSM_DISSW             0x10000000 /* FW Disables SW Writes */
  64 /* FW established a valid mode */
  65 #define E1000_ICH_FWSM_FW_VALID          0x00008000
  66
  67 #define E1000_ICH_MNG_IAMT_MODE          0x2
  68
  69 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  70                                  (ID_LED_OFF1_OFF2 <<  8) | \
  71                                  (ID_LED_OFF1_ON2  <<  4) | \
  72                                  (ID_LED_DEF1_DEF2))
  73
  74 #define E1000_ICH_NVM_SIG_WORD           0x13
  75 #define E1000_ICH_NVM_SIG_MASK           0xC000
  76 #define E1000_ICH_NVM_VALID_SIG_MASK     0xC0
  77 #define E1000_ICH_NVM_SIG_VALUE          0x80
  78
  79 #define E1000_ICH8_LAN_INIT_TIMEOUT      1500
  80
  81 #define E1000_FEXTNVM_SW_CONFIG        1
  82 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
  83
  84 #define PCIE_ICH8_SNOOP_ALL   PCIE_NO_SNOOP_ALL
  85
  86 #define E1000_ICH_RAR_ENTRIES            7
  87
  88 #define PHY_PAGE_SHIFT 5
  89 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
  90                            ((reg) & MAX_PHY_REG_ADDRESS))
  91 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
  92 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
  93 #define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
  94 #define IGP3_PM_CTRL    PHY_REG(769, 20) /* Power Management Control */
  95
  96 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS         0x0002
  97 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
  98 #define IGP3_VR_CTRL_MODE_SHUTDOWN           0x0200
  99 #define IGP3_PM_CTRL_FORCE_PWR_DOWN          0x0020
 100
 101 /* PHY Wakeup Registers and defines */
 102 #define BM_RCTL         PHY_REG(BM_WUC_PAGE, 0)
 103 #define BM_WUC          PHY_REG(BM_WUC_PAGE, 1)
 104 #define BM_WUFC         PHY_REG(BM_WUC_PAGE, 2)
 105 #define BM_WUS          PHY_REG(BM_WUC_PAGE, 3)
 106 #define BM_RAR_L(_i)    (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
 107 #define BM_RAR_M(_i)    (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
 108 #define BM_RAR_H(_i)    (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
 109 #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
 110 #define BM_MTA(_i)      (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
 111
 112 #define BM_RCTL_UPE           0x0001          /* Unicast Promiscuous Mode */
 113 #define BM_RCTL_MPE           0x0002          /* Multicast Promiscuous Mode */
 114 #define BM_RCTL_MO_SHIFT      3               /* Multicast Offset Shift */
 115 #define BM_RCTL_MO_MASK       (3 << 3)        /* Multicast Offset Mask */
 116 #define BM_RCTL_BAM           0x0020          /* Broadcast Accept Mode */
 117 #define BM_RCTL_PMCF          0x0040          /* Pass MAC Control Frames */
 118 #define BM_RCTL_RFCE          0x0080          /* Rx Flow Control Enable */
 119
 120 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 121 #define HV_MUX_DATA_CTRL               PHY_REG(776, 16)
 122 #define HV_MUX_DATA_CTRL_GEN_TO_MAC    0x0400
 123 #define HV_MUX_DATA_CTRL_FORCE_SPEED   0x0004
 124 #define HV_SCC_UPPER            PHY_REG(778, 16) /* Single Collision Count */
 125 #define HV_SCC_LOWER            PHY_REG(778, 17)
 126 #define HV_ECOL_UPPER           PHY_REG(778, 18) /* Excessive Collision Count */
 127 #define HV_ECOL_LOWER           PHY_REG(778, 19)
 128 #define HV_MCC_UPPER            PHY_REG(778, 20) /* Multiple Collision Count */
 129 #define HV_MCC_LOWER            PHY_REG(778, 21)
 130 #define HV_LATECOL_UPPER        PHY_REG(778, 23) /* Late Collision Count */
 131 #define HV_LATECOL_LOWER        PHY_REG(778, 24)
 132 #define HV_COLC_UPPER           PHY_REG(778, 25) /* Collision Count */
 133 #define HV_COLC_LOWER           PHY_REG(778, 26)
 134 #define HV_DC_UPPER             PHY_REG(778, 27) /* Defer Count */
 135 #define HV_DC_LOWER             PHY_REG(778, 28)
 136 #define HV_TNCRS_UPPER          PHY_REG(778, 29) /* Transmit with no CRS */
 137 #define HV_TNCRS_LOWER          PHY_REG(778, 30)
 138
 139 #define E1000_FCRTV_PCH     0x05F40 /* PCH Flow Control Refresh Timer Value */
 140
 141 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 142 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 143
 144 /* SMBus Address Phy Register */
 145 #define HV_SMB_ADDR            PHY_REG(768, 26)
 146 #define HV_SMB_ADDR_PEC_EN     0x0200
 147 #define HV_SMB_ADDR_VALID      0x0080
 148
 149 /* Strapping Option Register - RO */
 150 #define E1000_STRAP                     0x0000C
 151 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 152 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 153
 154 /* OEM Bits Phy Register */
 155 #define HV_OEM_BITS            PHY_REG(768, 25)
 156 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 157 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 158 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 159
 160 #define LCD_CFG_PHY_ADDR_BIT   0x0020 /* Phy address bit from LCD Config word */
 161
 162 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 163
 164 /*
 165  * Additional interrupts need to be handled for ICH family:
 166  *  DSW = The FW changed the status of the DISSW bit in FWSM
 167  *  PHYINT = The LAN connected device generates an interrupt
 168  *  EPRST = Manageability reset event
 169  */
 170 #define IMS_ICH_ENABLE_MASK (\
 171     E1000_IMS_DSW   | \
 172     E1000_IMS_PHYINT | \
 173     E1000_IMS_EPRST)
 174
 175 /* Additional interrupt register bit definitions */
 176 #define E1000_ICR_LSECPNC       0x00004000          /* PN threshold - client */
 177 #define E1000_IMS_LSECPNC       E1000_ICR_LSECPNC   /* PN threshold - client */
 178 #define E1000_ICS_LSECPNC       E1000_ICR_LSECPNC   /* PN threshold - client */
 179
 180 /* Security Processing bit Indication */
 181 #define E1000_RXDEXT_LINKSEC_STATUS_LSECH       0x01000000
 182 #define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK     0x60000000
 183 #define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH  0x20000000
 184 #define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000
 185 #define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG      0x60000000
 186
 187
 188 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
 189                                                  bool state);
 190 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
 191 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
 192 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
 193 s32 e1000e_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
 194 s32 e1000e_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_config);
 195
 196 #endif