src/drivers/net/igb/igb_defines.h

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 FILE_LICENCE ( GPL2_ONLY );
  29
  30 #ifndef _IGB_DEFINES_H_
  31 #define _IGB_DEFINES_H_
  32
  33 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
  34 #define REQ_TX_DESCRIPTOR_MULTIPLE  8
  35 #define REQ_RX_DESCRIPTOR_MULTIPLE  8
  36
  37 /* Definitions for power management and wakeup registers */
  38 /* Wake Up Control */
  39 #define E1000_WUC_APME       0x00000001 /* APM Enable */
  40 #define E1000_WUC_PME_EN     0x00000002 /* PME Enable */
  41 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
  42 #define E1000_WUC_APMPME     0x00000008 /* Assert PME on APM Wakeup */
  43 #define E1000_WUC_LSCWE      0x00000010 /* Link Status wake up enable */
  44 #define E1000_WUC_LSCWO      0x00000020 /* Link Status wake up override */
  45 #define E1000_WUC_SPM        0x80000000 /* Enable SPM */
  46 #define E1000_WUC_PHY_WAKE   0x00000100 /* if PHY supports wakeup */
  47
  48 /* Wake Up Filter Control */
  49 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
  50 #define E1000_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
  51 #define E1000_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
  52 #define E1000_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
  53 #define E1000_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
  54 #define E1000_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
  55 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
  56 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
  57 #define E1000_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
  58 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
  59 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
  60 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
  61 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
  62 #define E1000_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
  63 #define E1000_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
  64 #define E1000_WUFC_ALL_FILTERS  0x000F00FF /* Mask for all wakeup filters */
  65 #define E1000_WUFC_FLX_OFFSET   16 /* Offset to the Flexible Filters bits */
  66 #define E1000_WUFC_FLX_FILTERS  0x000F0000 /*Mask for the 4 flexible filters */
  67 /*
  68  * For 82576 to utilize Extended filter masks in addition to
  69  * existing (filter) masks
  70  */
  71 #define E1000_WUFC_EXT_FLX_FILTERS      0x00300000 /* Ext. FLX filter mask */
  72
  73 /* Wake Up Status */
  74 #define E1000_WUS_LNKC         E1000_WUFC_LNKC
  75 #define E1000_WUS_MAG          E1000_WUFC_MAG
  76 #define E1000_WUS_EX           E1000_WUFC_EX
  77 #define E1000_WUS_MC           E1000_WUFC_MC
  78 #define E1000_WUS_BC           E1000_WUFC_BC
  79 #define E1000_WUS_ARP          E1000_WUFC_ARP
  80 #define E1000_WUS_IPV4         E1000_WUFC_IPV4
  81 #define E1000_WUS_IPV6         E1000_WUFC_IPV6
  82 #define E1000_WUS_FLX0         E1000_WUFC_FLX0
  83 #define E1000_WUS_FLX1         E1000_WUFC_FLX1
  84 #define E1000_WUS_FLX2         E1000_WUFC_FLX2
  85 #define E1000_WUS_FLX3         E1000_WUFC_FLX3
  86 #define E1000_WUS_FLX_FILTERS  E1000_WUFC_FLX_FILTERS
  87
  88 /* Wake Up Packet Length */
  89 #define E1000_WUPL_LENGTH_MASK 0x0FFF   /* Only the lower 12 bits are valid */
  90
  91 /* Four Flexible Filters are supported */
  92 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
  93 /* Two Extended Flexible Filters are supported (82576) */
  94 #define E1000_EXT_FLEXIBLE_FILTER_COUNT_MAX     2
  95 #define E1000_FHFT_LENGTH_OFFSET        0xFC /* Length byte in FHFT */
  96 #define E1000_FHFT_LENGTH_MASK          0x0FF /* Length in lower byte */
  97
  98 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
  99 #define E1000_FLEXIBLE_FILTER_SIZE_MAX  128
 100
 101 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
 102 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
 103 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
 104
 105 /* Extended Device Control */
 106 #define E1000_CTRL_EXT_GPI0_EN   0x00000001 /* Maps SDP4 to GPI0 */
 107 #define E1000_CTRL_EXT_GPI1_EN   0x00000002 /* Maps SDP5 to GPI1 */
 108 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
 109 #define E1000_CTRL_EXT_GPI2_EN   0x00000004 /* Maps SDP6 to GPI2 */
 110 #define E1000_CTRL_EXT_GPI3_EN   0x00000008 /* Maps SDP7 to GPI3 */
 111 /* Reserved (bits 4,5) in >= 82575 */
 112 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */
 113 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */
 114 #define E1000_CTRL_EXT_PHY_INT   E1000_CTRL_EXT_SDP5_DATA
 115 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */
 116 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */
 117 /* SDP 4/5 (bits 8,9) are reserved in >= 82575 */
 118 #define E1000_CTRL_EXT_SDP4_DIR  0x00000100 /* Direction of SDP4 0=in 1=out */
 119 #define E1000_CTRL_EXT_SDP5_DIR  0x00000200 /* Direction of SDP5 0=in 1=out */
 120 #define E1000_CTRL_EXT_SDP6_DIR  0x00000400 /* Direction of SDP6 0=in 1=out */
 121 #define E1000_CTRL_EXT_SDP3_DIR  0x00000800 /* Direction of SDP3 0=in 1=out */
 122 #define E1000_CTRL_EXT_ASDCHK    0x00001000 /* Initiate an ASD sequence */
 123 #define E1000_CTRL_EXT_EE_RST    0x00002000 /* Reinitialize from EEPROM */
 124 #define E1000_CTRL_EXT_IPS       0x00004000 /* Invert Power State */
 125 /* Physical Func Reset Done Indication */
 126 #define E1000_CTRL_EXT_PFRSTD    0x00004000
 127 #define E1000_CTRL_EXT_SPD_BYPS  0x00008000 /* Speed Select Bypass */
 128 #define E1000_CTRL_EXT_RO_DIS    0x00020000 /* Relaxed Ordering disable */
 129 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */
 130 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
 131 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
 132 #define E1000_CTRL_EXT_LINK_MODE_TBI  0x00C00000
 133 #define E1000_CTRL_EXT_LINK_MODE_KMRN    0x00000000
 134 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES  0x00C00000
 135 #define E1000_CTRL_EXT_LINK_MODE_PCIX_SERDES  0x00800000
 136 #define E1000_CTRL_EXT_LINK_MODE_SGMII   0x00800000
 137 #define E1000_CTRL_EXT_EIAME          0x01000000
 138 #define E1000_CTRL_EXT_IRCA           0x00000001
 139 #define E1000_CTRL_EXT_WR_WMARK_MASK  0x03000000
 140 #define E1000_CTRL_EXT_WR_WMARK_256   0x00000000
 141 #define E1000_CTRL_EXT_WR_WMARK_320   0x01000000
 142 #define E1000_CTRL_EXT_WR_WMARK_384   0x02000000
 143 #define E1000_CTRL_EXT_WR_WMARK_448   0x03000000
 144 #define E1000_CTRL_EXT_CANC           0x04000000 /* Int delay cancellation */
 145 #define E1000_CTRL_EXT_DRV_LOAD       0x10000000 /* Driver loaded bit for FW */
 146 /* IAME enable bit (27) was removed in >= 82575 */
 147 #define E1000_CTRL_EXT_IAME          0x08000000 /* Int acknowledge Auto-mask */
 148 #define E1000_CRTL_EXT_PB_PAREN       0x01000000 /* packet buffer parity error
 149                                                   * detection enabled */
 150 #define E1000_CTRL_EXT_DF_PAREN       0x02000000 /* descriptor FIFO parity
 151                                                   * error detection enable */
 152 #define E1000_CTRL_EXT_GHOST_PAREN    0x40000000
 153 #define E1000_CTRL_EXT_PBA_CLR        0x80000000 /* PBA Clear */
 154 #define E1000_I2CCMD_REG_ADDR_SHIFT   16
 155 #define E1000_I2CCMD_REG_ADDR         0x00FF0000
 156 #define E1000_I2CCMD_PHY_ADDR_SHIFT   24
 157 #define E1000_I2CCMD_PHY_ADDR         0x07000000
 158 #define E1000_I2CCMD_OPCODE_READ      0x08000000
 159 #define E1000_I2CCMD_OPCODE_WRITE     0x00000000
 160 #define E1000_I2CCMD_RESET            0x10000000
 161 #define E1000_I2CCMD_READY            0x20000000
 162 #define E1000_I2CCMD_INTERRUPT_ENA    0x40000000
 163 #define E1000_I2CCMD_ERROR            0x80000000
 164 #define E1000_MAX_SGMII_PHY_REG_ADDR  255
 165 #define E1000_I2CCMD_PHY_TIMEOUT      200
 166 #define E1000_IVAR_VALID        0x80
 167 #define E1000_GPIE_NSICR        0x00000001
 168 #define E1000_GPIE_MSIX_MODE    0x00000010
 169 #define E1000_GPIE_EIAME        0x40000000
 170 #define E1000_GPIE_PBA          0x80000000
 171
 172 /* Receive Descriptor bit definitions */
 173 #define E1000_RXD_STAT_DD       0x01    /* Descriptor Done */
 174 #define E1000_RXD_STAT_EOP      0x02    /* End of Packet */
 175 #define E1000_RXD_STAT_IXSM     0x04    /* Ignore checksum */
 176 #define E1000_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
 177 #define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
 178 #define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
 179 #define E1000_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
 180 #define E1000_RXD_STAT_PIF      0x80    /* passed in-exact filter */
 181 #define E1000_RXD_STAT_CRCV     0x100   /* Speculative CRC Valid */
 182 #define E1000_RXD_STAT_IPIDV    0x200   /* IP identification valid */
 183 #define E1000_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
 184 #define E1000_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
 185 #define E1000_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
 186 #define E1000_RXD_ERR_CE        0x01    /* CRC Error */
 187 #define E1000_RXD_ERR_SE        0x02    /* Symbol Error */
 188 #define E1000_RXD_ERR_SEQ       0x04    /* Sequence Error */
 189 #define E1000_RXD_ERR_CXE       0x10    /* Carrier Extension Error */
 190 #define E1000_RXD_ERR_TCPE      0x20    /* TCP/UDP Checksum Error */
 191 #define E1000_RXD_ERR_IPE       0x40    /* IP Checksum Error */
 192 #define E1000_RXD_ERR_RXE       0x80    /* Rx Data Error */
 193 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
 194 #define E1000_RXD_SPC_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
 195 #define E1000_RXD_SPC_PRI_SHIFT 13
 196 #define E1000_RXD_SPC_CFI_MASK  0x1000  /* CFI is bit 12 */
 197 #define E1000_RXD_SPC_CFI_SHIFT 12
 198
 199 #define E1000_RXDEXT_STATERR_CE    0x01000000
 200 #define E1000_RXDEXT_STATERR_SE    0x02000000
 201 #define E1000_RXDEXT_STATERR_SEQ   0x04000000
 202 #define E1000_RXDEXT_STATERR_CXE   0x10000000
 203 #define E1000_RXDEXT_STATERR_TCPE  0x20000000
 204 #define E1000_RXDEXT_STATERR_IPE   0x40000000
 205 #define E1000_RXDEXT_STATERR_RXE   0x80000000
 206
 207 /* mask to determine if packets should be dropped due to frame errors */
 208 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \
 209     E1000_RXD_ERR_CE  |                \
 210     E1000_RXD_ERR_SE  |                \
 211     E1000_RXD_ERR_SEQ |                \
 212     E1000_RXD_ERR_CXE |                \
 213     E1000_RXD_ERR_RXE)
 214
 215 /* Same mask, but for extended and packet split descriptors */
 216 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
 217     E1000_RXDEXT_STATERR_CE  |            \
 218     E1000_RXDEXT_STATERR_SE  |            \
 219     E1000_RXDEXT_STATERR_SEQ |            \
 220     E1000_RXDEXT_STATERR_CXE |            \
 221     E1000_RXDEXT_STATERR_RXE)
 222
 223 #define E1000_MRQC_ENABLE_MASK                 0x00000007
 224 #define E1000_MRQC_ENABLE_RSS_2Q               0x00000001
 225 #define E1000_MRQC_ENABLE_RSS_INT              0x00000004
 226 #define E1000_MRQC_RSS_FIELD_MASK              0xFFFF0000
 227 #define E1000_MRQC_RSS_FIELD_IPV4_TCP          0x00010000
 228 #define E1000_MRQC_RSS_FIELD_IPV4              0x00020000
 229 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX       0x00040000
 230 #define E1000_MRQC_RSS_FIELD_IPV6_EX           0x00080000
 231 #define E1000_MRQC_RSS_FIELD_IPV6              0x00100000
 232 #define E1000_MRQC_RSS_FIELD_IPV6_TCP          0x00200000
 233
 234 #define E1000_RXDPS_HDRSTAT_HDRSP              0x00008000
 235 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK        0x000003FF
 236
 237 /* Management Control */
 238 #define E1000_MANC_SMBUS_EN      0x00000001 /* SMBus Enabled - RO */
 239 #define E1000_MANC_ASF_EN        0x00000002 /* ASF Enabled - RO */
 240 #define E1000_MANC_R_ON_FORCE    0x00000004 /* Reset on Force TCO - RO */
 241 #define E1000_MANC_RMCP_EN       0x00000100 /* Enable RCMP 026Fh Filtering */
 242 #define E1000_MANC_0298_EN       0x00000200 /* Enable RCMP 0298h Filtering */
 243 #define E1000_MANC_IPV4_EN       0x00000400 /* Enable IPv4 */
 244 #define E1000_MANC_IPV6_EN       0x00000800 /* Enable IPv6 */
 245 #define E1000_MANC_SNAP_EN       0x00001000 /* Accept LLC/SNAP */
 246 #define E1000_MANC_ARP_EN        0x00002000 /* Enable ARP Request Filtering */
 247 /* Enable Neighbor Discovery Filtering */
 248 #define E1000_MANC_NEIGHBOR_EN   0x00004000
 249 #define E1000_MANC_ARP_RES_EN    0x00008000 /* Enable ARP response Filtering */
 250 #define E1000_MANC_TCO_RESET     0x00010000 /* TCO Reset Occurred */
 251 #define E1000_MANC_RCV_TCO_EN    0x00020000 /* Receive TCO Packets Enabled */
 252 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
 253 #define E1000_MANC_RCV_ALL       0x00080000 /* Receive All Enabled */
 254 #define E1000_MANC_BLK_PHY_RST_ON_IDE   0x00040000 /* Block phy resets */
 255 /* Enable MAC address filtering */
 256 #define E1000_MANC_EN_MAC_ADDR_FILTER   0x00100000
 257 /* Enable MNG packets to host memory */
 258 #define E1000_MANC_EN_MNG2HOST   0x00200000
 259 /* Enable IP address filtering */
 260 #define E1000_MANC_EN_IP_ADDR_FILTER    0x00400000
 261 #define E1000_MANC_EN_XSUM_FILTER   0x00800000 /* Enable checksum filtering */
 262 #define E1000_MANC_BR_EN            0x01000000 /* Enable broadcast filtering */
 263 #define E1000_MANC_SMB_REQ       0x01000000 /* SMBus Request */
 264 #define E1000_MANC_SMB_GNT       0x02000000 /* SMBus Grant */
 265 #define E1000_MANC_SMB_CLK_IN    0x04000000 /* SMBus Clock In */
 266 #define E1000_MANC_SMB_DATA_IN   0x08000000 /* SMBus Data In */
 267 #define E1000_MANC_SMB_DATA_OUT  0x10000000 /* SMBus Data Out */
 268 #define E1000_MANC_SMB_CLK_OUT   0x20000000 /* SMBus Clock Out */
 269
 270 #define E1000_MANC_SMB_DATA_OUT_SHIFT  28 /* SMBus Data Out Shift */
 271 #define E1000_MANC_SMB_CLK_OUT_SHIFT   29 /* SMBus Clock Out Shift */
 272
 273 /* Receive Control */
 274 #define E1000_RCTL_RST            0x00000001    /* Software reset */
 275 #define E1000_RCTL_EN             0x00000002    /* enable */
 276 #define E1000_RCTL_SBP            0x00000004    /* store bad packet */
 277 #define E1000_RCTL_UPE            0x00000008    /* unicast promisc enable */
 278 #define E1000_RCTL_MPE            0x00000010    /* multicast promisc enable */
 279 #define E1000_RCTL_LPE            0x00000020    /* long packet enable */
 280 #define E1000_RCTL_LBM_NO         0x00000000    /* no loopback mode */
 281 #define E1000_RCTL_LBM_MAC        0x00000040    /* MAC loopback mode */
 282 #define E1000_RCTL_LBM_SLP        0x00000080    /* serial link loopback mode */
 283 #define E1000_RCTL_LBM_TCVR       0x000000C0    /* tcvr loopback mode */
 284 #define E1000_RCTL_DTYP_MASK      0x00000C00    /* Descriptor type mask */
 285 #define E1000_RCTL_DTYP_PS        0x00000400    /* Packet Split descriptor */
 286 #define E1000_RCTL_RDMTS_HALF     0x00000000    /* rx desc min thresh size */
 287 #define E1000_RCTL_RDMTS_QUAT     0x00000100    /* rx desc min thresh size */
 288 #define E1000_RCTL_RDMTS_EIGTH    0x00000200    /* rx desc min thresh size */
 289 #define E1000_RCTL_MO_SHIFT       12            /* multicast offset shift */
 290 #define E1000_RCTL_MO_0           0x00000000    /* multicast offset 11:0 */
 291 #define E1000_RCTL_MO_1           0x00001000    /* multicast offset 12:1 */
 292 #define E1000_RCTL_MO_2           0x00002000    /* multicast offset 13:2 */
 293 #define E1000_RCTL_MO_3           0x00003000    /* multicast offset 15:4 */
 294 #define E1000_RCTL_MDR            0x00004000    /* multicast desc ring 0 */
 295 #define E1000_RCTL_BAM            0x00008000    /* broadcast enable */
 296 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
 297 #define E1000_RCTL_SZ_2048        0x00000000    /* rx buffer size 2048 */
 298 #define E1000_RCTL_SZ_1024        0x00010000    /* rx buffer size 1024 */
 299 #define E1000_RCTL_SZ_512         0x00020000    /* rx buffer size 512 */
 300 #define E1000_RCTL_SZ_256         0x00030000    /* rx buffer size 256 */
 301 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
 302 #define E1000_RCTL_SZ_16384       0x00010000    /* rx buffer size 16384 */
 303 #define E1000_RCTL_SZ_8192        0x00020000    /* rx buffer size 8192 */
 304 #define E1000_RCTL_SZ_4096        0x00030000    /* rx buffer size 4096 */
 305 #define E1000_RCTL_VFE            0x00040000    /* vlan filter enable */
 306 #define E1000_RCTL_CFIEN          0x00080000    /* canonical form enable */
 307 #define E1000_RCTL_CFI            0x00100000    /* canonical form indicator */
 308 #define E1000_RCTL_DPF            0x00400000    /* discard pause frames */
 309 #define E1000_RCTL_PMCF           0x00800000    /* pass MAC control frames */
 310 #define E1000_RCTL_BSEX           0x02000000    /* Buffer size extension */
 311 #define E1000_RCTL_SECRC          0x04000000    /* Strip Ethernet CRC */
 312 #define E1000_RCTL_FLXBUF_MASK    0x78000000    /* Flexible buffer size */
 313 #define E1000_RCTL_FLXBUF_SHIFT   27            /* Flexible buffer shift */
 314
 315 /*
 316  * Use byte values for the following shift parameters
 317  * Usage:
 318  *     psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) &
 319  *                  E1000_PSRCTL_BSIZE0_MASK) |
 320  *                ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) &
 321  *                  E1000_PSRCTL_BSIZE1_MASK) |
 322  *                ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) &
 323  *                  E1000_PSRCTL_BSIZE2_MASK) |
 324  *                ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |;
 325  *                  E1000_PSRCTL_BSIZE3_MASK))
 326  * where value0 = [128..16256],  default=256
 327  *       value1 = [1024..64512], default=4096
 328  *       value2 = [0..64512],    default=4096
 329  *       value3 = [0..64512],    default=0
 330  */
 331
 332 #define E1000_PSRCTL_BSIZE0_MASK   0x0000007F
 333 #define E1000_PSRCTL_BSIZE1_MASK   0x00003F00
 334 #define E1000_PSRCTL_BSIZE2_MASK   0x003F0000
 335 #define E1000_PSRCTL_BSIZE3_MASK   0x3F000000
 336
 337 #define E1000_PSRCTL_BSIZE0_SHIFT  7            /* Shift _right_ 7 */
 338 #define E1000_PSRCTL_BSIZE1_SHIFT  2            /* Shift _right_ 2 */
 339 #define E1000_PSRCTL_BSIZE2_SHIFT  6            /* Shift _left_ 6 */
 340 #define E1000_PSRCTL_BSIZE3_SHIFT 14            /* Shift _left_ 14 */
 341
 342 /* SWFW_SYNC Definitions */
 343 #define E1000_SWFW_EEP_SM   0x01
 344 #define E1000_SWFW_PHY0_SM  0x02
 345 #define E1000_SWFW_PHY1_SM  0x04
 346 #define E1000_SWFW_CSR_SM   0x08
 347
 348 /* FACTPS Definitions */
 349 #define E1000_FACTPS_LFS    0x40000000  /* LAN Function Select */
 350 /* Device Control */
 351 #define E1000_CTRL_FD       0x00000001  /* Full duplex.0=half; 1=full */
 352 #define E1000_CTRL_BEM      0x00000002  /* Endian Mode.0=little,1=big */
 353 #define E1000_CTRL_PRIOR    0x00000004  /* Priority on PCI. 0=rx,1=fair */
 354 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master reqs */
 355 #define E1000_CTRL_LRST     0x00000008  /* Link reset. 0=normal,1=reset */
 356 #define E1000_CTRL_TME      0x00000010  /* Test mode. 0=normal,1=test */
 357 #define E1000_CTRL_SLE      0x00000020  /* Serial Link on 0=dis,1=en */
 358 #define E1000_CTRL_ASDE     0x00000020  /* Auto-speed detect enable */
 359 #define E1000_CTRL_SLU      0x00000040  /* Set link up (Force Link) */
 360 #define E1000_CTRL_ILOS     0x00000080  /* Invert Loss-Of Signal */
 361 #define E1000_CTRL_SPD_SEL  0x00000300  /* Speed Select Mask */
 362 #define E1000_CTRL_SPD_10   0x00000000  /* Force 10Mb */
 363 #define E1000_CTRL_SPD_100  0x00000100  /* Force 100Mb */
 364 #define E1000_CTRL_SPD_1000 0x00000200  /* Force 1Gb */
 365 #define E1000_CTRL_BEM32    0x00000400  /* Big Endian 32 mode */
 366 #define E1000_CTRL_FRCSPD   0x00000800  /* Force Speed */
 367 #define E1000_CTRL_FRCDPX   0x00001000  /* Force Duplex */
 368 #define E1000_CTRL_D_UD_EN  0x00002000  /* Dock/Undock enable */
 369 #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock
 370                                              * indication in SDP[0] */
 371 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through
 372                                                * PHYRST_N pin */
 373 #define E1000_CTRL_EXT_LINK_EN 0x00010000 /* enable link status from external
 374                                            * LINK_0 and LINK_1 pins */
 375 #define E1000_CTRL_SWDPIN0  0x00040000  /* SWDPIN 0 value */
 376 #define E1000_CTRL_SWDPIN1  0x00080000  /* SWDPIN 1 value */
 377 #define E1000_CTRL_SWDPIN2  0x00100000  /* SWDPIN 2 value */
 378 #define E1000_CTRL_ADVD3WUC 0x00100000  /* D3 WUC */
 379 #define E1000_CTRL_SWDPIN3  0x00200000  /* SWDPIN 3 value */
 380 #define E1000_CTRL_SWDPIO0  0x00400000  /* SWDPIN 0 Input or output */
 381 #define E1000_CTRL_SWDPIO1  0x00800000  /* SWDPIN 1 input or output */
 382 #define E1000_CTRL_SWDPIO2  0x01000000  /* SWDPIN 2 input or output */
 383 #define E1000_CTRL_SWDPIO3  0x02000000  /* SWDPIN 3 input or output */
 384 #define E1000_CTRL_RST      0x04000000  /* Global reset */
 385 #define E1000_CTRL_RFCE     0x08000000  /* Receive Flow Control enable */
 386 #define E1000_CTRL_TFCE     0x10000000  /* Transmit flow control enable */
 387 #define E1000_CTRL_RTE      0x20000000  /* Routing tag enable */
 388 #define E1000_CTRL_VME      0x40000000  /* IEEE VLAN mode enable */
 389 #define E1000_CTRL_PHY_RST  0x80000000  /* PHY Reset */
 390 #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to ME */
 391 #define E1000_CTRL_I2C_ENA  0x02000000  /* I2C enable */
 392
 393 /*
 394  * Bit definitions for the Management Data IO (MDIO) and Management Data
 395  * Clock (MDC) pins in the Device Control Register.
 396  */
 397 #define E1000_CTRL_PHY_RESET_DIR  E1000_CTRL_SWDPIO0
 398 #define E1000_CTRL_PHY_RESET      E1000_CTRL_SWDPIN0
 399 #define E1000_CTRL_MDIO_DIR       E1000_CTRL_SWDPIO2
 400 #define E1000_CTRL_MDIO           E1000_CTRL_SWDPIN2
 401 #define E1000_CTRL_MDC_DIR        E1000_CTRL_SWDPIO3
 402 #define E1000_CTRL_MDC            E1000_CTRL_SWDPIN3
 403 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
 404 #define E1000_CTRL_PHY_RESET4     E1000_CTRL_EXT_SDP4_DATA
 405
 406 #define E1000_CONNSW_ENRGSRC             0x4
 407 #define E1000_PCS_CFG_PCS_EN             8
 408 #define E1000_PCS_LCTL_FLV_LINK_UP       1
 409 #define E1000_PCS_LCTL_FSV_10            0
 410 #define E1000_PCS_LCTL_FSV_100           2
 411 #define E1000_PCS_LCTL_FSV_1000          4
 412 #define E1000_PCS_LCTL_FDV_FULL          8
 413 #define E1000_PCS_LCTL_FSD               0x10
 414 #define E1000_PCS_LCTL_FORCE_LINK        0x20
 415 #define E1000_PCS_LCTL_LOW_LINK_LATCH    0x40
 416 #define E1000_PCS_LCTL_FORCE_FCTRL       0x80
 417 #define E1000_PCS_LCTL_AN_ENABLE         0x10000
 418 #define E1000_PCS_LCTL_AN_RESTART        0x20000
 419 #define E1000_PCS_LCTL_AN_TIMEOUT        0x40000
 420 #define E1000_PCS_LCTL_AN_SGMII_BYPASS   0x80000
 421 #define E1000_PCS_LCTL_AN_SGMII_TRIGGER  0x100000
 422 #define E1000_PCS_LCTL_FAST_LINK_TIMER   0x1000000
 423 #define E1000_PCS_LCTL_LINK_OK_FIX       0x2000000
 424 #define E1000_PCS_LCTL_CRS_ON_NI         0x4000000
 425 #define E1000_ENABLE_SERDES_LOOPBACK     0x0410
 426
 427 #define E1000_PCS_LSTS_LINK_OK           1
 428 #define E1000_PCS_LSTS_SPEED_10          0
 429 #define E1000_PCS_LSTS_SPEED_100         2
 430 #define E1000_PCS_LSTS_SPEED_1000        4
 431 #define E1000_PCS_LSTS_DUPLEX_FULL       8
 432 #define E1000_PCS_LSTS_SYNK_OK           0x10
 433 #define E1000_PCS_LSTS_AN_COMPLETE       0x10000
 434 #define E1000_PCS_LSTS_AN_PAGE_RX        0x20000
 435 #define E1000_PCS_LSTS_AN_TIMED_OUT      0x40000
 436 #define E1000_PCS_LSTS_AN_REMOTE_FAULT   0x80000
 437 #define E1000_PCS_LSTS_AN_ERROR_RWS      0x100000
 438
 439 /* Device Status */
 440 #define E1000_STATUS_FD         0x00000001      /* Full duplex.0=half,1=full */
 441 #define E1000_STATUS_LU         0x00000002      /* Link up.0=no,1=link */
 442 #define E1000_STATUS_FUNC_MASK  0x0000000C      /* PCI Function Mask */
 443 #define E1000_STATUS_FUNC_SHIFT 2
 444 #define E1000_STATUS_FUNC_0     0x00000000      /* Function 0 */
 445 #define E1000_STATUS_FUNC_1     0x00000004      /* Function 1 */
 446 #define E1000_STATUS_TXOFF      0x00000010      /* transmission paused */
 447 #define E1000_STATUS_TBIMODE    0x00000020      /* TBI mode */
 448 #define E1000_STATUS_SPEED_MASK 0x000000C0
 449 #define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
 450 #define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
 451 #define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
 452 #define E1000_STATUS_LAN_INIT_DONE 0x00000200  /* Lan Init Completion by NVM */
 453 #define E1000_STATUS_ASDV       0x00000300      /* Auto speed detect value */
 454 #define E1000_STATUS_PHYRA      0x00000400      /* PHY Reset Asserted */
 455 #define E1000_STATUS_DOCK_CI    0x00000800      /* Change in Dock/Undock state.
 456                                                  * Clear on write '0'. */
 457 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */
 458 #define E1000_STATUS_MTXCKOK    0x00000400      /* MTX clock running OK */
 459 #define E1000_STATUS_PCI66      0x00000800      /* In 66Mhz slot */
 460 #define E1000_STATUS_BUS64      0x00001000      /* In 64 bit slot */
 461 #define E1000_STATUS_PCIX_MODE  0x00002000      /* PCI-X mode */
 462 #define E1000_STATUS_PCIX_SPEED 0x0000C000      /* PCI-X bus speed */
 463 #define E1000_STATUS_BMC_SKU_0  0x00100000 /* BMC USB redirect disabled */
 464 #define E1000_STATUS_BMC_SKU_1  0x00200000 /* BMC SRAM disabled */
 465 #define E1000_STATUS_BMC_SKU_2  0x00400000 /* BMC SDRAM disabled */
 466 #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */
 467 #define E1000_STATUS_BMC_LITE   0x01000000 /* BMC external code execution
 468                                             * disabled */
 469 #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */
 470 #define E1000_STATUS_FUSE_8       0x04000000
 471 #define E1000_STATUS_FUSE_9       0x08000000
 472 #define E1000_STATUS_SERDES0_DIS  0x10000000 /* SERDES disabled on port 0 */
 473 #define E1000_STATUS_SERDES1_DIS  0x20000000 /* SERDES disabled on port 1 */
 474
 475 /* Constants used to interpret the masked PCI-X bus speed. */
 476 #define E1000_STATUS_PCIX_SPEED_66  0x00000000 /* PCI-X bus speed 50-66 MHz */
 477 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
 478 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /*PCI-X bus speed 100-133 MHz*/
 479
 480 #define SPEED_10    10
 481 #define SPEED_100   100
 482 #define SPEED_1000  1000
 483 #define HALF_DUPLEX 1
 484 #define FULL_DUPLEX 2
 485
 486 #define PHY_FORCE_TIME   20
 487
 488 #define ADVERTISE_10_HALF                 0x0001
 489 #define ADVERTISE_10_FULL                 0x0002
 490 #define ADVERTISE_100_HALF                0x0004
 491 #define ADVERTISE_100_FULL                0x0008
 492 #define ADVERTISE_1000_HALF               0x0010 /* Not used, just FYI */
 493 #define ADVERTISE_1000_FULL               0x0020
 494
 495 /* 1000/H is not supported, nor spec-compliant. */
 496 #define E1000_ALL_SPEED_DUPLEX  (ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
 497                                 ADVERTISE_100_HALF |  ADVERTISE_100_FULL | \
 498                                                      ADVERTISE_1000_FULL)
 499 #define E1000_ALL_NOT_GIG       (ADVERTISE_10_HALF |   ADVERTISE_10_FULL | \
 500                                 ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
 501 #define E1000_ALL_100_SPEED    (ADVERTISE_100_HALF |  ADVERTISE_100_FULL)
 502 #define E1000_ALL_10_SPEED      (ADVERTISE_10_HALF |   ADVERTISE_10_FULL)
 503 #define E1000_ALL_FULL_DUPLEX   (ADVERTISE_10_FULL |  ADVERTISE_100_FULL | \
 504                                                      ADVERTISE_1000_FULL)
 505 #define E1000_ALL_HALF_DUPLEX   (ADVERTISE_10_HALF |  ADVERTISE_100_HALF)
 506
 507 #define AUTONEG_ADVERTISE_SPEED_DEFAULT   E1000_ALL_SPEED_DUPLEX
 508
 509 /* LED Control */
 510 #define E1000_LEDCTL_LED0_MODE_MASK       0x0000000F
 511 #define E1000_LEDCTL_LED0_MODE_SHIFT      0
 512 #define E1000_LEDCTL_LED0_BLINK_RATE      0x00000020
 513 #define E1000_LEDCTL_LED0_IVRT            0x00000040
 514 #define E1000_LEDCTL_LED0_BLINK           0x00000080
 515 #define E1000_LEDCTL_LED1_MODE_MASK       0x00000F00
 516 #define E1000_LEDCTL_LED1_MODE_SHIFT      8
 517 #define E1000_LEDCTL_LED1_BLINK_RATE      0x00002000
 518 #define E1000_LEDCTL_LED1_IVRT            0x00004000
 519 #define E1000_LEDCTL_LED1_BLINK           0x00008000
 520 #define E1000_LEDCTL_LED2_MODE_MASK       0x000F0000
 521 #define E1000_LEDCTL_LED2_MODE_SHIFT      16
 522 #define E1000_LEDCTL_LED2_BLINK_RATE      0x00200000
 523 #define E1000_LEDCTL_LED2_IVRT            0x00400000
 524 #define E1000_LEDCTL_LED2_BLINK           0x00800000
 525 #define E1000_LEDCTL_LED3_MODE_MASK       0x0F000000
 526 #define E1000_LEDCTL_LED3_MODE_SHIFT      24
 527 #define E1000_LEDCTL_LED3_BLINK_RATE      0x20000000
 528 #define E1000_LEDCTL_LED3_IVRT            0x40000000
 529 #define E1000_LEDCTL_LED3_BLINK           0x80000000
 530
 531 #define E1000_LEDCTL_MODE_LINK_10_1000  0x0
 532 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1
 533 #define E1000_LEDCTL_MODE_LINK_UP       0x2
 534 #define E1000_LEDCTL_MODE_ACTIVITY      0x3
 535 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
 536 #define E1000_LEDCTL_MODE_LINK_10       0x5
 537 #define E1000_LEDCTL_MODE_LINK_100      0x6
 538 #define E1000_LEDCTL_MODE_LINK_1000     0x7
 539 #define E1000_LEDCTL_MODE_PCIX_MODE     0x8
 540 #define E1000_LEDCTL_MODE_FULL_DUPLEX   0x9
 541 #define E1000_LEDCTL_MODE_COLLISION     0xA
 542 #define E1000_LEDCTL_MODE_BUS_SPEED     0xB
 543 #define E1000_LEDCTL_MODE_BUS_SIZE      0xC
 544 #define E1000_LEDCTL_MODE_PAUSED        0xD
 545 #define E1000_LEDCTL_MODE_LED_ON        0xE
 546 #define E1000_LEDCTL_MODE_LED_OFF       0xF
 547
 548 /* Transmit Descriptor bit definitions */
 549 #define E1000_TXD_DTYP_D     0x00100000 /* Data Descriptor */
 550 #define E1000_TXD_DTYP_C     0x00000000 /* Context Descriptor */
 551 #define E1000_TXD_POPTS_SHIFT 8         /* POPTS shift */
 552 #define E1000_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
 553 #define E1000_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
 554 #define E1000_TXD_CMD_EOP    0x01000000 /* End of Packet */
 555 #define E1000_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
 556 #define E1000_TXD_CMD_IC     0x04000000 /* Insert Checksum */
 557 #define E1000_TXD_CMD_RS     0x08000000 /* Report Status */
 558 #define E1000_TXD_CMD_RPS    0x10000000 /* Report Packet Sent */
 559 #define E1000_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
 560 #define E1000_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
 561 #define E1000_TXD_CMD_IDE    0x80000000 /* Enable Tidv register */
 562 #define E1000_TXD_STAT_DD    0x00000001 /* Descriptor Done */
 563 #define E1000_TXD_STAT_EC    0x00000002 /* Excess Collisions */
 564 #define E1000_TXD_STAT_LC    0x00000004 /* Late Collisions */
 565 #define E1000_TXD_STAT_TU    0x00000008 /* Transmit underrun */
 566 #define E1000_TXD_CMD_TCP    0x01000000 /* TCP packet */
 567 #define E1000_TXD_CMD_IP     0x02000000 /* IP packet */
 568 #define E1000_TXD_CMD_TSE    0x04000000 /* TCP Seg enable */
 569 #define E1000_TXD_STAT_TC    0x00000004 /* Tx Underrun */
 570 /* Extended desc bits for Linksec and timesync */
 571
 572 /* Transmit Control */
 573 #define E1000_TCTL_RST    0x00000001    /* software reset */
 574 #define E1000_TCTL_EN     0x00000002    /* enable tx */
 575 #define E1000_TCTL_BCE    0x00000004    /* busy check enable */
 576 #define E1000_TCTL_PSP    0x00000008    /* pad short packets */
 577 #define E1000_TCTL_CT     0x00000ff0    /* collision threshold */
 578 #define E1000_TCTL_COLD   0x003ff000    /* collision distance */
 579 #define E1000_TCTL_SWXOFF 0x00400000    /* SW Xoff transmission */
 580 #define E1000_TCTL_PBE    0x00800000    /* Packet Burst Enable */
 581 #define E1000_TCTL_RTLC   0x01000000    /* Re-transmit on late collision */
 582 #define E1000_TCTL_NRTU   0x02000000    /* No Re-transmit on underrun */
 583 #define E1000_TCTL_MULR   0x10000000    /* Multiple request support */
 584
 585 /* Transmit Arbitration Count */
 586 #define E1000_TARC0_ENABLE     0x00000400   /* Enable Tx Queue 0 */
 587
 588 /* SerDes Control */
 589 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400
 590
 591 /* Receive Checksum Control */
 592 #define E1000_RXCSUM_PCSS_MASK 0x000000FF   /* Packet Checksum Start */
 593 #define E1000_RXCSUM_IPOFL     0x00000100   /* IPv4 checksum offload */
 594 #define E1000_RXCSUM_TUOFL     0x00000200   /* TCP / UDP checksum offload */
 595 #define E1000_RXCSUM_IPV6OFL   0x00000400   /* IPv6 checksum offload */
 596 #define E1000_RXCSUM_CRCOFL    0x00000800   /* CRC32 offload enable */
 597 #define E1000_RXCSUM_IPPCSE    0x00001000   /* IP payload checksum enable */
 598 #define E1000_RXCSUM_PCSD      0x00002000   /* packet checksum disabled */
 599
 600 /* Header split receive */
 601 #define E1000_RFCTL_ISCSI_DIS           0x00000001
 602 #define E1000_RFCTL_ISCSI_DWC_MASK      0x0000003E
 603 #define E1000_RFCTL_ISCSI_DWC_SHIFT     1
 604 #define E1000_RFCTL_NFSW_DIS            0x00000040
 605 #define E1000_RFCTL_NFSR_DIS            0x00000080
 606 #define E1000_RFCTL_NFS_VER_MASK        0x00000300
 607 #define E1000_RFCTL_NFS_VER_SHIFT       8
 608 #define E1000_RFCTL_IPV6_DIS            0x00000400
 609 #define E1000_RFCTL_IPV6_XSUM_DIS       0x00000800
 610 #define E1000_RFCTL_ACK_DIS             0x00001000
 611 #define E1000_RFCTL_ACKD_DIS            0x00002000
 612 #define E1000_RFCTL_IPFRSP_DIS          0x00004000
 613 #define E1000_RFCTL_EXTEN               0x00008000
 614 #define E1000_RFCTL_IPV6_EX_DIS         0x00010000
 615 #define E1000_RFCTL_NEW_IPV6_EXT_DIS    0x00020000
 616 #define E1000_RFCTL_LEF                 0x00040000
 617
 618 /* Collision related configuration parameters */
 619 #define E1000_COLLISION_THRESHOLD       15
 620 #define E1000_CT_SHIFT                  4
 621 #define E1000_COLLISION_DISTANCE        63
 622 #define E1000_COLD_SHIFT                12
 623
 624 /* Default values for the transmit IPG register */
 625 #define DEFAULT_82543_TIPG_IPGT_FIBER  9
 626 #define DEFAULT_82543_TIPG_IPGT_COPPER 8
 627
 628 #define E1000_TIPG_IPGT_MASK  0x000003FF
 629 #define E1000_TIPG_IPGR1_MASK 0x000FFC00
 630 #define E1000_TIPG_IPGR2_MASK 0x3FF00000
 631
 632 #define DEFAULT_82543_TIPG_IPGR1 8
 633 #define E1000_TIPG_IPGR1_SHIFT  10
 634
 635 #define DEFAULT_82543_TIPG_IPGR2 6
 636 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7
 637 #define E1000_TIPG_IPGR2_SHIFT  20
 638
 639 /* Ethertype field values */
 640 #define ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.3ac packet */
 641
 642 #define ETHERNET_FCS_SIZE       4
 643 #define MAX_JUMBO_FRAME_SIZE    0x3F00
 644
 645 /* Extended Configuration Control and Size */
 646 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP      0x00000020
 647 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE       0x00000001
 648 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE       0x00000008
 649 #define E1000_EXTCNF_CTRL_SWFLAG                 0x00000020
 650 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000
 651 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT          16
 652 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK   0x0FFF0000
 653 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT          16
 654
 655 #define E1000_PHY_CTRL_SPD_EN             0x00000001
 656 #define E1000_PHY_CTRL_D0A_LPLU           0x00000002
 657 #define E1000_PHY_CTRL_NOND0A_LPLU        0x00000004
 658 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008
 659 #define E1000_PHY_CTRL_GBE_DISABLE        0x00000040
 660
 661 #define E1000_KABGTXD_BGSQLBIAS           0x00050000
 662
 663 /* PBA constants */
 664 #define E1000_PBA_6K  0x0006    /* 6KB */
 665 #define E1000_PBA_8K  0x0008    /* 8KB */
 666 #define E1000_PBA_10K 0x000A    /* 10KB */
 667 #define E1000_PBA_12K 0x000C    /* 12KB */
 668 #define E1000_PBA_14K 0x000E    /* 14KB */
 669 #define E1000_PBA_16K 0x0010    /* 16KB */
 670 #define E1000_PBA_18K 0x0012
 671 #define E1000_PBA_20K 0x0014
 672 #define E1000_PBA_22K 0x0016
 673 #define E1000_PBA_24K 0x0018
 674 #define E1000_PBA_26K 0x001A
 675 #define E1000_PBA_30K 0x001E
 676 #define E1000_PBA_32K 0x0020
 677 #define E1000_PBA_34K 0x0022
 678 #define E1000_PBA_35K 0x0023
 679 #define E1000_PBA_38K 0x0026
 680 #define E1000_PBA_40K 0x0028
 681 #define E1000_PBA_48K 0x0030    /* 48KB */
 682 #define E1000_PBA_64K 0x0040    /* 64KB */
 683
 684 #define E1000_PBS_16K E1000_PBA_16K
 685 #define E1000_PBS_24K E1000_PBA_24K
 686
 687 #define IFS_MAX       80
 688 #define IFS_MIN       40
 689 #define IFS_RATIO     4
 690 #define IFS_STEP      10
 691 #define MIN_NUM_XMITS 1000
 692
 693 /* SW Semaphore Register */
 694 #define E1000_SWSM_SMBI         0x00000001 /* Driver Semaphore bit */
 695 #define E1000_SWSM_SWESMBI      0x00000002 /* FW Semaphore bit */
 696 #define E1000_SWSM_WMNG         0x00000004 /* Wake MNG Clock */
 697 #define E1000_SWSM_DRV_LOAD     0x00000008 /* Driver Loaded Bit */
 698
 699 #define E1000_SWSM2_LOCK        0x00000002 /* Secondary driver semaphore bit */
 700
 701 /* Interrupt Cause Read */
 702 #define E1000_ICR_TXDW          0x00000001 /* Transmit desc written back */
 703 #define E1000_ICR_TXQE          0x00000002 /* Transmit Queue empty */
 704 #define E1000_ICR_LSC           0x00000004 /* Link Status Change */
 705 #define E1000_ICR_RXSEQ         0x00000008 /* rx sequence error */
 706 #define E1000_ICR_RXDMT0        0x00000010 /* rx desc min. threshold (0) */
 707 #define E1000_ICR_RXO           0x00000040 /* rx overrun */
 708 #define E1000_ICR_RXT0          0x00000080 /* rx timer intr (ring 0) */
 709 #define E1000_ICR_VMMB          0x00000100 /* VM MB event */
 710 #define E1000_ICR_MDAC          0x00000200 /* MDIO access complete */
 711 #define E1000_ICR_RXCFG         0x00000400 /* Rx /c/ ordered set */
 712 #define E1000_ICR_GPI_EN0       0x00000800 /* GP Int 0 */
 713 #define E1000_ICR_GPI_EN1       0x00001000 /* GP Int 1 */
 714 #define E1000_ICR_GPI_EN2       0x00002000 /* GP Int 2 */
 715 #define E1000_ICR_GPI_EN3       0x00004000 /* GP Int 3 */
 716 #define E1000_ICR_TXD_LOW       0x00008000
 717 #define E1000_ICR_SRPD          0x00010000
 718 #define E1000_ICR_ACK           0x00020000 /* Receive Ack frame */
 719 #define E1000_ICR_MNG           0x00040000 /* Manageability event */
 720 #define E1000_ICR_DOCK          0x00080000 /* Dock/Undock */
 721 #define E1000_ICR_INT_ASSERTED  0x80000000 /* If this bit asserted, the driver
 722                                             * should claim the interrupt */
 723 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* Q0 Rx desc FIFO parity error */
 724 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* Q0 Tx desc FIFO parity error */
 725 #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity err */
 726 #define E1000_ICR_PB_PAR        0x00800000 /* packet buffer parity error */
 727 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* Q1 Rx desc FIFO parity error */
 728 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* Q1 Tx desc FIFO parity error */
 729 #define E1000_ICR_ALL_PARITY    0x03F00000 /* all parity error bits */
 730 #define E1000_ICR_DSW           0x00000020 /* FW changed the status of DISSW
 731                                             * bit in the FWSM */
 732 #define E1000_ICR_PHYINT        0x00001000 /* LAN connected device generates
 733                                             * an interrupt */
 734 #define E1000_ICR_DOUTSYNC      0x10000000 /* NIC DMA out of sync */
 735 #define E1000_ICR_EPRST         0x00100000 /* ME hardware reset occurs */
 736
 737
 738 /* Extended Interrupt Cause Read */
 739 #define E1000_EICR_RX_QUEUE0    0x00000001 /* Rx Queue 0 Interrupt */
 740 #define E1000_EICR_RX_QUEUE1    0x00000002 /* Rx Queue 1 Interrupt */
 741 #define E1000_EICR_RX_QUEUE2    0x00000004 /* Rx Queue 2 Interrupt */
 742 #define E1000_EICR_RX_QUEUE3    0x00000008 /* Rx Queue 3 Interrupt */
 743 #define E1000_EICR_TX_QUEUE0    0x00000100 /* Tx Queue 0 Interrupt */
 744 #define E1000_EICR_TX_QUEUE1    0x00000200 /* Tx Queue 1 Interrupt */
 745 #define E1000_EICR_TX_QUEUE2    0x00000400 /* Tx Queue 2 Interrupt */
 746 #define E1000_EICR_TX_QUEUE3    0x00000800 /* Tx Queue 3 Interrupt */
 747 #define E1000_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
 748 #define E1000_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
 749 /* TCP Timer */
 750 #define E1000_TCPTIMER_KS       0x00000100 /* KickStart */
 751 #define E1000_TCPTIMER_COUNT_ENABLE       0x00000200 /* Count Enable */
 752 #define E1000_TCPTIMER_COUNT_FINISH       0x00000400 /* Count finish */
 753 #define E1000_TCPTIMER_LOOP     0x00000800 /* Loop */
 754
 755 /*
 756  * This defines the bits that are set in the Interrupt Mask
 757  * Set/Read Register.  Each bit is documented below:
 758  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
 759  *   o RXSEQ  = Receive Sequence Error
 760  */
 761 #define POLL_IMS_ENABLE_MASK ( \
 762     E1000_IMS_RXDMT0 |    \
 763     E1000_IMS_RXSEQ)
 764
 765 /*
 766  * This defines the bits that are set in the Interrupt Mask
 767  * Set/Read Register.  Each bit is documented below:
 768  *   o RXT0   = Receiver Timer Interrupt (ring 0)
 769  *   o TXDW   = Transmit Descriptor Written Back
 770  *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
 771  *   o RXSEQ  = Receive Sequence Error
 772  *   o LSC    = Link Status Change
 773  */
 774 #define IMS_ENABLE_MASK ( \
 775     E1000_IMS_RXT0   |    \
 776     E1000_IMS_TXDW   |    \
 777     E1000_IMS_RXDMT0 |    \
 778     E1000_IMS_RXSEQ  |    \
 779     E1000_IMS_LSC)
 780
 781 /* Interrupt Mask Set */
 782 #define E1000_IMS_TXDW      E1000_ICR_TXDW      /* Tx desc written back */
 783 #define E1000_IMS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
 784 #define E1000_IMS_LSC       E1000_ICR_LSC       /* Link Status Change */
 785 #define E1000_IMS_VMMB      E1000_ICR_VMMB      /* Mail box activity */
 786 #define E1000_IMS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
 787 #define E1000_IMS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
 788 #define E1000_IMS_RXO       E1000_ICR_RXO       /* rx overrun */
 789 #define E1000_IMS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
 790 #define E1000_IMS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
 791 #define E1000_IMS_RXCFG     E1000_ICR_RXCFG     /* Rx /c/ ordered set */
 792 #define E1000_IMS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
 793 #define E1000_IMS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
 794 #define E1000_IMS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
 795 #define E1000_IMS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
 796 #define E1000_IMS_TXD_LOW   E1000_ICR_TXD_LOW
 797 #define E1000_IMS_SRPD      E1000_ICR_SRPD
 798 #define E1000_IMS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
 799 #define E1000_IMS_MNG       E1000_ICR_MNG       /* Manageability event */
 800 #define E1000_IMS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
 801 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
 802                                                          * parity error */
 803 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
 804                                                          * parity error */
 805 #define E1000_IMS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer
 806                                                          * parity error */
 807 #define E1000_IMS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity
 808                                                          * error */
 809 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
 810                                                          * parity error */
 811 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
 812                                                          * parity error */
 813 #define E1000_IMS_DSW       E1000_ICR_DSW
 814 #define E1000_IMS_PHYINT    E1000_ICR_PHYINT
 815 #define E1000_IMS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
 816 #define E1000_IMS_EPRST     E1000_ICR_EPRST
 817
 818 /* Extended Interrupt Mask Set */
 819 #define E1000_EIMS_RX_QUEUE0    E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
 820 #define E1000_EIMS_RX_QUEUE1    E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
 821 #define E1000_EIMS_RX_QUEUE2    E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
 822 #define E1000_EIMS_RX_QUEUE3    E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
 823 #define E1000_EIMS_TX_QUEUE0    E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
 824 #define E1000_EIMS_TX_QUEUE1    E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
 825 #define E1000_EIMS_TX_QUEUE2    E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
 826 #define E1000_EIMS_TX_QUEUE3    E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
 827 #define E1000_EIMS_TCP_TIMER    E1000_EICR_TCP_TIMER /* TCP Timer */
 828 #define E1000_EIMS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
 829
 830 /* Interrupt Cause Set */
 831 #define E1000_ICS_TXDW      E1000_ICR_TXDW      /* Tx desc written back */
 832 #define E1000_ICS_TXQE      E1000_ICR_TXQE      /* Transmit Queue empty */
 833 #define E1000_ICS_LSC       E1000_ICR_LSC       /* Link Status Change */
 834 #define E1000_ICS_RXSEQ     E1000_ICR_RXSEQ     /* rx sequence error */
 835 #define E1000_ICS_RXDMT0    E1000_ICR_RXDMT0    /* rx desc min. threshold */
 836 #define E1000_ICS_RXO       E1000_ICR_RXO       /* rx overrun */
 837 #define E1000_ICS_RXT0      E1000_ICR_RXT0      /* rx timer intr */
 838 #define E1000_ICS_MDAC      E1000_ICR_MDAC      /* MDIO access complete */
 839 #define E1000_ICS_RXCFG     E1000_ICR_RXCFG     /* Rx /c/ ordered set */
 840 #define E1000_ICS_GPI_EN0   E1000_ICR_GPI_EN0   /* GP Int 0 */
 841 #define E1000_ICS_GPI_EN1   E1000_ICR_GPI_EN1   /* GP Int 1 */
 842 #define E1000_ICS_GPI_EN2   E1000_ICR_GPI_EN2   /* GP Int 2 */
 843 #define E1000_ICS_GPI_EN3   E1000_ICR_GPI_EN3   /* GP Int 3 */
 844 #define E1000_ICS_TXD_LOW   E1000_ICR_TXD_LOW
 845 #define E1000_ICS_SRPD      E1000_ICR_SRPD
 846 #define E1000_ICS_ACK       E1000_ICR_ACK       /* Receive Ack frame */
 847 #define E1000_ICS_MNG       E1000_ICR_MNG       /* Manageability event */
 848 #define E1000_ICS_DOCK      E1000_ICR_DOCK      /* Dock/Undock */
 849 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* Q0 Rx desc FIFO
 850                                                          * parity error */
 851 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* Q0 Tx desc FIFO
 852                                                          * parity error */
 853 #define E1000_ICS_HOST_ARB_PAR  E1000_ICR_HOST_ARB_PAR  /* host arb read buffer
 854                                                          * parity error */
 855 #define E1000_ICS_PB_PAR        E1000_ICR_PB_PAR        /* packet buffer parity
 856                                                          * error */
 857 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* Q1 Rx desc FIFO
 858                                                          * parity error */
 859 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* Q1 Tx desc FIFO
 860                                                          * parity error */
 861 #define E1000_ICS_DSW       E1000_ICR_DSW
 862 #define E1000_ICS_DOUTSYNC  E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
 863 #define E1000_ICS_PHYINT    E1000_ICR_PHYINT
 864 #define E1000_ICS_EPRST     E1000_ICR_EPRST
 865
 866 /* Extended Interrupt Cause Set */
 867 #define E1000_EICS_RX_QUEUE0    E1000_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
 868 #define E1000_EICS_RX_QUEUE1    E1000_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
 869 #define E1000_EICS_RX_QUEUE2    E1000_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
 870 #define E1000_EICS_RX_QUEUE3    E1000_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
 871 #define E1000_EICS_TX_QUEUE0    E1000_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
 872 #define E1000_EICS_TX_QUEUE1    E1000_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
 873 #define E1000_EICS_TX_QUEUE2    E1000_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
 874 #define E1000_EICS_TX_QUEUE3    E1000_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
 875 #define E1000_EICS_TCP_TIMER    E1000_EICR_TCP_TIMER /* TCP Timer */
 876 #define E1000_EICS_OTHER        E1000_EICR_OTHER   /* Interrupt Cause Active */
 877
 878 #define E1000_EITR_ITR_INT_MASK 0x0000FFFF
 879
 880 /* Transmit Descriptor Control */
 881 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
 882 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
 883 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
 884 #define E1000_TXDCTL_GRAN    0x01000000 /* TXDCTL Granularity */
 885 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
 886 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
 887 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */
 888 /* Enable the counting of descriptors still to be processed. */
 889 #define E1000_TXDCTL_COUNT_DESC 0x00400000
 890
 891 /* Flow Control Constants */
 892 #define FLOW_CONTROL_ADDRESS_LOW  0x00C28001
 893 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
 894 #define FLOW_CONTROL_TYPE         0x8808
 895
 896 /* 802.1q VLAN Packet Size */
 897 #define VLAN_TAG_SIZE              4    /* 802.3ac tag (not DMA'd) */
 898 #define E1000_VLAN_FILTER_TBL_SIZE 128  /* VLAN Filter Table (4096 bits) */
 899
 900 /* Receive Address */
 901 /*
 902  * Number of high/low register pairs in the RAR. The RAR (Receive Address
 903  * Registers) holds the directed and multicast addresses that we monitor.
 904  * Technically, we have 16 spots.  However, we reserve one of these spots
 905  * (RAR[15]) for our directed address used by controllers with
 906  * manageability enabled, allowing us room for 15 multicast addresses.
 907  */
 908 #define E1000_RAR_ENTRIES     15
 909 #define E1000_RAH_AV  0x80000000        /* Receive descriptor valid */
 910 #define E1000_RAL_MAC_ADDR_LEN 4
 911 #define E1000_RAH_MAC_ADDR_LEN 2
 912 #define E1000_RAH_POOL_MASK 0x03FC0000
 913 #define E1000_RAH_POOL_1 0x00040000
 914
 915 /* Error Codes */
 916 #define E1000_SUCCESS      0
 917 #define E1000_ERR_NVM      1
 918 #define E1000_ERR_PHY      2
 919 #define E1000_ERR_CONFIG   3
 920 #define E1000_ERR_PARAM    4
 921 #define E1000_ERR_MAC_INIT 5
 922 #define E1000_ERR_PHY_TYPE 6
 923 #define E1000_ERR_RESET   9
 924 #define E1000_ERR_MASTER_REQUESTS_PENDING 10
 925 #define E1000_ERR_HOST_INTERFACE_COMMAND 11
 926 #define E1000_BLK_PHY_RESET   12
 927 #define E1000_ERR_SWFW_SYNC 13
 928 #define E1000_NOT_IMPLEMENTED 14
 929 #define E1000_ERR_MBX      15
 930
 931 /* Loop limit on how long we wait for auto-negotiation to complete */
 932 #define FIBER_LINK_UP_LIMIT               50
 933 #define COPPER_LINK_UP_LIMIT              10
 934 #define PHY_AUTO_NEG_LIMIT                45
 935 #define PHY_FORCE_LIMIT                   20
 936 /* Number of 100 microseconds we wait for PCI Express master disable */
 937 #define MASTER_DISABLE_TIMEOUT      800
 938 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
 939 #define PHY_CFG_TIMEOUT             100
 940 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
 941 #define MDIO_OWNERSHIP_TIMEOUT      10
 942 /* Number of milliseconds for NVM auto read done after MAC reset. */
 943 #define AUTO_READ_DONE_TIMEOUT      10
 944
 945 /* Flow Control */
 946 #define E1000_FCRTH_RTH  0x0000FFF8     /* Mask Bits[15:3] for RTH */
 947 #define E1000_FCRTH_XFCE 0x80000000     /* External Flow Control Enable */
 948 #define E1000_FCRTL_RTL  0x0000FFF8     /* Mask Bits[15:3] for RTL */
 949 #define E1000_FCRTL_XONE 0x80000000     /* Enable XON frame transmission */
 950
 951 /* Transmit Configuration Word */
 952 #define E1000_TXCW_FD         0x00000020        /* TXCW full duplex */
 953 #define E1000_TXCW_HD         0x00000040        /* TXCW half duplex */
 954 #define E1000_TXCW_PAUSE      0x00000080        /* TXCW sym pause request */
 955 #define E1000_TXCW_ASM_DIR    0x00000100        /* TXCW astm pause direction */
 956 #define E1000_TXCW_PAUSE_MASK 0x00000180        /* TXCW pause request mask */
 957 #define E1000_TXCW_RF         0x00003000        /* TXCW remote fault */
 958 #define E1000_TXCW_NP         0x00008000        /* TXCW next page */
 959 #define E1000_TXCW_CW         0x0000ffff        /* TxConfigWord mask */
 960 #define E1000_TXCW_TXC        0x40000000        /* Transmit Config control */
 961 #define E1000_TXCW_ANE        0x80000000        /* Auto-neg enable */
 962
 963 /* Receive Configuration Word */
 964 #define E1000_RXCW_CW         0x0000ffff        /* RxConfigWord mask */
 965 #define E1000_RXCW_NC         0x04000000        /* Receive config no carrier */
 966 #define E1000_RXCW_IV         0x08000000        /* Receive config invalid */
 967 #define E1000_RXCW_CC         0x10000000        /* Receive config change */
 968 #define E1000_RXCW_C          0x20000000        /* Receive config */
 969 #define E1000_RXCW_SYNCH      0x40000000        /* Receive config synch */
 970 #define E1000_RXCW_ANC        0x80000000        /* Auto-neg complete */
 971
 972 #define E1000_TSYNCTXCTL_VALID    0x00000001 /* tx timestamp valid */
 973 #define E1000_TSYNCTXCTL_ENABLED  0x00000010 /* enable tx timestampping */
 974
 975 #define E1000_TSYNCRXCTL_VALID      0x00000001 /* rx timestamp valid */
 976 #define E1000_TSYNCRXCTL_TYPE_MASK  0x0000000E /* rx type mask */
 977 #define E1000_TSYNCRXCTL_TYPE_L2_V2       0x00
 978 #define E1000_TSYNCRXCTL_TYPE_L4_V1       0x02
 979 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2    0x04
 980 #define E1000_TSYNCRXCTL_TYPE_ALL         0x08
 981 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2    0x0A
 982 #define E1000_TSYNCRXCTL_ENABLED    0x00000010 /* enable rx timestampping */
 983
 984 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK   0x000000FF
 985 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE       0x00
 986 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE  0x01
 987 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE   0x02
 988 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03
 989 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04
 990
 991 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK               0x00000F00
 992 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE                 0x0000
 993 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE            0x0100
 994 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE       0x0200
 995 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE      0x0300
 996 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE             0x0800
 997 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE           0x0900
 998 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE  0x0A00
 999 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE             0x0B00
1000 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE           0x0C00
1001 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE           0x0D00
1002
1003 #define E1000_TIMINCA_16NS_SHIFT 24
1004
1005 /* PCI Express Control */
1006 #define E1000_GCR_RXD_NO_SNOOP          0x00000001
1007 #define E1000_GCR_RXDSCW_NO_SNOOP       0x00000002
1008 #define E1000_GCR_RXDSCR_NO_SNOOP       0x00000004
1009 #define E1000_GCR_TXD_NO_SNOOP          0x00000008
1010 #define E1000_GCR_TXDSCW_NO_SNOOP       0x00000010
1011 #define E1000_GCR_TXDSCR_NO_SNOOP       0x00000020
1012 #define E1000_GCR_CMPL_TMOUT_MASK       0x0000F000
1013 #define E1000_GCR_CMPL_TMOUT_10ms       0x00001000
1014 #define E1000_GCR_CMPL_TMOUT_RESEND     0x00010000
1015 #define E1000_GCR_CAP_VER2              0x00040000
1016
1017 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP         | \
1018                            E1000_GCR_RXDSCW_NO_SNOOP      | \
1019                            E1000_GCR_RXDSCR_NO_SNOOP      | \
1020                            E1000_GCR_TXD_NO_SNOOP         | \
1021                            E1000_GCR_TXDSCW_NO_SNOOP      | \
1022                            E1000_GCR_TXDSCR_NO_SNOOP)
1023
1024 /* PHY Control Register */
1025 #define MII_CR_SPEED_SELECT_MSB 0x0040  /* bits 6,13: 10=1000, 01=100, 00=10 */
1026 #define MII_CR_COLL_TEST_ENABLE 0x0080  /* Collision test enable */
1027 #define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
1028 #define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
1029 #define MII_CR_ISOLATE          0x0400  /* Isolate PHY from MII */
1030 #define MII_CR_POWER_DOWN       0x0800  /* Power down */
1031 #define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
1032 #define MII_CR_SPEED_SELECT_LSB 0x2000  /* bits 6,13: 10=1000, 01=100, 00=10 */
1033 #define MII_CR_LOOPBACK         0x4000  /* 0 = normal, 1 = loopback */
1034 #define MII_CR_RESET            0x8000  /* 0 = normal, 1 = PHY reset */
1035 #define MII_CR_SPEED_1000       0x0040
1036 #define MII_CR_SPEED_100        0x2000
1037 #define MII_CR_SPEED_10         0x0000
1038
1039 /* PHY Status Register */
1040 #define MII_SR_EXTENDED_CAPS     0x0001 /* Extended register capabilities */
1041 #define MII_SR_JABBER_DETECT     0x0002 /* Jabber Detected */
1042 #define MII_SR_LINK_STATUS       0x0004 /* Link Status 1 = link */
1043 #define MII_SR_AUTONEG_CAPS      0x0008 /* Auto Neg Capable */
1044 #define MII_SR_REMOTE_FAULT      0x0010 /* Remote Fault Detect */
1045 #define MII_SR_AUTONEG_COMPLETE  0x0020 /* Auto Neg Complete */
1046 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
1047 #define MII_SR_EXTENDED_STATUS   0x0100 /* Ext. status info in Reg 0x0F */
1048 #define MII_SR_100T2_HD_CAPS     0x0200 /* 100T2 Half Duplex Capable */
1049 #define MII_SR_100T2_FD_CAPS     0x0400 /* 100T2 Full Duplex Capable */
1050 #define MII_SR_10T_HD_CAPS       0x0800 /* 10T   Half Duplex Capable */
1051 #define MII_SR_10T_FD_CAPS       0x1000 /* 10T   Full Duplex Capable */
1052 #define MII_SR_100X_HD_CAPS      0x2000 /* 100X  Half Duplex Capable */
1053 #define MII_SR_100X_FD_CAPS      0x4000 /* 100X  Full Duplex Capable */
1054 #define MII_SR_100T4_CAPS        0x8000 /* 100T4 Capable */
1055
1056 /* Autoneg Advertisement Register */
1057 #define NWAY_AR_SELECTOR_FIELD   0x0001   /* indicates IEEE 802.3 CSMA/CD */
1058 #define NWAY_AR_10T_HD_CAPS      0x0020   /* 10T   Half Duplex Capable */
1059 #define NWAY_AR_10T_FD_CAPS      0x0040   /* 10T   Full Duplex Capable */
1060 #define NWAY_AR_100TX_HD_CAPS    0x0080   /* 100TX Half Duplex Capable */
1061 #define NWAY_AR_100TX_FD_CAPS    0x0100   /* 100TX Full Duplex Capable */
1062 #define NWAY_AR_100T4_CAPS       0x0200   /* 100T4 Capable */
1063 #define NWAY_AR_PAUSE            0x0400   /* Pause operation desired */
1064 #define NWAY_AR_ASM_DIR          0x0800   /* Asymmetric Pause Direction bit */
1065 #define NWAY_AR_REMOTE_FAULT     0x2000   /* Remote Fault detected */
1066 #define NWAY_AR_NEXT_PAGE        0x8000   /* Next Page ability supported */
1067
1068 /* Link Partner Ability Register (Base Page) */
1069 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
1070 #define NWAY_LPAR_10T_HD_CAPS    0x0020 /* LP is 10T   Half Duplex Capable */
1071 #define NWAY_LPAR_10T_FD_CAPS    0x0040 /* LP is 10T   Full Duplex Capable */
1072 #define NWAY_LPAR_100TX_HD_CAPS  0x0080 /* LP is 100TX Half Duplex Capable */
1073 #define NWAY_LPAR_100TX_FD_CAPS  0x0100 /* LP is 100TX Full Duplex Capable */
1074 #define NWAY_LPAR_100T4_CAPS     0x0200 /* LP is 100T4 Capable */
1075 #define NWAY_LPAR_PAUSE          0x0400 /* LP Pause operation desired */
1076 #define NWAY_LPAR_ASM_DIR        0x0800 /* LP Asymmetric Pause Direction bit */
1077 #define NWAY_LPAR_REMOTE_FAULT   0x2000 /* LP has detected Remote Fault */
1078 #define NWAY_LPAR_ACKNOWLEDGE    0x4000 /* LP has rx'd link code word */
1079 #define NWAY_LPAR_NEXT_PAGE      0x8000 /* Next Page ability supported */
1080
1081 /* Autoneg Expansion Register */
1082 #define NWAY_ER_LP_NWAY_CAPS      0x0001 /* LP has Auto Neg Capability */
1083 #define NWAY_ER_PAGE_RXD          0x0002 /* LP is 10T   Half Duplex Capable */
1084 #define NWAY_ER_NEXT_PAGE_CAPS    0x0004 /* LP is 10T   Full Duplex Capable */
1085 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
1086 #define NWAY_ER_PAR_DETECT_FAULT  0x0010 /* LP is 100TX Full Duplex Capable */
1087
1088 /* 1000BASE-T Control Register */
1089 #define CR_1000T_ASYM_PAUSE      0x0080 /* Advertise asymmetric pause bit */
1090 #define CR_1000T_HD_CAPS         0x0100 /* Advertise 1000T HD capability */
1091 #define CR_1000T_FD_CAPS         0x0200 /* Advertise 1000T FD capability  */
1092 #define CR_1000T_REPEATER_DTE    0x0400 /* 1=Repeater/switch device port */
1093                                         /* 0=DTE device */
1094 #define CR_1000T_MS_VALUE        0x0800 /* 1=Configure PHY as Master */
1095                                         /* 0=Configure PHY as Slave */
1096 #define CR_1000T_MS_ENABLE      0x1000 /* 1=Master/Slave manual config value */
1097                                         /* 0=Automatic Master/Slave config */
1098 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
1099 #define CR_1000T_TEST_MODE_1     0x2000 /* Transmit Waveform test */
1100 #define CR_1000T_TEST_MODE_2     0x4000 /* Master Transmit Jitter test */
1101 #define CR_1000T_TEST_MODE_3     0x6000 /* Slave Transmit Jitter test */
1102 #define CR_1000T_TEST_MODE_4     0x8000 /* Transmitter Distortion test */
1103
1104 /* 1000BASE-T Status Register */
1105 #define SR_1000T_IDLE_ERROR_CNT   0x00FF /* Num idle errors since last read */
1106 #define SR_1000T_ASYM_PAUSE_DIR  0x0100 /* LP asymmetric pause direction bit */
1107 #define SR_1000T_LP_HD_CAPS       0x0400 /* LP is 1000T HD capable */
1108 #define SR_1000T_LP_FD_CAPS       0x0800 /* LP is 1000T FD capable */
1109 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
1110 #define SR_1000T_LOCAL_RX_STATUS  0x2000 /* Local receiver OK */
1111 #define SR_1000T_MS_CONFIG_RES    0x4000 /* 1=Local Tx is Master, 0=Slave */
1112 #define SR_1000T_MS_CONFIG_FAULT  0x8000 /* Master/Slave config fault */
1113
1114 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
1115
1116 /* PHY 1000 MII Register/Bit Definitions */
1117 /* PHY Registers defined by IEEE */
1118 #define PHY_CONTROL      0x00 /* Control Register */
1119 #define PHY_STATUS       0x01 /* Status Register */
1120 #define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
1121 #define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
1122 #define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
1123 #define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
1124 #define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
1125 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
1126 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
1127 #define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
1128 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1129 #define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
1130
1131 #define PHY_CONTROL_LB   0x4000 /* PHY Loopback bit */
1132
1133 /* NVM Control */
1134 #define E1000_EECD_SK        0x00000001 /* NVM Clock */
1135 #define E1000_EECD_CS        0x00000002 /* NVM Chip Select */
1136 #define E1000_EECD_DI        0x00000004 /* NVM Data In */
1137 #define E1000_EECD_DO        0x00000008 /* NVM Data Out */
1138 #define E1000_EECD_FWE_MASK  0x00000030
1139 #define E1000_EECD_FWE_DIS   0x00000010 /* Disable FLASH writes */
1140 #define E1000_EECD_FWE_EN    0x00000020 /* Enable FLASH writes */
1141 #define E1000_EECD_FWE_SHIFT 4
1142 #define E1000_EECD_REQ       0x00000040 /* NVM Access Request */
1143 #define E1000_EECD_GNT       0x00000080 /* NVM Access Grant */
1144 #define E1000_EECD_PRES      0x00000100 /* NVM Present */
1145 #define E1000_EECD_SIZE      0x00000200 /* NVM Size (0=64 word 1=256 word) */
1146 /* NVM Addressing bits based on type 0=small, 1=large */
1147 #define E1000_EECD_ADDR_BITS 0x00000400
1148 #define E1000_EECD_TYPE      0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1149 #define E1000_NVM_GRANT_ATTEMPTS   1000 /* NVM # attempts to gain grant */
1150 #define E1000_EECD_AUTO_RD          0x00000200  /* NVM Auto Read done */
1151 #define E1000_EECD_SIZE_EX_MASK     0x00007800  /* NVM Size */
1152 #define E1000_EECD_SIZE_EX_SHIFT     11
1153 #define E1000_EECD_NVADDS    0x00018000 /* NVM Address Size */
1154 #define E1000_EECD_SELSHAD   0x00020000 /* Select Shadow RAM */
1155 #define E1000_EECD_INITSRAM  0x00040000 /* Initialize Shadow RAM */
1156 #define E1000_EECD_FLUPD     0x00080000 /* Update FLASH */
1157 #define E1000_EECD_AUPDEN    0x00100000 /* Enable Autonomous FLASH update */
1158 #define E1000_EECD_SHADV     0x00200000 /* Shadow RAM Data Valid */
1159 #define E1000_EECD_SEC1VAL   0x00400000 /* Sector One Valid */
1160 #define E1000_EECD_SECVAL_SHIFT      22
1161 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
1162
1163 #define E1000_NVM_SWDPIN0   0x0001   /* SWDPIN 0 NVM Value */
1164 #define E1000_NVM_LED_LOGIC 0x0020   /* Led Logic Word */
1165 #define E1000_NVM_RW_REG_DATA   16  /* Offset to data in NVM read/write regs */
1166 #define E1000_NVM_RW_REG_DONE   2    /* Offset to READ/WRITE done bit */
1167 #define E1000_NVM_RW_REG_START  1    /* Start operation */
1168 #define E1000_NVM_RW_ADDR_SHIFT 2    /* Shift to the address bits */
1169 #define E1000_NVM_POLL_WRITE    1    /* Flag for polling for write complete */
1170 #define E1000_NVM_POLL_READ     0    /* Flag for polling for read complete */
1171 #define E1000_FLASH_UPDATES  2000
1172
1173 /* NVM Word Offsets */
1174 #define NVM_COMPAT                 0x0003
1175 #define NVM_ID_LED_SETTINGS        0x0004
1176 #define NVM_VERSION                0x0005
1177 #define NVM_SERDES_AMPLITUDE       0x0006 /* SERDES output amplitude */
1178 #define NVM_PHY_CLASS_WORD         0x0007
1179 #define NVM_INIT_CONTROL1_REG      0x000A
1180 #define NVM_INIT_CONTROL2_REG      0x000F
1181 #define NVM_SWDEF_PINS_CTRL_PORT_1 0x0010
1182 #define NVM_INIT_CONTROL3_PORT_B   0x0014
1183 #define NVM_INIT_3GIO_3            0x001A
1184 #define NVM_SWDEF_PINS_CTRL_PORT_0 0x0020
1185 #define NVM_INIT_CONTROL3_PORT_A   0x0024
1186 #define NVM_CFG                    0x0012
1187 #define NVM_FLASH_VERSION          0x0032
1188 #define NVM_ALT_MAC_ADDR_PTR       0x0037
1189 #define NVM_CHECKSUM_REG           0x003F
1190
1191 #define E1000_NVM_CFG_DONE_PORT_0  0x040000 /* MNG config cycle done */
1192 #define E1000_NVM_CFG_DONE_PORT_1  0x080000 /* ...for second port */
1193
1194 /* Mask bits for fields in Word 0x0f of the NVM */
1195 #define NVM_WORD0F_PAUSE_MASK       0x3000
1196 #define NVM_WORD0F_PAUSE            0x1000
1197 #define NVM_WORD0F_ASM_DIR          0x2000
1198 #define NVM_WORD0F_ANE              0x0800
1199 #define NVM_WORD0F_SWPDIO_EXT_MASK  0x00F0
1200 #define NVM_WORD0F_LPLU             0x0001
1201
1202 /* Mask bits for fields in Word 0x1a of the NVM */
1203 #define NVM_WORD1A_ASPM_MASK  0x000C
1204
1205 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
1206 #define NVM_SUM                    0xBABA
1207
1208 #define NVM_MAC_ADDR_OFFSET        0
1209 #define NVM_PBA_OFFSET_0           8
1210 #define NVM_PBA_OFFSET_1           9
1211 #define NVM_RESERVED_WORD          0xFFFF
1212 #define NVM_PHY_CLASS_A            0x8000
1213 #define NVM_SERDES_AMPLITUDE_MASK  0x000F
1214 #define NVM_SIZE_MASK              0x1C00
1215 #define NVM_SIZE_SHIFT             10
1216 #define NVM_WORD_SIZE_BASE_SHIFT   6
1217 #define NVM_SWDPIO_EXT_SHIFT       4
1218
1219 /* NVM Commands - SPI */
1220 #define NVM_MAX_RETRY_SPI          5000 /* Max wait of 5ms, for RDY signal */
1221 #define NVM_READ_OPCODE_SPI        0x03 /* NVM read opcode */
1222 #define NVM_WRITE_OPCODE_SPI       0x02 /* NVM write opcode */
1223 #define NVM_A8_OPCODE_SPI          0x08 /* opcode bit-3 = address bit-8 */
1224 #define NVM_WREN_OPCODE_SPI        0x06 /* NVM set Write Enable latch */
1225 #define NVM_WRDI_OPCODE_SPI        0x04 /* NVM reset Write Enable latch */
1226 #define NVM_RDSR_OPCODE_SPI        0x05 /* NVM read Status register */
1227 #define NVM_WRSR_OPCODE_SPI        0x01 /* NVM write Status register */
1228
1229 /* SPI NVM Status Register */
1230 #define NVM_STATUS_RDY_SPI         0x01
1231 #define NVM_STATUS_WEN_SPI         0x02
1232 #define NVM_STATUS_BP0_SPI         0x04
1233 #define NVM_STATUS_BP1_SPI         0x08
1234 #define NVM_STATUS_WPEN_SPI        0x80
1235
1236 /* Word definitions for ID LED Settings */
1237 #define ID_LED_RESERVED_0000 0x0000
1238 #define ID_LED_RESERVED_FFFF 0xFFFF
1239 #define ID_LED_DEFAULT       ((ID_LED_OFF1_ON2  << 12) | \
1240                               (ID_LED_OFF1_OFF2 <<  8) | \
1241                               (ID_LED_DEF1_DEF2 <<  4) | \
1242                               (ID_LED_DEF1_DEF2))
1243 #define ID_LED_DEF1_DEF2     0x1
1244 #define ID_LED_DEF1_ON2      0x2
1245 #define ID_LED_DEF1_OFF2     0x3
1246 #define ID_LED_ON1_DEF2      0x4
1247 #define ID_LED_ON1_ON2       0x5
1248 #define ID_LED_ON1_OFF2      0x6
1249 #define ID_LED_OFF1_DEF2     0x7
1250 #define ID_LED_OFF1_ON2      0x8
1251 #define ID_LED_OFF1_OFF2     0x9
1252
1253 #define IGP_ACTIVITY_LED_MASK   0xFFFFF0FF
1254 #define IGP_ACTIVITY_LED_ENABLE 0x0300
1255 #define IGP_LED3_MODE           0x07000000
1256
1257 /* PCI/PCI-X/PCI-EX Config space */
1258 #define PCI_HEADER_TYPE_REGISTER     0x0E
1259 #define PCIE_LINK_STATUS             0x12
1260 #define PCIE_DEVICE_CONTROL2         0x28
1261
1262 #define PCI_HEADER_TYPE_MULTIFUNC    0x80
1263 #define PCIE_LINK_WIDTH_MASK         0x3F0
1264 #define PCIE_LINK_WIDTH_SHIFT        4
1265 #define PCIE_DEVICE_CONTROL2_16ms    0x0005
1266
1267 #ifndef ETH_ADDR_LEN
1268 #define ETH_ADDR_LEN                 6
1269 #endif
1270
1271 #define PHY_REVISION_MASK      0xFFFFFFF0
1272 #define MAX_PHY_REG_ADDRESS    0x1F  /* 5 bit address bus (0-0x1F) */
1273 #define MAX_PHY_MULTI_PAGE_REG 0xF
1274
1275 /* Bit definitions for valid PHY IDs. */
1276 /*
1277  * I = Integrated
1278  * E = External
1279  */
1280 #define M88E1000_E_PHY_ID    0x01410C50
1281 #define M88E1000_I_PHY_ID    0x01410C30
1282 #define M88E1011_I_PHY_ID    0x01410C20
1283 #define IGP01E1000_I_PHY_ID  0x02A80380
1284 #define M88E1011_I_REV_4     0x04
1285 #define M88E1111_I_PHY_ID    0x01410CC0
1286 #define GG82563_E_PHY_ID     0x01410CA0
1287 #define IGP03E1000_E_PHY_ID  0x02A80390
1288 #define IFE_E_PHY_ID         0x02A80330
1289 #define IFE_PLUS_E_PHY_ID    0x02A80320
1290 #define IFE_C_E_PHY_ID       0x02A80310
1291 #define IGP04E1000_E_PHY_ID  0x02A80391
1292 #define M88_VENDOR           0x0141
1293
1294 /* M88E1000 Specific Registers */
1295 #define M88E1000_PHY_SPEC_CTRL     0x10  /* PHY Specific Control Register */
1296 #define M88E1000_PHY_SPEC_STATUS   0x11  /* PHY Specific Status Register */
1297 #define M88E1000_INT_ENABLE        0x12  /* Interrupt Enable Register */
1298 #define M88E1000_INT_STATUS        0x13  /* Interrupt Status Register */
1299 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14  /* Extended PHY Specific Control */
1300 #define M88E1000_RX_ERR_CNTR       0x15  /* Receive Error Counter */
1301
1302 #define M88E1000_PHY_EXT_CTRL      0x1A  /* PHY extend control register */
1303 #define M88E1000_PHY_PAGE_SELECT   0x1D  /* Reg 29 for page number setting */
1304 #define M88E1000_PHY_GEN_CONTROL   0x1E  /* Its meaning depends on reg 29 */
1305 #define M88E1000_PHY_VCO_REG_BIT8  0x100 /* Bits 8 & 11 are adjusted for */
1306 #define M88E1000_PHY_VCO_REG_BIT11 0x800    /* improved BER performance */
1307
1308 /* M88E1000 PHY Specific Control Register */
1309 #define M88E1000_PSCR_JABBER_DISABLE    0x0001 /* 1=Jabber Function disabled */
1310 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reverse enabled */
1311 #define M88E1000_PSCR_SQE_TEST          0x0004 /* 1=SQE Test enabled */
1312 /* 1=CLK125 low, 0=CLK125 toggling */
1313 #define M88E1000_PSCR_CLK125_DISABLE    0x0010
1314 #define M88E1000_PSCR_MDI_MANUAL_MODE  0x0000 /* MDI Crossover Mode bits 6:5 */
1315                                                /* Manual MDI configuration */
1316 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020  /* Manual MDIX configuration */
1317 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1318 #define M88E1000_PSCR_AUTO_X_1000T     0x0040
1319 /* Auto crossover enabled all speeds */
1320 #define M88E1000_PSCR_AUTO_X_MODE      0x0060
1321 /*
1322  * 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
1323  * 0=Normal 10BASE-T Rx Threshold
1324  */
1325 #define M88E1000_PSCR_EN_10BT_EXT_DIST 0x0080
1326 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
1327 #define M88E1000_PSCR_MII_5BIT_ENABLE      0x0100
1328 #define M88E1000_PSCR_SCRAMBLER_DISABLE    0x0200 /* 1=Scrambler disable */
1329 #define M88E1000_PSCR_FORCE_LINK_GOOD      0x0400 /* 1=Force link good */
1330 #define M88E1000_PSCR_ASSERT_CRS_ON_TX     0x0800 /* 1=Assert CRS on Tx */
1331
1332 /* M88E1000 PHY Specific Status Register */
1333 #define M88E1000_PSSR_JABBER             0x0001 /* 1=Jabber */
1334 #define M88E1000_PSSR_REV_POLARITY       0x0002 /* 1=Polarity reversed */
1335 #define M88E1000_PSSR_DOWNSHIFT          0x0020 /* 1=Downshifted */
1336 #define M88E1000_PSSR_MDIX               0x0040 /* 1=MDIX; 0=MDI */
1337 /*
1338  * 0 = <50M
1339  * 1 = 50-80M
1340  * 2 = 80-110M
1341  * 3 = 110-140M
1342  * 4 = >140M
1343  */
1344 #define M88E1000_PSSR_CABLE_LENGTH       0x0380
1345 #define M88E1000_PSSR_LINK               0x0400 /* 1=Link up, 0=Link down */
1346 #define M88E1000_PSSR_SPD_DPLX_RESOLVED  0x0800 /* 1=Speed & Duplex resolved */
1347 #define M88E1000_PSSR_PAGE_RCVD          0x1000 /* 1=Page received */
1348 #define M88E1000_PSSR_DPLX               0x2000 /* 1=Duplex 0=Half Duplex */
1349 #define M88E1000_PSSR_SPEED              0xC000 /* Speed, bits 14:15 */
1350 #define M88E1000_PSSR_10MBS              0x0000 /* 00=10Mbs */
1351 #define M88E1000_PSSR_100MBS             0x4000 /* 01=100Mbs */
1352 #define M88E1000_PSSR_1000MBS            0x8000 /* 10=1000Mbs */
1353
1354 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1355
1356 /* M88E1000 Extended PHY Specific Control Register */
1357 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
1358 /*
1359  * 1 = Lost lock detect enabled.
1360  * Will assert lost lock and bring
1361  * link down if idle not seen
1362  * within 1ms in 1000BASE-T
1363  */
1364 #define M88E1000_EPSCR_DOWN_NO_IDLE   0x8000
1365 /*
1366  * Number of times we will attempt to autonegotiate before downshifting if we
1367  * are the master
1368  */
1369 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1370 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X   0x0000
1371 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X   0x0400
1372 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X   0x0800
1373 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X   0x0C00
1374 /*
1375  * Number of times we will attempt to autonegotiate before downshifting if we
1376  * are the slave
1377  */
1378 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK  0x0300
1379 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS   0x0000
1380 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X    0x0100
1381 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X    0x0200
1382 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X    0x0300
1383 #define M88E1000_EPSCR_TX_CLK_2_5     0x0060 /* 2.5 MHz TX_CLK */
1384 #define M88E1000_EPSCR_TX_CLK_25      0x0070 /* 25  MHz TX_CLK */
1385 #define M88E1000_EPSCR_TX_CLK_0       0x0000 /* NO  TX_CLK */
1386
1387 /* M88EC018 Rev 2 specific DownShift settings */
1388 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK  0x0E00
1389 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X    0x0000
1390 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X    0x0200
1391 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X    0x0400
1392 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X    0x0600
1393 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X    0x0800
1394 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X    0x0A00
1395 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X    0x0C00
1396 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X    0x0E00
1397
1398 /*
1399  * Bits...
1400  * 15-5: page
1401  * 4-0: register offset
1402  */
1403 #define GG82563_PAGE_SHIFT        5
1404 #define GG82563_REG(page, reg)    \
1405         (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1406 #define GG82563_MIN_ALT_REG       30
1407
1408 /* GG82563 Specific Registers */
1409 #define GG82563_PHY_SPEC_CTRL           \
1410         GG82563_REG(0, 16) /* PHY Specific Control */
1411 #define GG82563_PHY_SPEC_STATUS         \
1412         GG82563_REG(0, 17) /* PHY Specific Status */
1413 #define GG82563_PHY_INT_ENABLE          \
1414         GG82563_REG(0, 18) /* Interrupt Enable */
1415 #define GG82563_PHY_SPEC_STATUS_2       \
1416         GG82563_REG(0, 19) /* PHY Specific Status 2 */
1417 #define GG82563_PHY_RX_ERR_CNTR         \
1418         GG82563_REG(0, 21) /* Receive Error Counter */
1419 #define GG82563_PHY_PAGE_SELECT         \
1420         GG82563_REG(0, 22) /* Page Select */
1421 #define GG82563_PHY_SPEC_CTRL_2         \
1422         GG82563_REG(0, 26) /* PHY Specific Control 2 */
1423 #define GG82563_PHY_PAGE_SELECT_ALT     \
1424         GG82563_REG(0, 29) /* Alternate Page Select */
1425 #define GG82563_PHY_TEST_CLK_CTRL       \
1426         GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
1427
1428 #define GG82563_PHY_MAC_SPEC_CTRL       \
1429         GG82563_REG(2, 21) /* MAC Specific Control Register */
1430 #define GG82563_PHY_MAC_SPEC_CTRL_2     \
1431         GG82563_REG(2, 26) /* MAC Specific Control 2 */
1432
1433 #define GG82563_PHY_DSP_DISTANCE    \
1434         GG82563_REG(5, 26) /* DSP Distance */
1435
1436 /* Page 193 - Port Control Registers */
1437 #define GG82563_PHY_KMRN_MODE_CTRL   \
1438         GG82563_REG(193, 16) /* Kumeran Mode Control */
1439 #define GG82563_PHY_PORT_RESET          \
1440         GG82563_REG(193, 17) /* Port Reset */
1441 #define GG82563_PHY_REVISION_ID         \
1442         GG82563_REG(193, 18) /* Revision ID */
1443 #define GG82563_PHY_DEVICE_ID           \
1444         GG82563_REG(193, 19) /* Device ID */
1445 #define GG82563_PHY_PWR_MGMT_CTRL       \
1446         GG82563_REG(193, 20) /* Power Management Control */
1447 #define GG82563_PHY_RATE_ADAPT_CTRL     \
1448         GG82563_REG(193, 25) /* Rate Adaptation Control */
1449
1450 /* Page 194 - KMRN Registers */
1451 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \
1452         GG82563_REG(194, 16) /* FIFO's Control/Status */
1453 #define GG82563_PHY_KMRN_CTRL           \
1454         GG82563_REG(194, 17) /* Control */
1455 #define GG82563_PHY_INBAND_CTRL         \
1456         GG82563_REG(194, 18) /* Inband Control */
1457 #define GG82563_PHY_KMRN_DIAGNOSTIC     \
1458         GG82563_REG(194, 19) /* Diagnostic */
1459 #define GG82563_PHY_ACK_TIMEOUTS        \
1460         GG82563_REG(194, 20) /* Acknowledge Timeouts */
1461 #define GG82563_PHY_ADV_ABILITY         \
1462         GG82563_REG(194, 21) /* Advertised Ability */
1463 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \
1464         GG82563_REG(194, 23) /* Link Partner Advertised Ability */
1465 #define GG82563_PHY_ADV_NEXT_PAGE       \
1466         GG82563_REG(194, 24) /* Advertised Next Page */
1467 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \
1468         GG82563_REG(194, 25) /* Link Partner Advertised Next page */
1469 #define GG82563_PHY_KMRN_MISC           \
1470         GG82563_REG(194, 26) /* Misc. */
1471
1472 /* MDI Control */
1473 #define E1000_MDIC_DATA_MASK 0x0000FFFF
1474 #define E1000_MDIC_REG_MASK  0x001F0000
1475 #define E1000_MDIC_REG_SHIFT 16
1476 #define E1000_MDIC_PHY_MASK  0x03E00000
1477 #define E1000_MDIC_PHY_SHIFT 21
1478 #define E1000_MDIC_OP_WRITE  0x04000000
1479 #define E1000_MDIC_OP_READ   0x08000000
1480 #define E1000_MDIC_READY     0x10000000
1481 #define E1000_MDIC_INT_EN    0x20000000
1482 #define E1000_MDIC_ERROR     0x40000000
1483
1484 /* SerDes Control */
1485 #define E1000_GEN_CTL_READY             0x80000000
1486 #define E1000_GEN_CTL_ADDRESS_SHIFT     8
1487 #define E1000_GEN_POLL_TIMEOUT          640
1488
1489 /* LinkSec register fields */
1490 #define E1000_LSECTXCAP_SUM_MASK        0x00FF0000
1491 #define E1000_LSECTXCAP_SUM_SHIFT       16
1492 #define E1000_LSECRXCAP_SUM_MASK        0x00FF0000
1493 #define E1000_LSECRXCAP_SUM_SHIFT       16
1494
1495 #define E1000_LSECTXCTRL_EN_MASK        0x00000003
1496 #define E1000_LSECTXCTRL_DISABLE        0x0
1497 #define E1000_LSECTXCTRL_AUTH           0x1
1498 #define E1000_LSECTXCTRL_AUTH_ENCRYPT   0x2
1499 #define E1000_LSECTXCTRL_AISCI          0x00000020
1500 #define E1000_LSECTXCTRL_PNTHRSH_MASK   0xFFFFFF00
1501 #define E1000_LSECTXCTRL_RSV_MASK       0x000000D8
1502
1503 #define E1000_LSECRXCTRL_EN_MASK        0x0000000C
1504 #define E1000_LSECRXCTRL_EN_SHIFT       2
1505 #define E1000_LSECRXCTRL_DISABLE        0x0
1506 #define E1000_LSECRXCTRL_CHECK          0x1
1507 #define E1000_LSECRXCTRL_STRICT         0x2
1508 #define E1000_LSECRXCTRL_DROP           0x3
1509 #define E1000_LSECRXCTRL_PLSH           0x00000040
1510 #define E1000_LSECRXCTRL_RP             0x00000080
1511 #define E1000_LSECRXCTRL_RSV_MASK       0xFFFFFF33
1512
1513
1514
1515 #endif /* _IGB_DEFINES_H_ */