?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[contrib] Allow Network Protocol header to display in rom-o-matic
[gpxe.git] / src / drivers / net / e1000 / e1000_phy.c
blobb3cad4809394aec813f4321fead102dc491e1d1c
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 FILE_LICENCE ( GPL2_OR_LATER );
30
31 #include "e1000_api.h"
32
33 #if 0
34 /* Cable length tables */
35 static const u16 e1000_m88_cable_length_table[] =
36 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
37 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
38 (sizeof(e1000_m88_cable_length_table) / \
39 sizeof(e1000_m88_cable_length_table[0]))
40
41 static const u16 e1000_igp_2_cable_length_table[] =
42 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
43 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
44 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
45 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
46 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
47 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
48 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
49 104, 109, 114, 118, 121, 124};
50 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
51 (sizeof(e1000_igp_2_cable_length_table) / \
52 sizeof(e1000_igp_2_cable_length_table[0]))
53 #endif
54
55 /**
56 * e1000_init_phy_ops_generic - Initialize PHY function pointers
57 * @hw: pointer to the HW structure
58 *
59 * Setups up the function pointers to no-op functions
60 **/
61 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
62 {
63 struct e1000_phy_info *phy = &hw->phy;
64 DEBUGFUNC("e1000_init_phy_ops_generic");
65
66 /* Initialize function pointers */
67 phy->ops.init_params = e1000_null_ops_generic;
68 phy->ops.acquire = e1000_null_ops_generic;
69 phy->ops.check_polarity = e1000_null_ops_generic;
70 phy->ops.check_reset_block = e1000_null_ops_generic;
71 phy->ops.commit = e1000_null_ops_generic;
72 #if 0
73 phy->ops.force_speed_duplex = e1000_null_ops_generic;
74 #endif
75 phy->ops.get_cfg_done = e1000_null_ops_generic;
76 #if 0
77 phy->ops.get_cable_length = e1000_null_ops_generic;
78 #endif
79 phy->ops.get_info = e1000_null_ops_generic;
80 phy->ops.read_reg = e1000_null_read_reg;
81 phy->ops.release = e1000_null_phy_generic;
82 phy->ops.reset = e1000_null_ops_generic;
83 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
84 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
85 phy->ops.write_reg = e1000_null_write_reg;
86 phy->ops.power_up = e1000_null_phy_generic;
87 phy->ops.power_down = e1000_null_phy_generic;
88 }
89
90 /**
91 * e1000_null_read_reg - No-op function, return 0
92 * @hw: pointer to the HW structure
93 **/
94 s32 e1000_null_read_reg(struct e1000_hw *hw __unused, u32 offset __unused,
95 u16 *data __unused)
96 {
97 DEBUGFUNC("e1000_null_read_reg");
98 return E1000_SUCCESS;
99 }
100
101 /**
102 * e1000_null_phy_generic - No-op function, return void
103 * @hw: pointer to the HW structure
104 **/
105 void e1000_null_phy_generic(struct e1000_hw *hw __unused)
106 {
107 DEBUGFUNC("e1000_null_phy_generic");
108 return;
109 }
110
111 /**
112 * e1000_null_lplu_state - No-op function, return 0
113 * @hw: pointer to the HW structure
114 **/
115 s32 e1000_null_lplu_state(struct e1000_hw *hw __unused, bool active __unused)
116 {
117 DEBUGFUNC("e1000_null_lplu_state");
118 return E1000_SUCCESS;
119 }
120
121 /**
122 * e1000_null_write_reg - No-op function, return 0
123 * @hw: pointer to the HW structure
124 **/
125 s32 e1000_null_write_reg(struct e1000_hw *hw __unused, u32 offset __unused,
126 u16 data __unused)
127 {
128 DEBUGFUNC("e1000_null_write_reg");
129 return E1000_SUCCESS;
130 }
131
132 /**
133 * e1000_check_reset_block_generic - Check if PHY reset is blocked
134 * @hw: pointer to the HW structure
135 *
136 * Read the PHY management control register and check whether a PHY reset
137 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
138 * return E1000_BLK_PHY_RESET (12).
139 **/
140 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
141 {
142 u32 manc;
143
144 DEBUGFUNC("e1000_check_reset_block");
145
146 manc = E1000_READ_REG(hw, E1000_MANC);
147
148 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
149 E1000_BLK_PHY_RESET : E1000_SUCCESS;
150 }
151
152 /**
153 * e1000_get_phy_id - Retrieve the PHY ID and revision
154 * @hw: pointer to the HW structure
155 *
156 * Reads the PHY registers and stores the PHY ID and possibly the PHY
157 * revision in the hardware structure.
158 **/
159 s32 e1000_get_phy_id(struct e1000_hw *hw)
160 {
161 struct e1000_phy_info *phy = &hw->phy;
162 s32 ret_val = E1000_SUCCESS;
163 u16 phy_id;
164
165 DEBUGFUNC("e1000_get_phy_id");
166
167 if (!(phy->ops.read_reg))
168 goto out;
169
170 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
171 if (ret_val)
172 goto out;
173
174 phy->id = (u32)(phy_id << 16);
175 usec_delay(20);
176 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
177 if (ret_val)
178 goto out;
179
180 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
181 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
182
183 out:
184 return ret_val;
185 }
186
187 /**
188 * e1000_phy_reset_dsp_generic - Reset PHY DSP
189 * @hw: pointer to the HW structure
190 *
191 * Reset the digital signal processor.
192 **/
193 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
194 {
195 s32 ret_val = E1000_SUCCESS;
196
197 DEBUGFUNC("e1000_phy_reset_dsp_generic");
198
199 if (!(hw->phy.ops.write_reg))
200 goto out;
201
202 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
203 if (ret_val)
204 goto out;
205
206 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
207
208 out:
209 return ret_val;
210 }
211
212 /**
213 * e1000_read_phy_reg_mdic - Read MDI control register
214 * @hw: pointer to the HW structure
215 * @offset: register offset to be read
216 * @data: pointer to the read data
217 *
218 * Reads the MDI control register in the PHY at offset and stores the
219 * information read to data.
220 **/
221 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
222 {
223 struct e1000_phy_info *phy = &hw->phy;
224 u32 i, mdic = 0;
225 s32 ret_val = E1000_SUCCESS;
226
227 DEBUGFUNC("e1000_read_phy_reg_mdic");
228
229 /*
230 * Set up Op-code, Phy Address, and register offset in the MDI
231 * Control register. The MAC will take care of interfacing with the
232 * PHY to retrieve the desired data.
233 */
234 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
235 (phy->addr << E1000_MDIC_PHY_SHIFT) |
236 (E1000_MDIC_OP_READ));
237
238 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
239
240 /*
241 * Poll the ready bit to see if the MDI read completed
242 * Increasing the time out as testing showed failures with
243 * the lower time out
244 */
245 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
246 usec_delay(50);
247 mdic = E1000_READ_REG(hw, E1000_MDIC);
248 if (mdic & E1000_MDIC_READY)
249 break;
250 }
251 if (!(mdic & E1000_MDIC_READY)) {
252 DEBUGOUT("MDI Read did not complete\n");
253 ret_val = -E1000_ERR_PHY;
254 goto out;
255 }
256 if (mdic & E1000_MDIC_ERROR) {
257 DEBUGOUT("MDI Error\n");
258 ret_val = -E1000_ERR_PHY;
259 goto out;
260 }
261 *data = (u16) mdic;
262
263 out:
264 return ret_val;
265 }
266
267 /**
268 * e1000_write_phy_reg_mdic - Write MDI control register
269 * @hw: pointer to the HW structure
270 * @offset: register offset to write to
271 * @data: data to write to register at offset
272 *
273 * Writes data to MDI control register in the PHY at offset.
274 **/
275 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
276 {
277 struct e1000_phy_info *phy = &hw->phy;
278 u32 i, mdic = 0;
279 s32 ret_val = E1000_SUCCESS;
280
281 DEBUGFUNC("e1000_write_phy_reg_mdic");
282
283 /*
284 * Set up Op-code, Phy Address, and register offset in the MDI
285 * Control register. The MAC will take care of interfacing with the
286 * PHY to retrieve the desired data.
287 */
288 mdic = (((u32)data) |
289 (offset << E1000_MDIC_REG_SHIFT) |
290 (phy->addr << E1000_MDIC_PHY_SHIFT) |
291 (E1000_MDIC_OP_WRITE));
292
293 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
294
295 /*
296 * Poll the ready bit to see if the MDI read completed
297 * Increasing the time out as testing showed failures with
298 * the lower time out
299 */
300 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
301 usec_delay(50);
302 mdic = E1000_READ_REG(hw, E1000_MDIC);
303 if (mdic & E1000_MDIC_READY)
304 break;
305 }
306 if (!(mdic & E1000_MDIC_READY)) {
307 DEBUGOUT("MDI Write did not complete\n");
308 ret_val = -E1000_ERR_PHY;
309 goto out;
310 }
311 if (mdic & E1000_MDIC_ERROR) {
312 DEBUGOUT("MDI Error\n");
313 ret_val = -E1000_ERR_PHY;
314 goto out;
315 }
316
317 out:
318 return ret_val;
319 }
320
321 /**
322 * e1000_read_phy_reg_m88 - Read m88 PHY register
323 * @hw: pointer to the HW structure
324 * @offset: register offset to be read
325 * @data: pointer to the read data
326 *
327 * Acquires semaphore, if necessary, then reads the PHY register at offset
328 * and storing the retrieved information in data. Release any acquired
329 * semaphores before exiting.
330 **/
331 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
332 {
333 s32 ret_val = E1000_SUCCESS;
334
335 DEBUGFUNC("e1000_read_phy_reg_m88");
336
337 if (!(hw->phy.ops.acquire))
338 goto out;
339
340 ret_val = hw->phy.ops.acquire(hw);
341 if (ret_val)
342 goto out;
343
344 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
345 data);
346
347 hw->phy.ops.release(hw);
348
349 out:
350 return ret_val;
351 }
352
353 /**
354 * e1000_write_phy_reg_m88 - Write m88 PHY register
355 * @hw: pointer to the HW structure
356 * @offset: register offset to write to
357 * @data: data to write at register offset
358 *
359 * Acquires semaphore, if necessary, then writes the data to PHY register
360 * at the offset. Release any acquired semaphores before exiting.
361 **/
362 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
363 {
364 s32 ret_val = E1000_SUCCESS;
365
366 DEBUGFUNC("e1000_write_phy_reg_m88");
367
368 if (!(hw->phy.ops.acquire))
369 goto out;
370
371 ret_val = hw->phy.ops.acquire(hw);
372 if (ret_val)
373 goto out;
374
375 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
376 data);
377
378 hw->phy.ops.release(hw);
379
380 out:
381 return ret_val;
382 }
383
384 /**
385 * e1000_read_phy_reg_igp - Read igp PHY register
386 * @hw: pointer to the HW structure
387 * @offset: register offset to be read
388 * @data: pointer to the read data
389 *
390 * Acquires semaphore, if necessary, then reads the PHY register at offset
391 * and storing the retrieved information in data. Release any acquired
392 * semaphores before exiting.
393 **/
394 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
395 {
396 s32 ret_val = E1000_SUCCESS;
397
398 DEBUGFUNC("e1000_read_phy_reg_igp");
399
400 if (!(hw->phy.ops.acquire))
401 goto out;
402
403 ret_val = hw->phy.ops.acquire(hw);
404 if (ret_val)
405 goto out;
406
407 if (offset > MAX_PHY_MULTI_PAGE_REG) {
408 ret_val = e1000_write_phy_reg_mdic(hw,
409 IGP01E1000_PHY_PAGE_SELECT,
410 (u16)offset);
411 if (ret_val) {
412 hw->phy.ops.release(hw);
413 goto out;
414 }
415 }
416
417 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
418 data);
419
420 hw->phy.ops.release(hw);
421
422 out:
423 return ret_val;
424 }
425
426 /**
427 * e1000_write_phy_reg_igp - Write igp PHY register
428 * @hw: pointer to the HW structure
429 * @offset: register offset to write to
430 * @data: data to write at register offset
431 *
432 * Acquires semaphore, if necessary, then writes the data to PHY register
433 * at the offset. Release any acquired semaphores before exiting.
434 **/
435 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
436 {
437 s32 ret_val = E1000_SUCCESS;
438
439 DEBUGFUNC("e1000_write_phy_reg_igp");
440
441 if (!(hw->phy.ops.acquire))
442 goto out;
443
444 ret_val = hw->phy.ops.acquire(hw);
445 if (ret_val)
446 goto out;
447
448 if (offset > MAX_PHY_MULTI_PAGE_REG) {
449 ret_val = e1000_write_phy_reg_mdic(hw,
450 IGP01E1000_PHY_PAGE_SELECT,
451 (u16)offset);
452 if (ret_val) {
453 hw->phy.ops.release(hw);
454 goto out;
455 }
456 }
457
458 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
459 data);
460
461 hw->phy.ops.release(hw);
462
463 out:
464 return ret_val;
465 }
466
467 /**
468 * e1000_read_kmrn_reg_generic - Read kumeran register
469 * @hw: pointer to the HW structure
470 * @offset: register offset to be read
471 * @data: pointer to the read data
472 *
473 * Acquires semaphore, if necessary. Then reads the PHY register at offset
474 * using the kumeran interface. The information retrieved is stored in data.
475 * Release any acquired semaphores before exiting.
476 **/
477 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
478 {
479 u32 kmrnctrlsta;
480 s32 ret_val = E1000_SUCCESS;
481
482 DEBUGFUNC("e1000_read_kmrn_reg_generic");
483
484 if (!(hw->phy.ops.acquire))
485 goto out;
486
487 ret_val = hw->phy.ops.acquire(hw);
488 if (ret_val)
489 goto out;
490
491 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
492 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
493 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
494
495 usec_delay(2);
496
497 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
498 *data = (u16)kmrnctrlsta;
499
500 hw->phy.ops.release(hw);
501
502 out:
503 return ret_val;
504 }
505
506 /**
507 * e1000_write_kmrn_reg_generic - Write kumeran register
508 * @hw: pointer to the HW structure
509 * @offset: register offset to write to
510 * @data: data to write at register offset
511 *
512 * Acquires semaphore, if necessary. Then write the data to PHY register
513 * at the offset using the kumeran interface. Release any acquired semaphores
514 * before exiting.
515 **/
516 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
517 {
518 u32 kmrnctrlsta;
519 s32 ret_val = E1000_SUCCESS;
520
521 DEBUGFUNC("e1000_write_kmrn_reg_generic");
522
523 if (!(hw->phy.ops.acquire))
524 goto out;
525
526 ret_val = hw->phy.ops.acquire(hw);
527 if (ret_val)
528 goto out;
529
530 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
531 E1000_KMRNCTRLSTA_OFFSET) | data;
532 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
533
534 usec_delay(2);
535 hw->phy.ops.release(hw);
536
537 out:
538 return ret_val;
539 }
540
541 /**
542 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
543 * @hw: pointer to the HW structure
544 *
545 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
546 * and downshift values are set also.
547 **/
548 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
549 {
550 struct e1000_phy_info *phy = &hw->phy;
551 s32 ret_val;
552 u16 phy_data;
553
554 DEBUGFUNC("e1000_copper_link_setup_m88");
555
556 if (phy->reset_disable) {
557 ret_val = E1000_SUCCESS;
558 goto out;
559 }
560
561 /* Enable CRS on TX. This must be set for half-duplex operation. */
562 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
563 if (ret_val)
564 goto out;
565
566 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
567
568 /*
569 * Options:
570 * MDI/MDI-X = 0 (default)
571 * 0 - Auto for all speeds
572 * 1 - MDI mode
573 * 2 - MDI-X mode
574 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
575 */
576 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
577
578 switch (phy->mdix) {
579 case 1:
580 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
581 break;
582 case 2:
583 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
584 break;
585 case 3:
586 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
587 break;
588 case 0:
589 default:
590 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
591 break;
592 }
593
594 /*
595 * Options:
596 * disable_polarity_correction = 0 (default)
597 * Automatic Correction for Reversed Cable Polarity
598 * 0 - Disabled
599 * 1 - Enabled
600 */
601 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
602 if (phy->disable_polarity_correction == 1)
603 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
604
605 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
606 if (ret_val)
607 goto out;
608
609 if (phy->revision < E1000_REVISION_4) {
610 /*
611 * Force TX_CLK in the Extended PHY Specific Control Register
612 * to 25MHz clock.
613 */
614 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
615 &phy_data);
616 if (ret_val)
617 goto out;
618
619 phy_data |= M88E1000_EPSCR_TX_CLK_25;
620
621 if ((phy->revision == E1000_REVISION_2) &&
622 (phy->id == M88E1111_I_PHY_ID)) {
623 /* 82573L PHY - set the downshift counter to 5x. */
624 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
625 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
626 } else {
627 /* Configure Master and Slave downshift values */
628 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
629 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
630 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
631 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
632 }
633 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
634 phy_data);
635 if (ret_val)
636 goto out;
637 }
638
639 /* Commit the changes. */
640 ret_val = phy->ops.commit(hw);
641 if (ret_val) {
642 DEBUGOUT("Error committing the PHY changes\n");
643 goto out;
644 }
645
646 out:
647 return ret_val;
648 }
649
650 /**
651 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
652 * @hw: pointer to the HW structure
653 *
654 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
655 * igp PHY's.
656 **/
657 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
658 {
659 struct e1000_phy_info *phy = &hw->phy;
660 s32 ret_val;
661 u16 data;
662
663 DEBUGFUNC("e1000_copper_link_setup_igp");
664
665 if (phy->reset_disable) {
666 ret_val = E1000_SUCCESS;
667 goto out;
668 }
669
670 ret_val = hw->phy.ops.reset(hw);
671 if (ret_val) {
672 DEBUGOUT("Error resetting the PHY.\n");
673 goto out;
674 }
675
676 /*
677 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
678 * timeout issues when LFS is enabled.
679 */
680 msec_delay(100);
681
682 /*
683 * The NVM settings will configure LPLU in D3 for
684 * non-IGP1 PHYs.
685 */
686 if (phy->type == e1000_phy_igp) {
687 /* disable lplu d3 during driver init */
688 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
689 if (ret_val) {
690 DEBUGOUT("Error Disabling LPLU D3\n");
691 goto out;
692 }
693 }
694
695 /* disable lplu d0 during driver init */
696 if (hw->phy.ops.set_d0_lplu_state) {
697 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
698 if (ret_val) {
699 DEBUGOUT("Error Disabling LPLU D0\n");
700 goto out;
701 }
702 }
703 /* Configure mdi-mdix settings */
704 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
705 if (ret_val)
706 goto out;
707
708 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
709
710 switch (phy->mdix) {
711 case 1:
712 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
713 break;
714 case 2:
715 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
716 break;
717 case 0:
718 default:
719 data |= IGP01E1000_PSCR_AUTO_MDIX;
720 break;
721 }
722 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
723 if (ret_val)
724 goto out;
725
726 /* set auto-master slave resolution settings */
727 if (hw->mac.autoneg) {
728 /*
729 * when autonegotiation advertisement is only 1000Mbps then we
730 * should disable SmartSpeed and enable Auto MasterSlave
731 * resolution as hardware default.
732 */
733 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
734 /* Disable SmartSpeed */
735 ret_val = phy->ops.read_reg(hw,
736 IGP01E1000_PHY_PORT_CONFIG,
737 &data);
738 if (ret_val)
739 goto out;
740
741 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
742 ret_val = phy->ops.write_reg(hw,
743 IGP01E1000_PHY_PORT_CONFIG,
744 data);
745 if (ret_val)
746 goto out;
747
748 /* Set auto Master/Slave resolution process */
749 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
750 if (ret_val)
751 goto out;
752
753 data &= ~CR_1000T_MS_ENABLE;
754 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
755 if (ret_val)
756 goto out;
757 }
758
759 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
760 if (ret_val)
761 goto out;
762
763 /* load defaults for future use */
764 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
765 ((data & CR_1000T_MS_VALUE) ?
766 e1000_ms_force_master :
767 e1000_ms_force_slave) :
768 e1000_ms_auto;
769
770 switch (phy->ms_type) {
771 case e1000_ms_force_master:
772 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
773 break;
774 case e1000_ms_force_slave:
775 data |= CR_1000T_MS_ENABLE;
776 data &= ~(CR_1000T_MS_VALUE);
777 break;
778 case e1000_ms_auto:
779 data &= ~CR_1000T_MS_ENABLE;
780 default:
781 break;
782 }
783 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
784 if (ret_val)
785 goto out;
786 }
787
788 out:
789 return ret_val;
790 }
791
792 /**
793 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
794 * @hw: pointer to the HW structure
795 *
796 * Performs initial bounds checking on autoneg advertisement parameter, then
797 * configure to advertise the full capability. Setup the PHY to autoneg
798 * and restart the negotiation process between the link partner. If
799 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
800 **/
801 s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
802 {
803 struct e1000_phy_info *phy = &hw->phy;
804 s32 ret_val;
805 u16 phy_ctrl;
806
807 DEBUGFUNC("e1000_copper_link_autoneg");
808
809 /*
810 * Perform some bounds checking on the autoneg advertisement
811 * parameter.
812 */
813 phy->autoneg_advertised &= phy->autoneg_mask;
814
815 /*
816 * If autoneg_advertised is zero, we assume it was not defaulted
817 * by the calling code so we set to advertise full capability.
818 */
819 if (phy->autoneg_advertised == 0)
820 phy->autoneg_advertised = phy->autoneg_mask;
821
822 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
823 ret_val = e1000_phy_setup_autoneg(hw);
824 if (ret_val) {
825 DEBUGOUT("Error Setting up Auto-Negotiation\n");
826 goto out;
827 }
828 DEBUGOUT("Restarting Auto-Neg\n");
829
830 /*
831 * Restart auto-negotiation by setting the Auto Neg Enable bit and
832 * the Auto Neg Restart bit in the PHY control register.
833 */
834 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
835 if (ret_val)
836 goto out;
837
838 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
839 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
840 if (ret_val)
841 goto out;
842
843 /*
844 * Does the user want to wait for Auto-Neg to complete here, or
845 * check at a later time (for example, callback routine).
846 */
847 if (phy->autoneg_wait_to_complete) {
848 ret_val = hw->mac.ops.wait_autoneg(hw);
849 if (ret_val) {
850 DEBUGOUT("Error while waiting for "
851 "autoneg to complete\n");
852 goto out;
853 }
854 }
855
856 hw->mac.get_link_status = true;
857
858 out:
859 return ret_val;
860 }
861
862 /**
863 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
864 * @hw: pointer to the HW structure
865 *
866 * Reads the MII auto-neg advertisement register and/or the 1000T control
867 * register and if the PHY is already setup for auto-negotiation, then
868 * return successful. Otherwise, setup advertisement and flow control to
869 * the appropriate values for the wanted auto-negotiation.
870 **/
871 s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
872 {
873 struct e1000_phy_info *phy = &hw->phy;
874 s32 ret_val;
875 u16 mii_autoneg_adv_reg;
876 u16 mii_1000t_ctrl_reg = 0;
877
878 DEBUGFUNC("e1000_phy_setup_autoneg");
879
880 phy->autoneg_advertised &= phy->autoneg_mask;
881
882 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
883 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
884 if (ret_val)
885 goto out;
886
887 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
888 /* Read the MII 1000Base-T Control Register (Address 9). */
889 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
890 &mii_1000t_ctrl_reg);
891 if (ret_val)
892 goto out;
893 }
894
895 /*
896 * Need to parse both autoneg_advertised and fc and set up
897 * the appropriate PHY registers. First we will parse for
898 * autoneg_advertised software override. Since we can advertise
899 * a plethora of combinations, we need to check each bit
900 * individually.
901 */
902
903 /*
904 * First we clear all the 10/100 mb speed bits in the Auto-Neg
905 * Advertisement Register (Address 4) and the 1000 mb speed bits in
906 * the 1000Base-T Control Register (Address 9).
907 */
908 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
909 NWAY_AR_100TX_HD_CAPS |
910 NWAY_AR_10T_FD_CAPS |
911 NWAY_AR_10T_HD_CAPS);
912 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
913
914 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
915
916 /* Do we want to advertise 10 Mb Half Duplex? */
917 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
918 DEBUGOUT("Advertise 10mb Half duplex\n");
919 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
920 }
921
922 /* Do we want to advertise 10 Mb Full Duplex? */
923 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
924 DEBUGOUT("Advertise 10mb Full duplex\n");
925 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
926 }
927
928 /* Do we want to advertise 100 Mb Half Duplex? */
929 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
930 DEBUGOUT("Advertise 100mb Half duplex\n");
931 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
932 }
933
934 /* Do we want to advertise 100 Mb Full Duplex? */
935 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
936 DEBUGOUT("Advertise 100mb Full duplex\n");
937 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
938 }
939
940 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
941 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
942 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
943
944 /* Do we want to advertise 1000 Mb Full Duplex? */
945 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
946 DEBUGOUT("Advertise 1000mb Full duplex\n");
947 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
948 }
949
950 /*
951 * Check for a software override of the flow control settings, and
952 * setup the PHY advertisement registers accordingly. If
953 * auto-negotiation is enabled, then software will have to set the
954 * "PAUSE" bits to the correct value in the Auto-Negotiation
955 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
956 * negotiation.
957 *
958 * The possible values of the "fc" parameter are:
959 * 0: Flow control is completely disabled
960 * 1: Rx flow control is enabled (we can receive pause frames
961 * but not send pause frames).
962 * 2: Tx flow control is enabled (we can send pause frames
963 * but we do not support receiving pause frames).
964 * 3: Both Rx and Tx flow control (symmetric) are enabled.
965 * other: No software override. The flow control configuration
966 * in the EEPROM is used.
967 */
968 switch (hw->fc.current_mode) {
969 case e1000_fc_none:
970 /*
971 * Flow control (Rx & Tx) is completely disabled by a
972 * software over-ride.
973 */
974 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
975 break;
976 case e1000_fc_rx_pause:
977 /*
978 * Rx Flow control is enabled, and Tx Flow control is
979 * disabled, by a software over-ride.
980 *
981 * Since there really isn't a way to advertise that we are
982 * capable of Rx Pause ONLY, we will advertise that we
983 * support both symmetric and asymmetric Rx PAUSE. Later
984 * (in e1000_config_fc_after_link_up) we will disable the
985 * hw's ability to send PAUSE frames.
986 */
987 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
988 break;
989 case e1000_fc_tx_pause:
990 /*
991 * Tx Flow control is enabled, and Rx Flow control is
992 * disabled, by a software over-ride.
993 */
994 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
995 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
996 break;
997 case e1000_fc_full:
998 /*
999 * Flow control (both Rx and Tx) is enabled by a software
1000 * over-ride.
1001 */
1002 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1003 break;
1004 default:
1005 DEBUGOUT("Flow control param set incorrectly\n");
1006 ret_val = -E1000_ERR_CONFIG;
1007 goto out;
1008 }
1009
1010 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1011 if (ret_val)
1012 goto out;
1013
1014 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1015
1016 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1017 ret_val = phy->ops.write_reg(hw,
1018 PHY_1000T_CTRL,
1019 mii_1000t_ctrl_reg);
1020 if (ret_val)
1021 goto out;
1022 }
1023
1024 out:
1025 return ret_val;
1026 }
1027
1028 /**
1029 * e1000_setup_copper_link_generic - Configure copper link settings
1030 * @hw: pointer to the HW structure
1031 *
1032 * Calls the appropriate function to configure the link for auto-neg or forced
1033 * speed and duplex. Then we check for link, once link is established calls
1034 * to configure collision distance and flow control are called. If link is
1035 * not established, we return -E1000_ERR_PHY (-2).
1036 **/
1037 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1038 {
1039 s32 ret_val;
1040 bool link;
1041
1042 DEBUGFUNC("e1000_setup_copper_link_generic");
1043
1044 if (hw->mac.autoneg) {
1045 /*
1046 * Setup autoneg and flow control advertisement and perform
1047 * autonegotiation.
1048 */
1049 ret_val = e1000_copper_link_autoneg(hw);
1050 if (ret_val)
1051 goto out;
1052 } else {
1053 #if 0
1054 /*
1055 * PHY will be set to 10H, 10F, 100H or 100F
1056 * depending on user settings.
1057 */
1058 DEBUGOUT("Forcing Speed and Duplex\n");
1059 ret_val = hw->phy.ops.force_speed_duplex(hw);
1060 if (ret_val) {
1061 DEBUGOUT("Error Forcing Speed and Duplex\n");
1062 goto out;
1063 }
1064 #endif
1065 }
1066
1067 /*
1068 * Check link status. Wait up to 100 microseconds for link to become
1069 * valid.
1070 */
1071 ret_val = e1000_phy_has_link_generic(hw,
1072 COPPER_LINK_UP_LIMIT,
1073 10,
1074 &link);
1075 if (ret_val)
1076 goto out;
1077
1078 if (link) {
1079 DEBUGOUT("Valid link established!!!\n");
1080 e1000_config_collision_dist_generic(hw);
1081 ret_val = e1000_config_fc_after_link_up_generic(hw);
1082 } else {
1083 DEBUGOUT("Unable to establish link!!!\n");
1084 }
1085
1086 out:
1087 return ret_val;
1088 }
1089
1090 #if 0
1091 /**
1092 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1093 * @hw: pointer to the HW structure
1094 *
1095 * Calls the PHY setup function to force speed and duplex. Clears the
1096 * auto-crossover to force MDI manually. Waits for link and returns
1097 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1098 **/
1099 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1100 {
1101 struct e1000_phy_info *phy = &hw->phy;
1102 s32 ret_val;
1103 u16 phy_data;
1104 bool link;
1105
1106 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1107
1108 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1109 if (ret_val)
1110 goto out;
1111
1112 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1113
1114 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1115 if (ret_val)
1116 goto out;
1117
1118 /*
1119 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1120 * forced whenever speed and duplex are forced.
1121 */
1122 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1123 if (ret_val)
1124 goto out;
1125
1126 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1127 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1128
1129 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1130 if (ret_val)
1131 goto out;
1132
1133 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1134
1135 usec_delay(1);
1136
1137 if (phy->autoneg_wait_to_complete) {
1138 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1139
1140 ret_val = e1000_phy_has_link_generic(hw,
1141 PHY_FORCE_LIMIT,
1142 100000,
1143 &link);
1144 if (ret_val)
1145 goto out;
1146
1147 if (!link)
1148 DEBUGOUT("Link taking longer than expected.\n");
1149
1150 /* Try once more */
1151 ret_val = e1000_phy_has_link_generic(hw,
1152 PHY_FORCE_LIMIT,
1153 100000,
1154 &link);
1155 if (ret_val)
1156 goto out;
1157 }
1158
1159 out:
1160 return ret_val;
1161 }
1162
1163 /**
1164 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1165 * @hw: pointer to the HW structure
1166 *
1167 * Calls the PHY setup function to force speed and duplex. Clears the
1168 * auto-crossover to force MDI manually. Resets the PHY to commit the
1169 * changes. If time expires while waiting for link up, we reset the DSP.
1170 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1171 * successful completion, else return corresponding error code.
1172 **/
1173 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1174 {
1175 struct e1000_phy_info *phy = &hw->phy;
1176 s32 ret_val;
1177 u16 phy_data;
1178 bool link;
1179
1180 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1181
1182 /*
1183 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1184 * forced whenever speed and duplex are forced.
1185 */
1186 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1187 if (ret_val)
1188 goto out;
1189
1190 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1191 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1192 if (ret_val)
1193 goto out;
1194
1195 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1196
1197 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1198 if (ret_val)
1199 goto out;
1200
1201 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1202
1203 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1204 if (ret_val)
1205 goto out;
1206
1207 /* Reset the phy to commit changes. */
1208 ret_val = hw->phy.ops.commit(hw);
1209 if (ret_val)
1210 goto out;
1211
1212 if (phy->autoneg_wait_to_complete) {
1213 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1214
1215 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1216 100000, &link);
1217 if (ret_val)
1218 goto out;
1219
1220 if (!link) {
1221 /*
1222 * We didn't get link.
1223 * Reset the DSP and cross our fingers.
1224 */
1225 ret_val = phy->ops.write_reg(hw,
1226 M88E1000_PHY_PAGE_SELECT,
1227 0x001d);
1228 if (ret_val)
1229 goto out;
1230 ret_val = e1000_phy_reset_dsp_generic(hw);
1231 if (ret_val)
1232 goto out;
1233 }
1234
1235 /* Try once more */
1236 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1237 100000, &link);
1238 if (ret_val)
1239 goto out;
1240 }
1241
1242 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1243 if (ret_val)
1244 goto out;
1245
1246 /*
1247 * Resetting the phy means we need to re-force TX_CLK in the
1248 * Extended PHY Specific Control Register to 25MHz clock from
1249 * the reset value of 2.5MHz.
1250 */
1251 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1252 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1253 if (ret_val)
1254 goto out;
1255
1256 /*
1257 * In addition, we must re-enable CRS on Tx for both half and full
1258 * duplex.
1259 */
1260 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1261 if (ret_val)
1262 goto out;
1263
1264 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1265 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1266
1267 out:
1268 return ret_val;
1269 }
1270
1271 /**
1272 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1273 * @hw: pointer to the HW structure
1274 *
1275 * Forces the speed and duplex settings of the PHY.
1276 * This is a function pointer entry point only called by
1277 * PHY setup routines.
1278 **/
1279 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1280 {
1281 struct e1000_phy_info *phy = &hw->phy;
1282 s32 ret_val;
1283 u16 data;
1284 bool link;
1285
1286 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1287
1288 if (phy->type != e1000_phy_ife) {
1289 ret_val = e1000_phy_force_speed_duplex_igp(hw);
1290 goto out;
1291 }
1292
1293 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1294 if (ret_val)
1295 goto out;
1296
1297 e1000_phy_force_speed_duplex_setup(hw, &data);
1298
1299 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1300 if (ret_val)
1301 goto out;
1302
1303 /* Disable MDI-X support for 10/100 */
1304 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1305 if (ret_val)
1306 goto out;
1307
1308 data &= ~IFE_PMC_AUTO_MDIX;
1309 data &= ~IFE_PMC_FORCE_MDIX;
1310
1311 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1312 if (ret_val)
1313 goto out;
1314
1315 DEBUGOUT1("IFE PMC: %X\n", data);
1316
1317 usec_delay(1);
1318
1319 if (phy->autoneg_wait_to_complete) {
1320 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1321
1322 ret_val = e1000_phy_has_link_generic(hw,
1323 PHY_FORCE_LIMIT,
1324 100000,
1325 &link);
1326 if (ret_val)
1327 goto out;
1328
1329 if (!link)
1330 DEBUGOUT("Link taking longer than expected.\n");
1331
1332 /* Try once more */
1333 ret_val = e1000_phy_has_link_generic(hw,
1334 PHY_FORCE_LIMIT,
1335 100000,
1336 &link);
1337 if (ret_val)
1338 goto out;
1339 }
1340
1341 out:
1342 return ret_val;
1343 }
1344
1345 /**
1346 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1347 * @hw: pointer to the HW structure
1348 * @phy_ctrl: pointer to current value of PHY_CONTROL
1349 *
1350 * Forces speed and duplex on the PHY by doing the following: disable flow
1351 * control, force speed/duplex on the MAC, disable auto speed detection,
1352 * disable auto-negotiation, configure duplex, configure speed, configure
1353 * the collision distance, write configuration to CTRL register. The
1354 * caller must write to the PHY_CONTROL register for these settings to
1355 * take affect.
1356 **/
1357 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1358 {
1359 struct e1000_mac_info *mac = &hw->mac;
1360 u32 ctrl;
1361
1362 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1363
1364 /* Turn off flow control when forcing speed/duplex */
1365 hw->fc.current_mode = e1000_fc_none;
1366
1367 /* Force speed/duplex on the mac */
1368 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1369 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1370 ctrl &= ~E1000_CTRL_SPD_SEL;
1371
1372 /* Disable Auto Speed Detection */
1373 ctrl &= ~E1000_CTRL_ASDE;
1374
1375 /* Disable autoneg on the phy */
1376 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1377
1378 /* Forcing Full or Half Duplex? */
1379 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1380 ctrl &= ~E1000_CTRL_FD;
1381 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1382 DEBUGOUT("Half Duplex\n");
1383 } else {
1384 ctrl |= E1000_CTRL_FD;
1385 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1386 DEBUGOUT("Full Duplex\n");
1387 }
1388
1389 /* Forcing 10mb or 100mb? */
1390 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1391 ctrl |= E1000_CTRL_SPD_100;
1392 *phy_ctrl |= MII_CR_SPEED_100;
1393 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1394 DEBUGOUT("Forcing 100mb\n");
1395 } else {
1396 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1397 *phy_ctrl |= MII_CR_SPEED_10;
1398 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1399 DEBUGOUT("Forcing 10mb\n");
1400 }
1401
1402 e1000_config_collision_dist_generic(hw);
1403
1404 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1405 }
1406 #endif
1407
1408 /**
1409 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1410 * @hw: pointer to the HW structure
1411 * @active: boolean used to enable/disable lplu
1412 *
1413 * Success returns 0, Failure returns 1
1414 *
1415 * The low power link up (lplu) state is set to the power management level D3
1416 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1417 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1418 * is used during Dx states where the power conservation is most important.
1419 * During driver activity, SmartSpeed should be enabled so performance is
1420 * maintained.
1421 **/
1422 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1423 {
1424 struct e1000_phy_info *phy = &hw->phy;
1425 s32 ret_val = E1000_SUCCESS;
1426 u16 data;
1427
1428 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1429
1430 if (!(hw->phy.ops.read_reg))
1431 goto out;
1432
1433 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1434 if (ret_val)
1435 goto out;
1436
1437 if (!active) {
1438 data &= ~IGP02E1000_PM_D3_LPLU;
1439 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1440 data);
1441 if (ret_val)
1442 goto out;
1443 /*
1444 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1445 * during Dx states where the power conservation is most
1446 * important. During driver activity we should enable
1447 * SmartSpeed, so performance is maintained.
1448 */
1449 if (phy->smart_speed == e1000_smart_speed_on) {
1450 ret_val = phy->ops.read_reg(hw,
1451 IGP01E1000_PHY_PORT_CONFIG,
1452 &data);
1453 if (ret_val)
1454 goto out;
1455
1456 data |= IGP01E1000_PSCFR_SMART_SPEED;
1457 ret_val = phy->ops.write_reg(hw,
1458 IGP01E1000_PHY_PORT_CONFIG,
1459 data);
1460 if (ret_val)
1461 goto out;
1462 } else if (phy->smart_speed == e1000_smart_speed_off) {
1463 ret_val = phy->ops.read_reg(hw,
1464 IGP01E1000_PHY_PORT_CONFIG,
1465 &data);
1466 if (ret_val)
1467 goto out;
1468
1469 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1470 ret_val = phy->ops.write_reg(hw,
1471 IGP01E1000_PHY_PORT_CONFIG,
1472 data);
1473 if (ret_val)
1474 goto out;
1475 }
1476 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1477 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1478 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1479 data |= IGP02E1000_PM_D3_LPLU;
1480 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1481 data);
1482 if (ret_val)
1483 goto out;
1484
1485 /* When LPLU is enabled, we should disable SmartSpeed */
1486 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1487 &data);
1488 if (ret_val)
1489 goto out;
1490
1491 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1492 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1493 data);
1494 }
1495
1496 out:
1497 return ret_val;
1498 }
1499
1500 /**
1501 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
1502 * @hw: pointer to the HW structure
1503 *
1504 * Success returns 0, Failure returns 1
1505 *
1506 * A downshift is detected by querying the PHY link health.
1507 **/
1508 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
1509 {
1510 struct e1000_phy_info *phy = &hw->phy;
1511 s32 ret_val;
1512 u16 phy_data, offset, mask;
1513
1514 DEBUGFUNC("e1000_check_downshift_generic");
1515
1516 switch (phy->type) {
1517 case e1000_phy_m88:
1518 case e1000_phy_gg82563:
1519 offset = M88E1000_PHY_SPEC_STATUS;
1520 mask = M88E1000_PSSR_DOWNSHIFT;
1521 break;
1522 case e1000_phy_igp_2:
1523 case e1000_phy_igp:
1524 case e1000_phy_igp_3:
1525 offset = IGP01E1000_PHY_LINK_HEALTH;
1526 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1527 break;
1528 default:
1529 /* speed downshift not supported */
1530 phy->speed_downgraded = false;
1531 ret_val = E1000_SUCCESS;
1532 goto out;
1533 }
1534
1535 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1536
1537 if (!ret_val)
1538 phy->speed_downgraded = (phy_data & mask) ? true : false;
1539
1540 out:
1541 return ret_val;
1542 }
1543
1544 /**
1545 * e1000_check_polarity_m88 - Checks the polarity.
1546 * @hw: pointer to the HW structure
1547 *
1548 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1549 *
1550 * Polarity is determined based on the PHY specific status register.
1551 **/
1552 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1553 {
1554 struct e1000_phy_info *phy = &hw->phy;
1555 s32 ret_val;
1556 u16 data;
1557
1558 DEBUGFUNC("e1000_check_polarity_m88");
1559
1560 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1561
1562 if (!ret_val)
1563 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1564 ? e1000_rev_polarity_reversed
1565 : e1000_rev_polarity_normal;
1566
1567 return ret_val;
1568 }
1569
1570 /**
1571 * e1000_check_polarity_igp - Checks the polarity.
1572 * @hw: pointer to the HW structure
1573 *
1574 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1575 *
1576 * Polarity is determined based on the PHY port status register, and the
1577 * current speed (since there is no polarity at 100Mbps).
1578 **/
1579 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1580 {
1581 struct e1000_phy_info *phy = &hw->phy;
1582 s32 ret_val;
1583 u16 data, offset, mask;
1584
1585 DEBUGFUNC("e1000_check_polarity_igp");
1586
1587 /*
1588 * Polarity is determined based on the speed of
1589 * our connection.
1590 */
1591 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1592 if (ret_val)
1593 goto out;
1594
1595 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1596 IGP01E1000_PSSR_SPEED_1000MBPS) {
1597 offset = IGP01E1000_PHY_PCS_INIT_REG;
1598 mask = IGP01E1000_PHY_POLARITY_MASK;
1599 } else {
1600 /*
1601 * This really only applies to 10Mbps since
1602 * there is no polarity for 100Mbps (always 0).
1603 */
1604 offset = IGP01E1000_PHY_PORT_STATUS;
1605 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1606 }
1607
1608 ret_val = phy->ops.read_reg(hw, offset, &data);
1609
1610 if (!ret_val)
1611 phy->cable_polarity = (data & mask)
1612 ? e1000_rev_polarity_reversed
1613 : e1000_rev_polarity_normal;
1614
1615 out:
1616 return ret_val;
1617 }
1618
1619 /**
1620 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1621 * @hw: pointer to the HW structure
1622 *
1623 * Polarity is determined on the polarity reversal feature being enabled.
1624 **/
1625 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1626 {
1627 struct e1000_phy_info *phy = &hw->phy;
1628 s32 ret_val;
1629 u16 phy_data, offset, mask;
1630
1631 DEBUGFUNC("e1000_check_polarity_ife");
1632
1633 /*
1634 * Polarity is determined based on the reversal feature being enabled.
1635 */
1636 if (phy->polarity_correction) {
1637 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1638 mask = IFE_PESC_POLARITY_REVERSED;
1639 } else {
1640 offset = IFE_PHY_SPECIAL_CONTROL;
1641 mask = IFE_PSC_FORCE_POLARITY;
1642 }
1643
1644 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1645
1646 if (!ret_val)
1647 phy->cable_polarity = (phy_data & mask)
1648 ? e1000_rev_polarity_reversed
1649 : e1000_rev_polarity_normal;
1650
1651 return ret_val;
1652 }
1653
1654 /**
1655 * e1000_wait_autoneg_generic - Wait for auto-neg completion
1656 * @hw: pointer to the HW structure
1657 *
1658 * Waits for auto-negotiation to complete or for the auto-negotiation time
1659 * limit to expire, which ever happens first.
1660 **/
1661 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
1662 {
1663 s32 ret_val = E1000_SUCCESS;
1664 u16 i, phy_status;
1665
1666 DEBUGFUNC("e1000_wait_autoneg_generic");
1667
1668 if (!(hw->phy.ops.read_reg))
1669 return E1000_SUCCESS;
1670
1671 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1672 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1673 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1674 if (ret_val)
1675 break;
1676 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1677 if (ret_val)
1678 break;
1679 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1680 break;
1681 msec_delay(100);
1682 }
1683
1684 /*
1685 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1686 * has completed.
1687 */
1688 return ret_val;
1689 }
1690
1691 /**
1692 * e1000_phy_has_link_generic - Polls PHY for link
1693 * @hw: pointer to the HW structure
1694 * @iterations: number of times to poll for link
1695 * @usec_interval: delay between polling attempts
1696 * @success: pointer to whether polling was successful or not
1697 *
1698 * Polls the PHY status register for link, 'iterations' number of times.
1699 **/
1700 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1701 u32 usec_interval, bool *success)
1702 {
1703 s32 ret_val = E1000_SUCCESS;
1704 u16 i, phy_status;
1705
1706 DEBUGFUNC("e1000_phy_has_link_generic");
1707
1708 if (!(hw->phy.ops.read_reg))
1709 return E1000_SUCCESS;
1710
1711 for (i = 0; i < iterations; i++) {
1712 /*
1713 * Some PHYs require the PHY_STATUS register to be read
1714 * twice due to the link bit being sticky. No harm doing
1715 * it across the board.
1716 */
1717 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1718 if (ret_val) {
1719 /*
1720 * If the first read fails, another entity may have
1721 * ownership of the resources, wait and try again to
1722 * see if they have relinquished the resources yet.
1723 */
1724 usec_delay(usec_interval);
1725 }
1726 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1727 if (ret_val)
1728 break;
1729 if (phy_status & MII_SR_LINK_STATUS)
1730 break;
1731 if (usec_interval >= 1000)
1732 msec_delay_irq(usec_interval/1000);
1733 else
1734 usec_delay(usec_interval);
1735 }
1736
1737 *success = (i < iterations) ? true : false;
1738
1739 return ret_val;
1740 }
1741
1742 #if 0
1743 /**
1744 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
1745 * @hw: pointer to the HW structure
1746 *
1747 * Reads the PHY specific status register to retrieve the cable length
1748 * information. The cable length is determined by averaging the minimum and
1749 * maximum values to get the "average" cable length. The m88 PHY has four
1750 * possible cable length values, which are:
1751 * Register Value Cable Length
1752 * 0 < 50 meters
1753 * 1 50 - 80 meters
1754 * 2 80 - 110 meters
1755 * 3 110 - 140 meters
1756 * 4 > 140 meters
1757 **/
1758 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
1759 {
1760 struct e1000_phy_info *phy = &hw->phy;
1761 s32 ret_val;
1762 u16 phy_data, index;
1763
1764 DEBUGFUNC("e1000_get_cable_length_m88");
1765
1766 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1767 if (ret_val)
1768 goto out;
1769
1770 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1771 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1772 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE + 1) {
1773 ret_val = E1000_ERR_PHY;
1774 goto out;
1775 }
1776
1777 phy->min_cable_length = e1000_m88_cable_length_table[index];
1778 phy->max_cable_length = e1000_m88_cable_length_table[index+1];
1779
1780 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1781
1782 out:
1783 return ret_val;
1784 }
1785
1786 /**
1787 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1788 * @hw: pointer to the HW structure
1789 *
1790 * The automatic gain control (agc) normalizes the amplitude of the
1791 * received signal, adjusting for the attenuation produced by the
1792 * cable. By reading the AGC registers, which represent the
1793 * combination of coarse and fine gain value, the value can be put
1794 * into a lookup table to obtain the approximate cable length
1795 * for each channel.
1796 **/
1797 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
1798 {
1799 struct e1000_phy_info *phy = &hw->phy;
1800 s32 ret_val = E1000_SUCCESS;
1801 u16 phy_data, i, agc_value = 0;
1802 u16 cur_agc_index, max_agc_index = 0;
1803 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1804 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1805 {IGP02E1000_PHY_AGC_A,
1806 IGP02E1000_PHY_AGC_B,
1807 IGP02E1000_PHY_AGC_C,
1808 IGP02E1000_PHY_AGC_D};
1809
1810 DEBUGFUNC("e1000_get_cable_length_igp_2");
1811
1812 /* Read the AGC registers for all channels */
1813 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1814 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1815 if (ret_val)
1816 goto out;
1817
1818 /*
1819 * Getting bits 15:9, which represent the combination of
1820 * coarse and fine gain values. The result is a number
1821 * that can be put into the lookup table to obtain the
1822 * approximate cable length.
1823 */
1824 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1825 IGP02E1000_AGC_LENGTH_MASK;
1826
1827 /* Array index bound check. */
1828 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1829 (cur_agc_index == 0)) {
1830 ret_val = -E1000_ERR_PHY;
1831 goto out;
1832 }
1833
1834 /* Remove min & max AGC values from calculation. */
1835 if (e1000_igp_2_cable_length_table[min_agc_index] >
1836 e1000_igp_2_cable_length_table[cur_agc_index])
1837 min_agc_index = cur_agc_index;
1838 if (e1000_igp_2_cable_length_table[max_agc_index] <
1839 e1000_igp_2_cable_length_table[cur_agc_index])
1840 max_agc_index = cur_agc_index;
1841
1842 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1843 }
1844
1845 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1846 e1000_igp_2_cable_length_table[max_agc_index]);
1847 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1848
1849 /* Calculate cable length with the error range of +/- 10 meters. */
1850 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1851 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1852 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1853
1854 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1855
1856 out:
1857 return ret_val;
1858 }
1859 #endif
1860
1861 /**
1862 * e1000_get_phy_info_m88 - Retrieve PHY information
1863 * @hw: pointer to the HW structure
1864 *
1865 * Valid for only copper links. Read the PHY status register (sticky read)
1866 * to verify that link is up. Read the PHY special control register to
1867 * determine the polarity and 10base-T extended distance. Read the PHY
1868 * special status register to determine MDI/MDIx and current speed. If
1869 * speed is 1000, then determine cable length, local and remote receiver.
1870 **/
1871 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
1872 {
1873 struct e1000_phy_info *phy = &hw->phy;
1874 s32 ret_val;
1875 u16 phy_data;
1876 bool link;
1877
1878 DEBUGFUNC("e1000_get_phy_info_m88");
1879
1880 if (hw->phy.media_type != e1000_media_type_copper) {
1881 DEBUGOUT("Phy info is only valid for copper media\n");
1882 ret_val = -E1000_ERR_CONFIG;
1883 goto out;
1884 }
1885
1886 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1887 if (ret_val)
1888 goto out;
1889
1890 if (!link) {
1891 DEBUGOUT("Phy info is only valid if link is up\n");
1892 ret_val = -E1000_ERR_CONFIG;
1893 goto out;
1894 }
1895
1896 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1897 if (ret_val)
1898 goto out;
1899
1900 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1901 ? true : false;
1902
1903 ret_val = e1000_check_polarity_m88(hw);
1904 if (ret_val)
1905 goto out;
1906
1907 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1908 if (ret_val)
1909 goto out;
1910
1911 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1912
1913 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1914 #if 0
1915 ret_val = hw->phy.ops.get_cable_length(hw);
1916 #endif
1917 ret_val = -E1000_ERR_CONFIG;
1918 if (ret_val)
1919 goto out;
1920
1921 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1922 if (ret_val)
1923 goto out;
1924
1925 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1926 ? e1000_1000t_rx_status_ok
1927 : e1000_1000t_rx_status_not_ok;
1928
1929 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1930 ? e1000_1000t_rx_status_ok
1931 : e1000_1000t_rx_status_not_ok;
1932 } else {
1933 /* Set values to "undefined" */
1934 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1935 phy->local_rx = e1000_1000t_rx_status_undefined;
1936 phy->remote_rx = e1000_1000t_rx_status_undefined;
1937 }
1938
1939 out:
1940 return ret_val;
1941 }
1942
1943 /**
1944 * e1000_get_phy_info_igp - Retrieve igp PHY information
1945 * @hw: pointer to the HW structure
1946 *
1947 * Read PHY status to determine if link is up. If link is up, then
1948 * set/determine 10base-T extended distance and polarity correction. Read
1949 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1950 * determine on the cable length, local and remote receiver.
1951 **/
1952 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
1953 {
1954 struct e1000_phy_info *phy = &hw->phy;
1955 s32 ret_val;
1956 u16 data;
1957 bool link;
1958
1959 DEBUGFUNC("e1000_get_phy_info_igp");
1960
1961 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1962 if (ret_val)
1963 goto out;
1964
1965 if (!link) {
1966 DEBUGOUT("Phy info is only valid if link is up\n");
1967 ret_val = -E1000_ERR_CONFIG;
1968 goto out;
1969 }
1970
1971 phy->polarity_correction = true;
1972
1973 ret_val = e1000_check_polarity_igp(hw);
1974 if (ret_val)
1975 goto out;
1976
1977 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1978 if (ret_val)
1979 goto out;
1980
1981 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
1982
1983 #if 0
1984 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1985 IGP01E1000_PSSR_SPEED_1000MBPS) {
1986 ret_val = hw->phy.ops.get_cable_length(hw);
1987 if (ret_val)
1988 goto out;
1989
1990 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
1991 if (ret_val)
1992 goto out;
1993
1994 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1995 ? e1000_1000t_rx_status_ok
1996 : e1000_1000t_rx_status_not_ok;
1997
1998 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1999 ? e1000_1000t_rx_status_ok
2000 : e1000_1000t_rx_status_not_ok;
2001 } else {
2002 #endif
2003 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2004 phy->local_rx = e1000_1000t_rx_status_undefined;
2005 phy->remote_rx = e1000_1000t_rx_status_undefined;
2006 #if 0
2007 }
2008 #endif
2009
2010 out:
2011 return ret_val;
2012 }
2013
2014 /**
2015 * e1000_phy_sw_reset_generic - PHY software reset
2016 * @hw: pointer to the HW structure
2017 *
2018 * Does a software reset of the PHY by reading the PHY control register and
2019 * setting/write the control register reset bit to the PHY.
2020 **/
2021 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2022 {
2023 s32 ret_val = E1000_SUCCESS;
2024 u16 phy_ctrl;
2025
2026 DEBUGFUNC("e1000_phy_sw_reset_generic");
2027
2028 if (!(hw->phy.ops.read_reg))
2029 goto out;
2030
2031 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2032 if (ret_val)
2033 goto out;
2034
2035 phy_ctrl |= MII_CR_RESET;
2036 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2037 if (ret_val)
2038 goto out;
2039
2040 usec_delay(1);
2041
2042 out:
2043 return ret_val;
2044 }
2045
2046 /**
2047 * e1000_phy_hw_reset_generic - PHY hardware reset
2048 * @hw: pointer to the HW structure
2049 *
2050 * Verify the reset block is not blocking us from resetting. Acquire
2051 * semaphore (if necessary) and read/set/write the device control reset
2052 * bit in the PHY. Wait the appropriate delay time for the device to
2053 * reset and release the semaphore (if necessary).
2054 **/
2055 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2056 {
2057 struct e1000_phy_info *phy = &hw->phy;
2058 s32 ret_val = E1000_SUCCESS;
2059 u32 ctrl;
2060
2061 DEBUGFUNC("e1000_phy_hw_reset_generic");
2062
2063 ret_val = phy->ops.check_reset_block(hw);
2064 if (ret_val) {
2065 ret_val = E1000_SUCCESS;
2066 goto out;
2067 }
2068
2069 ret_val = phy->ops.acquire(hw);
2070 if (ret_val)
2071 goto out;
2072
2073 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2074 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2075 E1000_WRITE_FLUSH(hw);
2076
2077 usec_delay(phy->reset_delay_us);
2078
2079 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2080 E1000_WRITE_FLUSH(hw);
2081
2082 usec_delay(150);
2083
2084 phy->ops.release(hw);
2085
2086 ret_val = phy->ops.get_cfg_done(hw);
2087
2088 out:
2089 return ret_val;
2090 }
2091
2092 /**
2093 * e1000_get_cfg_done_generic - Generic configuration done
2094 * @hw: pointer to the HW structure
2095 *
2096 * Generic function to wait 10 milli-seconds for configuration to complete
2097 * and return success.
2098 **/
2099 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw __unused)
2100 {
2101 DEBUGFUNC("e1000_get_cfg_done_generic");
2102
2103 msec_delay_irq(10);
2104
2105 return E1000_SUCCESS;
2106 }
2107
2108 /**
2109 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2110 * @hw: pointer to the HW structure
2111 *
2112 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2113 **/
2114 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2115 {
2116 DEBUGOUT("Running IGP 3 PHY init script\n");
2117
2118 /* PHY init IGP 3 */
2119 /* Enable rise/fall, 10-mode work in class-A */
2120 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2121 /* Remove all caps from Replica path filter */
2122 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2123 /* Bias trimming for ADC, AFE and Driver (Default) */
2124 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2125 /* Increase Hybrid poly bias */
2126 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2127 /* Add 4% to Tx amplitude in Gig mode */
2128 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2129 /* Disable trimming (TTT) */
2130 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2131 /* Poly DC correction to 94.6% + 2% for all channels */
2132 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2133 /* ABS DC correction to 95.9% */
2134 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2135 /* BG temp curve trim */
2136 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2137 /* Increasing ADC OPAMP stage 1 currents to max */
2138 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2139 /* Force 1000 ( required for enabling PHY regs configuration) */
2140 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2141 /* Set upd_freq to 6 */
2142 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2143 /* Disable NPDFE */
2144 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2145 /* Disable adaptive fixed FFE (Default) */
2146 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2147 /* Enable FFE hysteresis */
2148 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2149 /* Fixed FFE for short cable lengths */
2150 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2151 /* Fixed FFE for medium cable lengths */
2152 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2153 /* Fixed FFE for long cable lengths */
2154 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2155 /* Enable Adaptive Clip Threshold */
2156 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2157 /* AHT reset limit to 1 */
2158 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2159 /* Set AHT master delay to 127 msec */
2160 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2161 /* Set scan bits for AHT */
2162 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2163 /* Set AHT Preset bits */
2164 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2165 /* Change integ_factor of channel A to 3 */
2166 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2167 /* Change prop_factor of channels BCD to 8 */
2168 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2169 /* Change cg_icount + enable integbp for channels BCD */
2170 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2171 /*
2172 * Change cg_icount + enable integbp + change prop_factor_master
2173 * to 8 for channel A
2174 */
2175 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2176 /* Disable AHT in Slave mode on channel A */
2177 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2178 /*
2179 * Enable LPLU and disable AN to 1000 in non-D0a states,
2180 * Enable SPD+B2B
2181 */
2182 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2183 /* Enable restart AN on an1000_dis change */
2184 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2185 /* Enable wh_fifo read clock in 10/100 modes */
2186 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2187 /* Restart AN, Speed selection is 1000 */
2188 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2189
2190 return E1000_SUCCESS;
2191 }
2192
2193 /**
2194 * e1000_get_phy_type_from_id - Get PHY type from id
2195 * @phy_id: phy_id read from the phy
2196 *
2197 * Returns the phy type from the id.
2198 **/
2199 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2200 {
2201 enum e1000_phy_type phy_type = e1000_phy_unknown;
2202
2203 switch (phy_id) {
2204 case M88E1000_I_PHY_ID:
2205 case M88E1000_E_PHY_ID:
2206 case M88E1111_I_PHY_ID:
2207 case M88E1011_I_PHY_ID:
2208 phy_type = e1000_phy_m88;
2209 break;
2210 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2211 phy_type = e1000_phy_igp_2;
2212 break;
2213 case GG82563_E_PHY_ID:
2214 phy_type = e1000_phy_gg82563;
2215 break;
2216 case IGP03E1000_E_PHY_ID:
2217 phy_type = e1000_phy_igp_3;
2218 break;
2219 case IFE_E_PHY_ID:
2220 case IFE_PLUS_E_PHY_ID:
2221 case IFE_C_E_PHY_ID:
2222 phy_type = e1000_phy_ife;
2223 break;
2224 default:
2225 phy_type = e1000_phy_unknown;
2226 break;
2227 }
2228 return phy_type;
2229 }
2230
2231 /**
2232 * e1000_determine_phy_address - Determines PHY address.
2233 * @hw: pointer to the HW structure
2234 *
2235 * This uses a trial and error method to loop through possible PHY
2236 * addresses. It tests each by reading the PHY ID registers and
2237 * checking for a match.
2238 **/
2239 s32 e1000_determine_phy_address(struct e1000_hw *hw)
2240 {
2241 s32 ret_val = -E1000_ERR_PHY_TYPE;
2242 u32 phy_addr = 0;
2243 u32 i;
2244 enum e1000_phy_type phy_type = e1000_phy_unknown;
2245
2246 hw->phy.id = phy_type;
2247
2248 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2249 hw->phy.addr = phy_addr;
2250 i = 0;
2251
2252 do {
2253 e1000_get_phy_id(hw);
2254 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
2255
2256 /*
2257 * If phy_type is valid, break - we found our
2258 * PHY address
2259 */
2260 if (phy_type != e1000_phy_unknown) {
2261 ret_val = E1000_SUCCESS;
2262 goto out;
2263 }
2264 msec_delay(1);
2265 i++;
2266 } while (i < 10);
2267 }
2268
2269 out:
2270 return ret_val;
2271 }
2272
2273 /**
2274 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2275 * @hw: pointer to the HW structure
2276 *
2277 * In the case of a PHY power down to save power, or to turn off link during a
2278 * driver unload, or wake on lan is not enabled, restore the link to previous
2279 * settings.
2280 **/
2281 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2282 {
2283 u16 mii_reg = 0;
2284
2285 /* The PHY will retain its settings across a power down/up cycle */
2286 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2287 mii_reg &= ~MII_CR_POWER_DOWN;
2288 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2289 }
2290
2291 /**
2292 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2293 * @hw: pointer to the HW structure
2294 *
2295 * In the case of a PHY power down to save power, or to turn off link during a
2296 * driver unload, or wake on lan is not enabled, restore the link to previous
2297 * settings.
2298 **/
2299 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2300 {
2301 u16 mii_reg = 0;
2302
2303 /* The PHY will retain its settings across a power down/up cycle */
2304 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2305 mii_reg |= MII_CR_POWER_DOWN;
2306 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2307 msec_delay(1);
2308 }
gPXE - free pxe roms