src/drivers/net/phantom/phantom.h

   1 #ifndef _PHANTOM_H
   2 #define _PHANTOM_H
   3
   4 /*
   5  * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
   6  * Copyright (C) 2008 NetXen, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of the
  11  * License, or any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 FILE_LICENCE ( GPL2_OR_LATER );
  24
  25 /**
  26  * @file
  27  *
  28  * NetXen Phantom NICs
  29  *
  30  */
  31
  32 #include <stdint.h>
  33
  34 /* Drag in hardware definitions */
  35 #include "nx_bitops.h"
  36 #include "phantom_hw.h"
  37 struct phantom_rds { NX_PSEUDO_BIT_STRUCT ( struct phantom_rds_pb ) };
  38 struct phantom_sds { NX_PSEUDO_BIT_STRUCT ( struct phantom_sds_pb ) };
  39 union phantom_cds { NX_PSEUDO_BIT_STRUCT ( union phantom_cds_pb ) };
  40
  41 /* Drag in firmware interface definitions */
  42 typedef uint8_t U8;
  43 typedef uint16_t U16;
  44 typedef uint32_t U32;
  45 typedef uint64_t U64;
  46 typedef uint32_t nx_rcode_t;
  47 #define NXHAL_VERSION 1
  48 #include "nxhal_nic_interface.h"
  49
  50 /** DMA buffer alignment */
  51 #define UNM_DMA_BUFFER_ALIGN 16
  52
  53 /** Mark structure as DMA-aligned */
  54 #define __unm_dma_aligned __attribute__ (( aligned ( UNM_DMA_BUFFER_ALIGN ) ))
  55
  56 /******************************************************************************
  57  *
  58  * Register definitions
  59  *
  60  */
  61
  62 #define UNM_128M_CRB_WINDOW             0x6110210UL
  63 #define UNM_32M_CRB_WINDOW              0x0110210UL
  64 #define UNM_2M_CRB_WINDOW               0x0130060UL
  65
  66 /**
  67  * Phantom register blocks
  68  *
  69  * The upper address bits vary between cards.  We define an abstract
  70  * address space in which the upper 8 bits of the 32-bit register
  71  * address encode the register block.  This gets translated to a bus
  72  * address by the phantom_crb_access_xxx() methods.
  73  */
  74 enum unm_reg_blocks {
  75         UNM_CRB_BLK_PCIE        = 0x01,
  76         UNM_CRB_BLK_CAM         = 0x22,
  77         UNM_CRB_BLK_ROMUSB      = 0x33,
  78         UNM_CRB_BLK_TEST        = 0x02,
  79         UNM_CRB_BLK_PEG_0       = 0x11,
  80         UNM_CRB_BLK_PEG_1       = 0x12,
  81         UNM_CRB_BLK_PEG_2       = 0x13,
  82         UNM_CRB_BLK_PEG_3       = 0x14,
  83         UNM_CRB_BLK_PEG_4       = 0x0f,
  84 };
  85 #define UNM_CRB_BASE(blk)               ( (blk) << 20 )
  86 #define UNM_CRB_BLK(reg)                ( (reg) >> 20 )
  87 #define UNM_CRB_OFFSET(reg)             ( (reg) & 0x000fffff )
  88
  89 #define UNM_CRB_PCIE                    UNM_CRB_BASE ( UNM_CRB_BLK_PCIE )
  90 #define UNM_PCIE_SEM2_LOCK              ( UNM_CRB_PCIE + 0x1c010 )
  91 #define UNM_PCIE_SEM2_UNLOCK            ( UNM_CRB_PCIE + 0x1c014 )
  92 #define UNM_PCIE_IRQ_VECTOR             ( UNM_CRB_PCIE + 0x10100 )
  93 #define UNM_PCIE_IRQ_VECTOR_BIT(n)              ( 1 << ( (n) + 7 ) )
  94 #define UNM_PCIE_IRQ_STATE              ( UNM_CRB_PCIE + 0x1206c )
  95 #define UNM_PCIE_IRQ_STATE_TRIGGERED(state)     (( (state) & 0x300 ) == 0x200 )
  96 #define UNM_PCIE_IRQ_MASK_F0            ( UNM_CRB_PCIE + 0x10128 )
  97 #define UNM_PCIE_IRQ_MASK_F1            ( UNM_CRB_PCIE + 0x10170 )
  98 #define UNM_PCIE_IRQ_MASK_F2            ( UNM_CRB_PCIE + 0x10174 )
  99 #define UNM_PCIE_IRQ_MASK_F3            ( UNM_CRB_PCIE + 0x10178 )
 100 #define UNM_PCIE_IRQ_MASK_F4            ( UNM_CRB_PCIE + 0x10370 )
 101 #define UNM_PCIE_IRQ_MASK_F5            ( UNM_CRB_PCIE + 0x10374 )
 102 #define UNM_PCIE_IRQ_MASK_F6            ( UNM_CRB_PCIE + 0x10378 )
 103 #define UNM_PCIE_IRQ_MASK_F7            ( UNM_CRB_PCIE + 0x1037c )
 104 #define UNM_PCIE_IRQ_MASK_MAGIC                 0x0000fbffUL
 105 #define UNM_PCIE_IRQ_STATUS_F0          ( UNM_CRB_PCIE + 0x10118 )
 106 #define UNM_PCIE_IRQ_STATUS_F1          ( UNM_CRB_PCIE + 0x10160 )
 107 #define UNM_PCIE_IRQ_STATUS_F2          ( UNM_CRB_PCIE + 0x10164 )
 108 #define UNM_PCIE_IRQ_STATUS_F3          ( UNM_CRB_PCIE + 0x10168 )
 109 #define UNM_PCIE_IRQ_STATUS_F4          ( UNM_CRB_PCIE + 0x10360 )
 110 #define UNM_PCIE_IRQ_STATUS_F5          ( UNM_CRB_PCIE + 0x10364 )
 111 #define UNM_PCIE_IRQ_STATUS_F6          ( UNM_CRB_PCIE + 0x10368 )
 112 #define UNM_PCIE_IRQ_STATUS_F7          ( UNM_CRB_PCIE + 0x1036c )
 113 #define UNM_PCIE_IRQ_STATUS_MAGIC               0xffffffffUL
 114
 115 #define UNM_CRB_CAM                     UNM_CRB_BASE ( UNM_CRB_BLK_CAM )
 116
 117 #define UNM_CAM_RAM                     ( UNM_CRB_CAM + 0x02000 )
 118 #define UNM_CAM_RAM_PORT_MODE           ( UNM_CAM_RAM + 0x00024 )
 119 #define UNM_CAM_RAM_PORT_MODE_AUTO_NEG          4
 120 #define UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G       5
 121 #define UNM_CAM_RAM_DMESG_HEAD(n)       ( UNM_CAM_RAM + 0x00030 + (n) * 0x10 )
 122 #define UNM_CAM_RAM_DMESG_LEN(n)        ( UNM_CAM_RAM + 0x00034 + (n) * 0x10 )
 123 #define UNM_CAM_RAM_DMESG_TAIL(n)       ( UNM_CAM_RAM + 0x00038 + (n) * 0x10 )
 124 #define UNM_CAM_RAM_DMESG_SIG(n)        ( UNM_CAM_RAM + 0x0003c + (n) * 0x10 )
 125 #define UNM_CAM_RAM_DMESG_SIG_MAGIC             0xcafebabeUL
 126 #define UNM_CAM_RAM_NUM_DMESG_BUFFERS           5
 127 #define UNM_CAM_RAM_CLP_COMMAND         ( UNM_CAM_RAM + 0x000c0 )
 128 #define UNM_CAM_RAM_CLP_COMMAND_LAST            0x00000080UL
 129 #define UNM_CAM_RAM_CLP_DATA_LO         ( UNM_CAM_RAM + 0x000c4 )
 130 #define UNM_CAM_RAM_CLP_DATA_HI         ( UNM_CAM_RAM + 0x000c8 )
 131 #define UNM_CAM_RAM_CLP_STATUS          ( UNM_CAM_RAM + 0x000cc )
 132 #define UNM_CAM_RAM_CLP_STATUS_START            0x00000001UL
 133 #define UNM_CAM_RAM_CLP_STATUS_DONE             0x00000002UL
 134 #define UNM_CAM_RAM_CLP_STATUS_ERROR            0x0000ff00UL
 135 #define UNM_CAM_RAM_CLP_STATUS_UNINITIALISED    0xffffffffUL
 136 #define UNM_CAM_RAM_BOOT_ENABLE         ( UNM_CAM_RAM + 0x000fc )
 137 #define UNM_CAM_RAM_WOL_PORT_MODE       ( UNM_CAM_RAM + 0x00198 )
 138 #define UNM_CAM_RAM_MAC_ADDRS           ( UNM_CAM_RAM + 0x001c0 )
 139 #define UNM_CAM_RAM_COLD_BOOT           ( UNM_CAM_RAM + 0x001fc )
 140 #define UNM_CAM_RAM_COLD_BOOT_MAGIC             0x55555555UL
 141
 142 #define UNM_NIC_REG                     ( UNM_CRB_CAM + 0x02200 )
 143 #define UNM_NIC_REG_NX_CDRP             ( UNM_NIC_REG + 0x00018 )
 144 #define UNM_NIC_REG_NX_ARG1             ( UNM_NIC_REG + 0x0001c )
 145 #define UNM_NIC_REG_NX_ARG2             ( UNM_NIC_REG + 0x00020 )
 146 #define UNM_NIC_REG_NX_ARG3             ( UNM_NIC_REG + 0x00024 )
 147 #define UNM_NIC_REG_NX_SIGN             ( UNM_NIC_REG + 0x00028 )
 148 #define UNM_NIC_REG_DUMMY_BUF_ADDR_HI   ( UNM_NIC_REG + 0x0003c )
 149 #define UNM_NIC_REG_DUMMY_BUF_ADDR_LO   ( UNM_NIC_REG + 0x00040 )
 150 #define UNM_NIC_REG_CMDPEG_STATE        ( UNM_NIC_REG + 0x00050 )
 151 #define UNM_NIC_REG_CMDPEG_STATE_INITIALIZED    0xff01
 152 #define UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK 0xf00f
 153 #define UNM_NIC_REG_DUMMY_BUF           ( UNM_NIC_REG + 0x000fc )
 154 #define UNM_NIC_REG_DUMMY_BUF_INIT              0
 155 #define UNM_NIC_REG_XG_STATE_P3         ( UNM_NIC_REG + 0x00098 )
 156 #define UNM_NIC_REG_XG_STATE_P3_LINK( port, state_p3 ) \
 157         ( ( (state_p3) >> ( (port) * 4 ) ) & 0x0f )
 158 #define UNM_NIC_REG_XG_STATE_P3_LINK_UP         0x01
 159 #define UNM_NIC_REG_XG_STATE_P3_LINK_DOWN       0x02
 160 #define UNM_NIC_REG_RCVPEG_STATE        ( UNM_NIC_REG + 0x0013c )
 161 #define UNM_NIC_REG_RCVPEG_STATE_INITIALIZED    0xff01
 162
 163 #define UNM_CRB_ROMUSB                  UNM_CRB_BASE ( UNM_CRB_BLK_ROMUSB )
 164
 165 #define UNM_ROMUSB_GLB                  ( UNM_CRB_ROMUSB + 0x00000 )
 166 #define UNM_ROMUSB_GLB_STATUS           ( UNM_ROMUSB_GLB + 0x00004 )
 167 #define UNM_ROMUSB_GLB_STATUS_ROM_DONE          ( 1 << 1 )
 168 #define UNM_ROMUSB_GLB_SW_RESET         ( UNM_ROMUSB_GLB + 0x00008 )
 169 #define UNM_ROMUSB_GLB_SW_RESET_MAGIC           0x0080000fUL
 170 #define UNM_ROMUSB_GLB_PEGTUNE_DONE     ( UNM_ROMUSB_GLB + 0x0005c )
 171 #define UNM_ROMUSB_GLB_PEGTUNE_DONE_MAGIC       0x31
 172
 173 #define UNM_ROMUSB_ROM                  ( UNM_CRB_ROMUSB + 0x10000 )
 174 #define UNM_ROMUSB_ROM_INSTR_OPCODE     ( UNM_ROMUSB_ROM + 0x00004 )
 175 #define UNM_ROMUSB_ROM_ADDRESS          ( UNM_ROMUSB_ROM + 0x00008 )
 176 #define UNM_ROMUSB_ROM_WDATA            ( UNM_ROMUSB_ROM + 0x0000c )
 177 #define UNM_ROMUSB_ROM_ABYTE_CNT        ( UNM_ROMUSB_ROM + 0x00010 )
 178 #define UNM_ROMUSB_ROM_DUMMY_BYTE_CNT   ( UNM_ROMUSB_ROM + 0x00014 )
 179 #define UNM_ROMUSB_ROM_RDATA            ( UNM_ROMUSB_ROM + 0x00018 )
 180
 181 #define UNM_CRB_TEST                    UNM_CRB_BASE ( UNM_CRB_BLK_TEST )
 182
 183 #define UNM_TEST_CONTROL                ( UNM_CRB_TEST + 0x00090 )
 184 #define UNM_TEST_CONTROL_START                  0x01
 185 #define UNM_TEST_CONTROL_ENABLE                 0x02
 186 #define UNM_TEST_CONTROL_BUSY                   0x08
 187 #define UNM_TEST_ADDR_LO                ( UNM_CRB_TEST + 0x00094 )
 188 #define UNM_TEST_ADDR_HI                ( UNM_CRB_TEST + 0x00098 )
 189 #define UNM_TEST_RDDATA_LO              ( UNM_CRB_TEST + 0x000a8 )
 190 #define UNM_TEST_RDDATA_HI              ( UNM_CRB_TEST + 0x000ac )
 191
 192 #define UNM_CRB_PEG_0                   UNM_CRB_BASE ( UNM_CRB_BLK_PEG_0 )
 193 #define UNM_PEG_0_HALT_STATUS           ( UNM_CRB_PEG_0 + 0x00030 )
 194 #define UNM_PEG_0_HALT                  ( UNM_CRB_PEG_0 + 0x0003c )
 195
 196 #define UNM_CRB_PEG_1                   UNM_CRB_BASE ( UNM_CRB_BLK_PEG_1 )
 197 #define UNM_PEG_1_HALT_STATUS           ( UNM_CRB_PEG_1 + 0x00030 )
 198 #define UNM_PEG_1_HALT                  ( UNM_CRB_PEG_1 + 0x0003c )
 199
 200 #define UNM_CRB_PEG_2                   UNM_CRB_BASE ( UNM_CRB_BLK_PEG_2 )
 201 #define UNM_PEG_2_HALT_STATUS           ( UNM_CRB_PEG_2 + 0x00030 )
 202 #define UNM_PEG_2_HALT                  ( UNM_CRB_PEG_2 + 0x0003c )
 203
 204 #define UNM_CRB_PEG_3                   UNM_CRB_BASE ( UNM_CRB_BLK_PEG_3 )
 205 #define UNM_PEG_3_HALT_STATUS           ( UNM_CRB_PEG_3 + 0x00030 )
 206 #define UNM_PEG_3_HALT                  ( UNM_CRB_PEG_3 + 0x0003c )
 207
 208 #define UNM_CRB_PEG_4                   UNM_CRB_BASE ( UNM_CRB_BLK_PEG_4 )
 209 #define UNM_PEG_4_HALT_STATUS           ( UNM_CRB_PEG_4 + 0x00030 )
 210 #define UNM_PEG_4_HALT                  ( UNM_CRB_PEG_4 + 0x0003c )
 211
 212 #endif /* _PHANTOM_H */