src/include/i82365.h

   1 /*
   2  * i82365.h 1.15 1999/10/25 20:03:34
   3  *
   4  * The contents of this file may be used under the
   5  * terms of the GNU General Public License version 2 (the "GPL").
   6  *
   7  * Software distributed under the License is distributed on an "AS IS"
   8  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
   9  * the License for the specific language governing rights and
  10  * limitations under the License.
  11  *
  12  * The initial developer of the original code is David A. Hinds
  13  * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
  14  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
  15  */
  16
  17 #ifndef _LINUX_I82365_H
  18 #define _LINUX_I82365_H
  19
  20 /* register definitions for the Intel 82365SL PCMCIA controller */
  21
  22 /* Offsets for PCIC registers */
  23 #define I365_IDENT      0x00    /* Identification and revision */
  24 #define I365_STATUS     0x01    /* Interface status */
  25 #define I365_POWER      0x02    /* Power and RESETDRV control */
  26 #define I365_INTCTL     0x03    /* Interrupt and general control */
  27 #define I365_CSC        0x04    /* Card status change */
  28 #define I365_CSCINT     0x05    /* Card status change interrupt control */
  29 #define I365_ADDRWIN    0x06    /* Address window enable */
  30 #define I365_IOCTL      0x07    /* I/O control */
  31 #define I365_GENCTL     0x16    /* Card detect and general control */
  32 #define I365_GBLCTL     0x1E    /* Global control register */
  33
  34 /* Offsets for I/O and memory window registers */
  35 #define I365_IO(map)    (0x08+((map)<<2))
  36 #define I365_MEM(map)   (0x10+((map)<<3))
  37 #define I365_W_START    0
  38 #define I365_W_STOP     2
  39 #define I365_W_OFF      4
  40
  41 /* Flags for I365_STATUS */
  42 #define I365_CS_BVD1    0x01
  43 #define I365_CS_STSCHG  0x01
  44 #define I365_CS_BVD2    0x02
  45 #define I365_CS_SPKR    0x02
  46 #define I365_CS_DETECT  0x0C
  47 #define I365_CS_WRPROT  0x10
  48 #define I365_CS_READY   0x20    /* Inverted */
  49 #define I365_CS_POWERON 0x40
  50 #define I365_CS_GPI     0x80
  51
  52 /* Flags for I365_POWER */
  53 #define I365_PWR_OFF    0x00    /* Turn off the socket */
  54 #define I365_PWR_OUT    0x80    /* Output enable */
  55 #define I365_PWR_NORESET 0x40   /* Disable RESETDRV on resume */
  56 #define I365_PWR_AUTO   0x20    /* Auto pwr switch enable */
  57 #define I365_VCC_MASK   0x18    /* Mask for turning off Vcc */
  58 /* There are different layouts for B-step and DF-step chips: the B
  59    step has independent Vpp1/Vpp2 control, and the DF step has only
  60    Vpp1 control, plus 3V control */
  61 #define I365_VCC_5V     0x10    /* Vcc = 5.0v */
  62 #define I365_VCC_3V     0x18    /* Vcc = 3.3v */
  63 #define I365_VPP2_MASK  0x0c    /* Mask for turning off Vpp2 */
  64 #define I365_VPP2_5V    0x04    /* Vpp2 = 5.0v */
  65 #define I365_VPP2_12V   0x08    /* Vpp2 = 12.0v */
  66 #define I365_VPP1_MASK  0x03    /* Mask for turning off Vpp1 */
  67 #define I365_VPP1_5V    0x01    /* Vpp2 = 5.0v */
  68 #define I365_VPP1_12V   0x02    /* Vpp2 = 12.0v */
  69
  70 /* Flags for I365_INTCTL */
  71 #define I365_RING_ENA   0x80
  72 #define I365_PC_RESET   0x40
  73 #define I365_PC_IOCARD  0x20
  74 #define I365_INTR_ENA   0x10
  75 #define I365_IRQ_MASK   0x0F
  76
  77 /* Flags for I365_CSC and I365_CSCINT*/
  78 #define I365_CSC_BVD1   0x01
  79 #define I365_CSC_STSCHG 0x01
  80 #define I365_CSC_BVD2   0x02
  81 #define I365_CSC_READY  0x04
  82 #define I365_CSC_DETECT 0x08
  83 #define I365_CSC_ANY    0x0F
  84 #define I365_CSC_GPI    0x10
  85
  86 /* Flags for I365_ADDRWIN */
  87 #define I365_ENA_IO(map)        (0x40 << (map))
  88 #define I365_ENA_MEM(map)       (0x01 << (map))
  89
  90 /* Flags for I365_IOCTL */
  91 #define I365_IOCTL_MASK(map)    (0x0F << (map<<2))
  92 #define I365_IOCTL_WAIT(map)    (0x08 << (map<<2))
  93 #define I365_IOCTL_0WS(map)     (0x04 << (map<<2))
  94 #define I365_IOCTL_IOCS16(map)  (0x02 << (map<<2))
  95 #define I365_IOCTL_16BIT(map)   (0x01 << (map<<2))
  96
  97 /* Flags for I365_GENCTL */
  98 #define I365_CTL_16DELAY        0x01
  99 #define I365_CTL_RESET          0x02
 100 #define I365_CTL_GPI_ENA        0x04
 101 #define I365_CTL_GPI_CTL        0x08
 102 #define I365_CTL_RESUME         0x10
 103 #define I365_CTL_SW_IRQ         0x20
 104
 105 /* Flags for I365_GBLCTL */
 106 #define I365_GBL_PWRDOWN        0x01
 107 #define I365_GBL_CSC_LEV        0x02
 108 #define I365_GBL_WRBACK         0x04
 109 #define I365_GBL_IRQ_0_LEV      0x08
 110 #define I365_GBL_IRQ_1_LEV      0x10
 111
 112 /* Flags for memory window registers */
 113 #define I365_MEM_16BIT  0x8000  /* In memory start high byte */
 114 #define I365_MEM_0WS    0x4000
 115 #define I365_MEM_WS1    0x8000  /* In memory stop high byte */
 116 #define I365_MEM_WS0    0x4000
 117 #define I365_MEM_WRPROT 0x8000  /* In offset high byte */
 118 #define I365_MEM_REG    0x4000
 119
 120 #define I365_REG(slot, reg)     (((slot) << 6) + reg)
 121
 122 #endif /* _LINUX_I82365_H */
 123
 124 //*****************************************************************************
 125 //*****************************************************************************
 126 //*****************************************************************************
 127 //*****************************************************************************
 128 //*****************************************************************************
 129 // Beginning vg468.h (for VADEM chipset)
 130
 131 #ifndef _LINUX_VG468_H
 132 #define _LINUX_VG468_H
 133
 134 /* Special bit in I365_IDENT used for Vadem chip detection */
 135 #define I365_IDENT_VADEM        0x08
 136
 137 /* Special definitions in I365_POWER */
 138 #define VG468_VPP2_MASK         0x0c
 139 #define VG468_VPP2_5V           0x04
 140 #define VG468_VPP2_12V          0x08
 141
 142 /* Unique Vadem registers */
 143 #define VG469_VSENSE            0x1f    /* Card voltage sense */
 144 #define VG469_VSELECT           0x2f    /* Card voltage select */
 145 #define VG468_CTL               0x38    /* Control register */
 146 #define VG468_TIMER             0x39    /* Timer control */
 147 #define VG468_MISC              0x3a    /* Miscellaneous */
 148 #define VG468_GPIO_CFG          0x3b    /* GPIO configuration */
 149 #define VG469_EXT_MODE          0x3c    /* Extended mode register */
 150 #define VG468_SELECT            0x3d    /* Programmable chip select */
 151 #define VG468_SELECT_CFG        0x3e    /* Chip select configuration */
 152 #define VG468_ATA               0x3f    /* ATA control */
 153
 154 /* Flags for VG469_VSENSE */
 155 #define VG469_VSENSE_A_VS1      0x01
 156 #define VG469_VSENSE_A_VS2      0x02
 157 #define VG469_VSENSE_B_VS1      0x04
 158 #define VG469_VSENSE_B_VS2      0x08
 159
 160 /* Flags for VG469_VSELECT */
 161 #define VG469_VSEL_VCC          0x03
 162 #define VG469_VSEL_5V           0x00
 163 #define VG469_VSEL_3V           0x03
 164 #define VG469_VSEL_MAX          0x0c
 165 #define VG469_VSEL_EXT_STAT     0x10
 166 #define VG469_VSEL_EXT_BUS      0x20
 167 #define VG469_VSEL_MIXED        0x40
 168 #define VG469_VSEL_ISA          0x80
 169
 170 /* Flags for VG468_CTL */
 171 #define VG468_CTL_SLOW          0x01    /* 600ns memory timing */
 172 #define VG468_CTL_ASYNC         0x02    /* Asynchronous bus clocking */
 173 #define VG468_CTL_TSSI          0x08    /* Tri-state some outputs */
 174 #define VG468_CTL_DELAY         0x10    /* Card detect debounce */
 175 #define VG468_CTL_INPACK        0x20    /* Obey INPACK signal? */
 176 #define VG468_CTL_POLARITY      0x40    /* VCCEN polarity */
 177 #define VG468_CTL_COMPAT        0x80    /* Compatibility stuff */
 178
 179 #define VG469_CTL_WS_COMPAT     0x04    /* Wait state compatibility */
 180 #define VG469_CTL_STRETCH       0x10    /* LED stretch */
 181
 182 /* Flags for VG468_TIMER */
 183 #define VG468_TIMER_ZEROPWR     0x10    /* Zero power control */
 184 #define VG468_TIMER_SIGEN       0x20    /* Power up */
 185 #define VG468_TIMER_STATUS      0x40    /* Activity timer status */
 186 #define VG468_TIMER_RES         0x80    /* Timer resolution */
 187 #define VG468_TIMER_MASK        0x0f    /* Activity timer timeout */
 188
 189 /* Flags for VG468_MISC */
 190 #define VG468_MISC_GPIO         0x04    /* General-purpose IO */
 191 #define VG468_MISC_DMAWSB       0x08    /* DMA wait state control */
 192 #define VG469_MISC_LEDENA       0x10    /* LED enable */
 193 #define VG468_MISC_VADEMREV     0x40    /* Vadem revision control */
 194 #define VG468_MISC_UNLOCK       0x80    /* Unique register lock */
 195
 196 /* Flags for VG469_EXT_MODE_A */
 197 #define VG469_MODE_VPPST        0x03    /* Vpp steering control */
 198 #define VG469_MODE_INT_SENSE    0x04    /* Internal voltage sense */
 199 #define VG469_MODE_CABLE        0x08
 200 #define VG469_MODE_COMPAT       0x10    /* i82365sl B or DF step */
 201 #define VG469_MODE_TEST         0x20
 202 #define VG469_MODE_RIO          0x40    /* Steer RIO to INTR? */
 203
 204 /* Flags for VG469_EXT_MODE_B */
 205 #define VG469_MODE_B_3V         0x01    /* 3.3v for socket B */
 206
 207 #endif /* _LINUX_VG468_H */
 208
 209
 210 //*****************************************************************************
 211 //*****************************************************************************
 212 //*****************************************************************************
 213 //*****************************************************************************
 214 //*****************************************************************************
 215 // Beginning ricoh.h (RICOH chipsets)
 216
 217 #ifndef _LINUX_RICOH_H
 218 #define _LINUX_RICOH_H
 219
 220
 221 #define RF5C_MODE_CTL           0x1f    /* Mode control */
 222 #define RF5C_PWR_CTL            0x2f    /* Mixed voltage control */
 223 #define RF5C_CHIP_ID            0x3a    /* Chip identification */
 224 #define RF5C_MODE_CTL_3         0x3b    /* Mode control 3 */
 225
 226 /* I/O window address offset */
 227 #define RF5C_IO_OFF(w)          (0x36+((w)<<1))
 228
 229 /* Flags for RF5C_MODE_CTL */
 230 #define RF5C_MODE_ATA           0x01    /* ATA mode */
 231 #define RF5C_MODE_LED_ENA       0x02    /* IRQ 12 is LED */
 232 #define RF5C_MODE_CA21          0x04
 233 #define RF5C_MODE_CA22          0x08
 234 #define RF5C_MODE_CA23          0x10
 235 #define RF5C_MODE_CA24          0x20
 236 #define RF5C_MODE_CA25          0x40
 237 #define RF5C_MODE_3STATE_BIT7   0x80
 238
 239 /* Flags for RF5C_PWR_CTL */
 240 #define RF5C_PWR_VCC_3V         0x01
 241 #define RF5C_PWR_IREQ_HIGH      0x02
 242 #define RF5C_PWR_INPACK_ENA     0x04
 243 #define RF5C_PWR_5V_DET         0x08
 244 #define RF5C_PWR_TC_SEL         0x10    /* Terminal Count: irq 11 or 15 */
 245 #define RF5C_PWR_DREQ_LOW       0x20
 246 #define RF5C_PWR_DREQ_OFF       0x00    /* DREQ steering control */
 247 #define RF5C_PWR_DREQ_INPACK    0x40
 248 #define RF5C_PWR_DREQ_SPKR      0x80
 249 #define RF5C_PWR_DREQ_IOIS16    0xc0
 250
 251 /* Values for RF5C_CHIP_ID */
 252 #define RF5C_CHIP_RF5C296       0x32
 253 #define RF5C_CHIP_RF5C396       0xb2
 254
 255 /* Flags for RF5C_MODE_CTL_3 */
 256 #define RF5C_MCTL3_DISABLE      0x01    /* Disable PCMCIA interface */
 257 #define RF5C_MCTL3_DMA_ENA      0x02
 258
 259 /* Register definitions for Ricoh PCI-to-CardBus bridges */
 260
 261 /* Extra bits in CB_BRIDGE_CONTROL */
 262 #define RL5C46X_BCR_3E0_ENA             0x0800
 263 #define RL5C46X_BCR_3E2_ENA             0x1000
 264
 265 /* Bridge Configuration Register */
 266 #define RL5C4XX_CONFIG                  0x80    /* 16 bit */
 267 #define  RL5C4XX_CONFIG_IO_1_MODE       0x0200
 268 #define  RL5C4XX_CONFIG_IO_0_MODE       0x0100
 269 #define  RL5C4XX_CONFIG_PREFETCH        0x0001
 270
 271
 272 /* Misc Control Register */
 273 #define RL5C4XX_MISC                    0x0082  /* 16 bit */
 274 #define  RL5C4XX_MISC_HW_SUSPEND_ENA    0x0002
 275 #define  RL5C4XX_MISC_VCCEN_POL         0x0100
 276 #define  RL5C4XX_MISC_VPPEN_POL         0x0200
 277 #define  RL5C46X_MISC_SUSPEND           0x0001
 278 #define  RL5C46X_MISC_PWR_SAVE_2        0x0004
 279 #define  RL5C46X_MISC_IFACE_BUSY        0x0008
 280 #define  RL5C46X_MISC_B_LOCK            0x0010
 281 #define  RL5C46X_MISC_A_LOCK            0x0020
 282 #define  RL5C46X_MISC_PCI_LOCK          0x0040
 283 #define  RL5C47X_MISC_IFACE_BUSY        0x0004
 284 #define  RL5C47X_MISC_PCI_INT_MASK      0x0018
 285 #define  RL5C47X_MISC_PCI_INT_DIS       0x0020
 286 #define  RL5C47X_MISC_SUBSYS_WR         0x0040
 287 #define  RL5C47X_MISC_SRIRQ_ENA         0x0080
 288 #define  RL5C47X_MISC_5V_DISABLE        0x0400
 289 #define  RL5C47X_MISC_LED_POL           0x0800
 290
 291 /* 16-bit Interface Control Register */
 292 #define RL5C4XX_16BIT_CTL               0x0084  /* 16 bit */
 293 #define  RL5C4XX_16CTL_IO_TIMING        0x0100
 294 #define  RL5C4XX_16CTL_MEM_TIMING       0x0200
 295 #define  RL5C46X_16CTL_LEVEL_1          0x0010
 296 #define  RL5C46X_16CTL_LEVEL_2          0x0020
 297
 298 /* 16-bit IO and memory timing registers */
 299 #define RL5C4XX_16BIT_IO_0              0x0088  /* 16 bit */
 300 #define RL5C4XX_16BIT_MEM_0             0x0088  /* 16 bit */
 301 #define  RL5C4XX_SETUP_MASK             0x0007
 302 #define  RL5C4XX_SETUP_SHIFT            0
 303 #define  RL5C4XX_CMD_MASK               0x01f0
 304 #define  RL5C4XX_CMD_SHIFT              4
 305 #define  RL5C4XX_HOLD_MASK              0x1c00
 306 #define  RL5C4XX_HOLD_SHIFT             10
 307 #define  RL5C4XX_MISC_CONTROL           0x2F /* 8 bit */
 308 #define  RL5C4XX_ZV_ENABLE              0x08
 309
 310 #endif /* _LINUX_RICOH_H */
 311
 312
 313 //*****************************************************************************
 314 //*****************************************************************************
 315 //*****************************************************************************
 316 //*****************************************************************************
 317 //*****************************************************************************
 318 // Beginning cirrus.h (CIRRUS chipsets)
 319
 320 #ifndef _LINUX_CIRRUS_H
 321 #define _LINUX_CIRRUS_H
 322
 323 #ifndef PCI_VENDOR_ID_CIRRUS
 324 #define PCI_VENDOR_ID_CIRRUS            0x1013
 325 #endif
 326 #ifndef PCI_DEVICE_ID_CIRRUS_6729
 327 #define PCI_DEVICE_ID_CIRRUS_6729       0x1100
 328 #endif
 329 #ifndef PCI_DEVICE_ID_CIRRUS_6832
 330 #define PCI_DEVICE_ID_CIRRUS_6832       0x1110
 331 #endif
 332
 333 #define PD67_MISC_CTL_1         0x16    /* Misc control 1 */
 334 #define PD67_FIFO_CTL           0x17    /* FIFO control */
 335 #define PD67_MISC_CTL_2         0x1E    /* Misc control 2 */
 336 #define PD67_CHIP_INFO          0x1f    /* Chip information */
 337 #define PD67_ATA_CTL            0x026   /* 6730: ATA control */
 338 #define PD67_EXT_INDEX          0x2e    /* Extension index */
 339 #define PD67_EXT_DATA           0x2f    /* Extension data */
 340
 341 /* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
 342 #define PD67_DATA_MASK0         0x01    /* Data mask 0 */
 343 #define PD67_DATA_MASK1         0x02    /* Data mask 1 */
 344 #define PD67_DMA_CTL            0x03    /* DMA control */
 345
 346 /* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
 347 #define PD67_EXT_CTL_1          0x03    /* Extension control 1 */
 348 #define PD67_MEM_PAGE(n)        ((n)+5) /* PCI window bits 31:24 */
 349 #define PD67_EXTERN_DATA        0x0a
 350 #define PD67_MISC_CTL_3         0x25
 351 #define PD67_SMB_PWR_CTL        0x26
 352
 353 /* I/O window address offset */
 354 #define PD67_IO_OFF(w)          (0x36+((w)<<1))
 355
 356 /* Timing register sets */
 357 #define PD67_TIME_SETUP(n)      (0x3a + 3*(n))
 358 #define PD67_TIME_CMD(n)        (0x3b + 3*(n))
 359 #define PD67_TIME_RECOV(n)      (0x3c + 3*(n))
 360
 361 /* Flags for PD67_MISC_CTL_1 */
 362 #define PD67_MC1_5V_DET         0x01    /* 5v detect */
 363 #define PD67_MC1_MEDIA_ENA      0x01    /* 6730: Multimedia enable */
 364 #define PD67_MC1_VCC_3V         0x02    /* 3.3v Vcc */
 365 #define PD67_MC1_PULSE_MGMT     0x04
 366 #define PD67_MC1_PULSE_IRQ      0x08
 367 #define PD67_MC1_SPKR_ENA       0x10
 368 #define PD67_MC1_INPACK_ENA     0x80
 369
 370 /* Flags for PD67_FIFO_CTL */
 371 #define PD67_FIFO_EMPTY         0x80
 372
 373 /* Flags for PD67_MISC_CTL_2 */
 374 #define PD67_MC2_FREQ_BYPASS    0x01
 375 #define PD67_MC2_DYNAMIC_MODE   0x02
 376 #define PD67_MC2_SUSPEND        0x04
 377 #define PD67_MC2_5V_CORE        0x08
 378 #define PD67_MC2_LED_ENA        0x10    /* IRQ 12 is LED enable */
 379 #define PD67_MC2_FAST_PCI       0x10    /* 6729: PCI bus > 25 MHz */
 380 #define PD67_MC2_3STATE_BIT7    0x20    /* Floppy change bit */
 381 #define PD67_MC2_DMA_MODE       0x40
 382 #define PD67_MC2_IRQ15_RI       0x80    /* IRQ 15 is ring enable */
 383
 384 /* Flags for PD67_CHIP_INFO */
 385 #define PD67_INFO_SLOTS         0x20    /* 0 = 1 slot, 1 = 2 slots */
 386 #define PD67_INFO_CHIP_ID       0xc0
 387 #define PD67_INFO_REV           0x1c
 388
 389 /* Fields in PD67_TIME_* registers */
 390 #define PD67_TIME_SCALE         0xc0
 391 #define PD67_TIME_SCALE_1       0x00
 392 #define PD67_TIME_SCALE_16      0x40
 393 #define PD67_TIME_SCALE_256     0x80
 394 #define PD67_TIME_SCALE_4096    0xc0
 395 #define PD67_TIME_MULT          0x3f
 396
 397 /* Fields in PD67_DMA_CTL */
 398 #define PD67_DMA_MODE           0xc0
 399 #define PD67_DMA_OFF            0x00
 400 #define PD67_DMA_DREQ_INPACK    0x40
 401 #define PD67_DMA_DREQ_WP        0x80
 402 #define PD67_DMA_DREQ_BVD2      0xc0
 403 #define PD67_DMA_PULLUP         0x20    /* Disable socket pullups? */
 404
 405 /* Fields in PD67_EXT_CTL_1 */
 406 #define PD67_EC1_VCC_PWR_LOCK   0x01
 407 #define PD67_EC1_AUTO_PWR_CLEAR 0x02
 408 #define PD67_EC1_LED_ENA        0x04
 409 #define PD67_EC1_INV_CARD_IRQ   0x08
 410 #define PD67_EC1_INV_MGMT_IRQ   0x10
 411 #define PD67_EC1_PULLUP_CTL     0x20
 412
 413 /* Fields in PD67_MISC_CTL_3 */
 414 #define PD67_MC3_IRQ_MASK       0x03
 415 #define PD67_MC3_IRQ_PCPCI      0x00
 416 #define PD67_MC3_IRQ_EXTERN     0x01
 417 #define PD67_MC3_IRQ_PCIWAY     0x02
 418 #define PD67_MC3_IRQ_PCI        0x03
 419 #define PD67_MC3_PWR_MASK       0x0c
 420 #define PD67_MC3_PWR_SERIAL     0x00
 421 #define PD67_MC3_PWR_TI2202     0x08
 422 #define PD67_MC3_PWR_SMB        0x0c
 423
 424 /* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */
 425
 426 /* PD6832 extension registers -- indexed in PD67_EXT_INDEX */
 427 #define PD68_EXT_CTL_2                  0x0b
 428 #define PD68_PCI_SPACE                  0x22
 429 #define PD68_PCCARD_SPACE               0x23
 430 #define PD68_WINDOW_TYPE                0x24
 431 #define PD68_EXT_CSC                    0x2e
 432 #define PD68_MISC_CTL_4                 0x2f
 433 #define PD68_MISC_CTL_5                 0x30
 434 #define PD68_MISC_CTL_6                 0x31
 435
 436 /* Extra flags in PD67_MISC_CTL_3 */
 437 #define PD68_MC3_HW_SUSP                0x10
 438 #define PD68_MC3_MM_EXPAND              0x40
 439 #define PD68_MC3_MM_ARM                 0x80
 440
 441 /* Bridge Control Register */
 442 #define  PD6832_BCR_MGMT_IRQ_ENA        0x0800
 443
 444 /* Socket Number Register */
 445 #define PD6832_SOCKET_NUMBER            0x004c  /* 8 bit */
 446
 447 #endif /* _LINUX_CIRRUS_H */
 448
 449
 450