src/drivers/net/e1000/e1000_82541.h

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 FILE_LICENCE ( GPL2_OR_LATER );
  30
  31 #ifndef _E1000_82541_H_
  32 #define _E1000_82541_H_
  33
  34 #define NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1)
  35
  36 #define IGP01E1000_PHY_CHANNEL_NUM                    4
  37
  38 #define IGP01E1000_PHY_AGC_A                     0x1172
  39 #define IGP01E1000_PHY_AGC_B                     0x1272
  40 #define IGP01E1000_PHY_AGC_C                     0x1472
  41 #define IGP01E1000_PHY_AGC_D                     0x1872
  42
  43 #define IGP01E1000_PHY_AGC_PARAM_A               0x1171
  44 #define IGP01E1000_PHY_AGC_PARAM_B               0x1271
  45 #define IGP01E1000_PHY_AGC_PARAM_C               0x1471
  46 #define IGP01E1000_PHY_AGC_PARAM_D               0x1871
  47
  48 #define IGP01E1000_PHY_EDAC_MU_INDEX             0xC000
  49 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS      0x8000
  50
  51 #define IGP01E1000_PHY_DSP_RESET                 0x1F33
  52
  53 #define IGP01E1000_PHY_DSP_FFE                   0x1F35
  54 #define IGP01E1000_PHY_DSP_FFE_CM_CP             0x0069
  55 #define IGP01E1000_PHY_DSP_FFE_DEFAULT           0x002A
  56
  57 #define IGP01E1000_IEEE_FORCE_GIG                0x0140
  58 #define IGP01E1000_IEEE_RESTART_AUTONEG          0x3300
  59
  60 #define IGP01E1000_AGC_LENGTH_SHIFT                   7
  61 #define IGP01E1000_AGC_RANGE                         10
  62
  63 #define FFE_IDLE_ERR_COUNT_TIMEOUT_20                20
  64 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100              100
  65
  66 #define IGP01E1000_ANALOG_FUSE_STATUS            0x20D0
  67 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS      0x20D1
  68 #define IGP01E1000_ANALOG_FUSE_CONTROL           0x20DC
  69 #define IGP01E1000_ANALOG_FUSE_BYPASS            0x20DE
  70
  71 #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED     0x0100
  72 #define IGP01E1000_ANALOG_FUSE_FINE_MASK         0x0F80
  73 #define IGP01E1000_ANALOG_FUSE_COARSE_MASK       0x0070
  74 #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH     0x0040
  75 #define IGP01E1000_ANALOG_FUSE_COARSE_10         0x0010
  76 #define IGP01E1000_ANALOG_FUSE_FINE_1            0x0080
  77 #define IGP01E1000_ANALOG_FUSE_FINE_10           0x0500
  78 #define IGP01E1000_ANALOG_FUSE_POLY_MASK         0xF000
  79 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
  80
  81 #define IGP01E1000_MSE_CHANNEL_D                 0x000F
  82 #define IGP01E1000_MSE_CHANNEL_C                 0x00F0
  83 #define IGP01E1000_MSE_CHANNEL_B                 0x0F00
  84 #define IGP01E1000_MSE_CHANNEL_A                 0xF000
  85
  86 #endif