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[e1000e] Add e1000e driver
[gpxe.git] / src / drivers / net / via-velocity.h
bloba43028bd9063bb23342cc85a630104797a3d28f6
1 /*
2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
3 * All rights reserved.
4 *
5 * This software may be redistributed and/or modified under
6 * the terms of the GNU General Public License as published by the Free
7 * Software Foundation; either version 2 of the License, or
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * File: via-velocity.h
16 *
17 * Purpose: Header file to define driver's private structures.
18 *
19 * Author: Chuang Liang-Shing, AJ Jiang
20 *
21 * Date: Jan 24, 2003
22 *
23 * Changes for Etherboot Port:
24 * Copyright (c) 2006 by Timothy Legge <tlegge@rogers.com>
25 */
26
27 #ifndef VELOCITY_H
28 #define VELOCITY_H
29
30 #define VELOCITY_TX_CSUM_SUPPORT
31
32 #define VELOCITY_NAME "via-velocity"
33 #define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver"
34 #define VELOCITY_VERSION "1.13"
35
36 #define PKT_BUF_SZ 1564
37
38 #define MAX_UNITS 8
39 #define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1}
40
41 #define REV_ID_VT6110 (0)
42
43 #define BYTE_REG_BITS_ON(x,p) do { writeb(readb((p))|(x),(p));} while (0)
44 #define WORD_REG_BITS_ON(x,p) do { writew(readw((p))|(x),(p));} while (0)
45 #define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0)
46
47 #define BYTE_REG_BITS_IS_ON(x,p) (readb((p)) & (x))
48 #define WORD_REG_BITS_IS_ON(x,p) (readw((p)) & (x))
49 #define DWORD_REG_BITS_IS_ON(x,p) (readl((p)) & (x))
50
51 #define BYTE_REG_BITS_OFF(x,p) do { writeb(readb((p)) & (~(x)),(p));} while (0)
52 #define WORD_REG_BITS_OFF(x,p) do { writew(readw((p)) & (~(x)),(p));} while (0)
53 #define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0)
54
55 #define BYTE_REG_BITS_SET(x,m,p) do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0)
56 #define WORD_REG_BITS_SET(x,m,p) do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0)
57 #define DWORD_REG_BITS_SET(x,m,p) do { writel( (readl((p)) & (~(m)))|(x),(p));} while (0)
58
59 #define VAR_USED(p) do {(p)=(p);} while (0)
60
61 /*
62 * Purpose: Structures for MAX RX/TX descriptors.
63 */
64
65
66 #define B_OWNED_BY_CHIP 1
67 #define B_OWNED_BY_HOST 0
68
69 /*
70 * Bits in the RSR0 register
71 */
72
73 #define RSR_DETAG 0x0080
74 #define RSR_SNTAG 0x0040
75 #define RSR_RXER 0x0020
76 #define RSR_RL 0x0010
77 #define RSR_CE 0x0008
78 #define RSR_FAE 0x0004
79 #define RSR_CRC 0x0002
80 #define RSR_VIDM 0x0001
81
82 /*
83 * Bits in the RSR1 register
84 */
85
86 #define RSR_RXOK 0x8000 // rx OK
87 #define RSR_PFT 0x4000 // Perfect filtering address match
88 #define RSR_MAR 0x2000 // MAC accept multicast address packet
89 #define RSR_BAR 0x1000 // MAC accept broadcast address packet
90 #define RSR_PHY 0x0800 // MAC accept physical address packet
91 #define RSR_VTAG 0x0400 // 802.1p/1q tagging packet indicator
92 #define RSR_STP 0x0200 // start of packet
93 #define RSR_EDP 0x0100 // end of packet
94
95 /*
96 * Bits in the RSR1 register
97 */
98
99 #define RSR1_RXOK 0x80 // rx OK
100 #define RSR1_PFT 0x40 // Perfect filtering address match
101 #define RSR1_MAR 0x20 // MAC accept multicast address packet
102 #define RSR1_BAR 0x10 // MAC accept broadcast address packet
103 #define RSR1_PHY 0x08 // MAC accept physical address packet
104 #define RSR1_VTAG 0x04 // 802.1p/1q tagging packet indicator
105 #define RSR1_STP 0x02 // start of packet
106 #define RSR1_EDP 0x01 // end of packet
107
108 /*
109 * Bits in the CSM register
110 */
111
112 #define CSM_IPOK 0x40 //IP Checkusm validatiaon ok
113 #define CSM_TUPOK 0x20 //TCP/UDP Checkusm validatiaon ok
114 #define CSM_FRAG 0x10 //Fragment IP datagram
115 #define CSM_IPKT 0x04 //Received an IP packet
116 #define CSM_TCPKT 0x02 //Received a TCP packet
117 #define CSM_UDPKT 0x01 //Received a UDP packet
118
119 /*
120 * Bits in the TSR0 register
121 */
122
123 #define TSR0_ABT 0x0080 // Tx abort because of excessive collision
124 #define TSR0_OWT 0x0040 // Jumbo frame Tx abort
125 #define TSR0_OWC 0x0020 // Out of window collision
126 #define TSR0_COLS 0x0010 // experience collision in this transmit event
127 #define TSR0_NCR3 0x0008 // collision retry counter[3]
128 #define TSR0_NCR2 0x0004 // collision retry counter[2]
129 #define TSR0_NCR1 0x0002 // collision retry counter[1]
130 #define TSR0_NCR0 0x0001 // collision retry counter[0]
131 #define TSR0_TERR 0x8000 //
132 #define TSR0_FDX 0x4000 // current transaction is serviced by full duplex mode
133 #define TSR0_GMII 0x2000 // current transaction is serviced by GMII mode
134 #define TSR0_LNKFL 0x1000 // packet serviced during link down
135 #define TSR0_SHDN 0x0400 // shutdown case
136 #define TSR0_CRS 0x0200 // carrier sense lost
137 #define TSR0_CDH 0x0100 // AQE test fail (CD heartbeat)
138
139 /*
140 * Bits in the TSR1 register
141 */
142
143 #define TSR1_TERR 0x80 //
144 #define TSR1_FDX 0x40 // current transaction is serviced by full duplex mode
145 #define TSR1_GMII 0x20 // current transaction is serviced by GMII mode
146 #define TSR1_LNKFL 0x10 // packet serviced during link down
147 #define TSR1_SHDN 0x04 // shutdown case
148 #define TSR1_CRS 0x02 // carrier sense lost
149 #define TSR1_CDH 0x01 // AQE test fail (CD heartbeat)
150
151 //
152 // Bits in the TCR0 register
153 //
154 #define TCR0_TIC 0x80 // assert interrupt immediately while descriptor has been send complete
155 #define TCR0_PIC 0x40 // priority interrupt request, INA# is issued over adaptive interrupt scheme
156 #define TCR0_VETAG 0x20 // enable VLAN tag
157 #define TCR0_IPCK 0x10 // request IP checksum calculation.
158 #define TCR0_UDPCK 0x08 // request UDP checksum calculation.
159 #define TCR0_TCPCK 0x04 // request TCP checksum calculation.
160 #define TCR0_JMBO 0x02 // indicate a jumbo packet in GMAC side
161 #define TCR0_CRC 0x01 // disable CRC generation
162
163 #define TCPLS_NORMAL 3
164 #define TCPLS_START 2
165 #define TCPLS_END 1
166 #define TCPLS_MED 0
167
168
169 // max transmit or receive buffer size
170 #define CB_RX_BUF_SIZE 2048UL // max buffer size
171 // NOTE: must be multiple of 4
172
173 #define CB_MAX_RD_NUM 512 // MAX # of RD
174 #define CB_MAX_TD_NUM 256 // MAX # of TD
175
176 #define CB_INIT_RD_NUM_3119 128 // init # of RD, for setup VT3119
177 #define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119
178
179 #define CB_INIT_RD_NUM 128 // init # of RD, for setup default
180 #define CB_INIT_TD_NUM 64 // init # of TD, for setup default
181
182 // for 3119
183 #define CB_TD_RING_NUM 4 // # of TD rings.
184 #define CB_MAX_SEG_PER_PKT 7 // max data seg per packet (Tx)
185
186
187 /*
188 * If collisions excess 15 times , tx will abort, and
189 * if tx fifo underflow, tx will fail
190 * we should try to resend it
191 */
192
193 #define CB_MAX_TX_ABORT_RETRY 3
194
195 /*
196 * Receive descriptor
197 */
198
199 struct rdesc0 {
200 u16 RSR; /* Receive status */
201 u16 len:14; /* Received packet length */
202 u16 reserved:1;
203 u16 owner:1; /* Who owns this buffer ? */
204 };
205
206 struct rdesc1 {
207 u16 PQTAG;
208 u8 CSM;
209 u8 IPKT;
210 };
211
212 struct rx_desc {
213 struct rdesc0 rdesc0;
214 struct rdesc1 rdesc1;
215 u32 pa_low; /* Low 32 bit PCI address */
216 u16 pa_high; /* Next 16 bit PCI address (48 total) */
217 u16 len:15; /* Frame size */
218 u16 inten:1; /* Enable interrupt */
219 } __attribute__ ((__packed__));
220
221 /*
222 * Transmit descriptor
223 */
224
225 struct tdesc0 {
226 u16 TSR; /* Transmit status register */
227 u16 pktsize:14; /* Size of frame */
228 u16 reserved:1;
229 u16 owner:1; /* Who owns the buffer */
230 };
231
232 struct pqinf { /* Priority queue info */
233 u16 VID:12;
234 u16 CFI:1;
235 u16 priority:3;
236 } __attribute__ ((__packed__));
237
238 struct tdesc1 {
239 struct pqinf pqinf;
240 u8 TCR;
241 u8 TCPLS:2;
242 u8 reserved:2;
243 u8 CMDZ:4;
244 } __attribute__ ((__packed__));
245
246 struct td_buf {
247 u32 pa_low;
248 u16 pa_high;
249 u16 bufsize:14;
250 u16 reserved:1;
251 u16 queue:1;
252 } __attribute__ ((__packed__));
253
254 struct tx_desc {
255 struct tdesc0 tdesc0;
256 struct tdesc1 tdesc1;
257 struct td_buf td_buf[7];
258 };
259
260 #ifdef LINUX
261 struct velocity_rd_info {
262 struct sk_buff *skb;
263 dma_addr_t skb_dma;
264 };
265
266
267 /**
268 * alloc_rd_info - allocate an rd info block
269 *
270 * Alocate and initialize a receive info structure used for keeping
271 * track of kernel side information related to each receive
272 * descriptor we are using
273 */
274
275 static inline struct velocity_rd_info *alloc_rd_info(void)
276 {
277 struct velocity_rd_info *ptr;
278 if ((ptr =
279 kmalloc(sizeof(struct velocity_rd_info), GFP_ATOMIC)) == NULL)
280 return NULL;
281 else {
282 memset(ptr, 0, sizeof(struct velocity_rd_info));
283 return ptr;
284 }
285 }
286
287 /*
288 * Used to track transmit side buffers.
289 */
290
291 struct velocity_td_info {
292 struct sk_buff *skb;
293 u8 *buf;
294 int nskb_dma;
295 dma_addr_t skb_dma[7];
296 dma_addr_t buf_dma;
297 };
298
299 #endif
300 enum {
301 OWNED_BY_HOST = 0,
302 OWNED_BY_NIC = 1
303 } velocity_owner;
304
305
306 /*
307 * MAC registers and macros.
308 */
309
310
311 #define MCAM_SIZE 64
312 #define VCAM_SIZE 64
313 #define TX_QUEUE_NO 4
314
315 #define MAX_HW_MIB_COUNTER 32
316 #define VELOCITY_MIN_MTU (1514-14)
317 #define VELOCITY_MAX_MTU (9000)
318
319 /*
320 * Registers in the MAC
321 */
322
323 #define MAC_REG_PAR 0x00 // physical address
324 #define MAC_REG_RCR 0x06
325 #define MAC_REG_TCR 0x07
326 #define MAC_REG_CR0_SET 0x08
327 #define MAC_REG_CR1_SET 0x09
328 #define MAC_REG_CR2_SET 0x0A
329 #define MAC_REG_CR3_SET 0x0B
330 #define MAC_REG_CR0_CLR 0x0C
331 #define MAC_REG_CR1_CLR 0x0D
332 #define MAC_REG_CR2_CLR 0x0E
333 #define MAC_REG_CR3_CLR 0x0F
334 #define MAC_REG_MAR 0x10
335 #define MAC_REG_CAM 0x10
336 #define MAC_REG_DEC_BASE_HI 0x18
337 #define MAC_REG_DBF_BASE_HI 0x1C
338 #define MAC_REG_ISR_CTL 0x20
339 #define MAC_REG_ISR_HOTMR 0x20
340 #define MAC_REG_ISR_TSUPTHR 0x20
341 #define MAC_REG_ISR_RSUPTHR 0x20
342 #define MAC_REG_ISR_CTL1 0x21
343 #define MAC_REG_TXE_SR 0x22
344 #define MAC_REG_RXE_SR 0x23
345 #define MAC_REG_ISR 0x24
346 #define MAC_REG_ISR0 0x24
347 #define MAC_REG_ISR1 0x25
348 #define MAC_REG_ISR2 0x26
349 #define MAC_REG_ISR3 0x27
350 #define MAC_REG_IMR 0x28
351 #define MAC_REG_IMR0 0x28
352 #define MAC_REG_IMR1 0x29
353 #define MAC_REG_IMR2 0x2A
354 #define MAC_REG_IMR3 0x2B
355 #define MAC_REG_TDCSR_SET 0x30
356 #define MAC_REG_RDCSR_SET 0x32
357 #define MAC_REG_TDCSR_CLR 0x34
358 #define MAC_REG_RDCSR_CLR 0x36
359 #define MAC_REG_RDBASE_LO 0x38
360 #define MAC_REG_RDINDX 0x3C
361 #define MAC_REG_TDBASE_LO 0x40
362 #define MAC_REG_RDCSIZE 0x50
363 #define MAC_REG_TDCSIZE 0x52
364 #define MAC_REG_TDINDX 0x54
365 #define MAC_REG_TDIDX0 0x54
366 #define MAC_REG_TDIDX1 0x56
367 #define MAC_REG_TDIDX2 0x58
368 #define MAC_REG_TDIDX3 0x5A
369 #define MAC_REG_PAUSE_TIMER 0x5C
370 #define MAC_REG_RBRDU 0x5E
371 #define MAC_REG_FIFO_TEST0 0x60
372 #define MAC_REG_FIFO_TEST1 0x64
373 #define MAC_REG_CAMADDR 0x68
374 #define MAC_REG_CAMCR 0x69
375 #define MAC_REG_GFTEST 0x6A
376 #define MAC_REG_FTSTCMD 0x6B
377 #define MAC_REG_MIICFG 0x6C
378 #define MAC_REG_MIISR 0x6D
379 #define MAC_REG_PHYSR0 0x6E
380 #define MAC_REG_PHYSR1 0x6F
381 #define MAC_REG_MIICR 0x70
382 #define MAC_REG_MIIADR 0x71
383 #define MAC_REG_MIIDATA 0x72
384 #define MAC_REG_SOFT_TIMER0 0x74
385 #define MAC_REG_SOFT_TIMER1 0x76
386 #define MAC_REG_CFGA 0x78
387 #define MAC_REG_CFGB 0x79
388 #define MAC_REG_CFGC 0x7A
389 #define MAC_REG_CFGD 0x7B
390 #define MAC_REG_DCFG0 0x7C
391 #define MAC_REG_DCFG1 0x7D
392 #define MAC_REG_MCFG0 0x7E
393 #define MAC_REG_MCFG1 0x7F
394
395 #define MAC_REG_TBIST 0x80
396 #define MAC_REG_RBIST 0x81
397 #define MAC_REG_PMCC 0x82
398 #define MAC_REG_STICKHW 0x83
399 #define MAC_REG_MIBCR 0x84
400 #define MAC_REG_EERSV 0x85
401 #define MAC_REG_REVID 0x86
402 #define MAC_REG_MIBREAD 0x88
403 #define MAC_REG_BPMA 0x8C
404 #define MAC_REG_EEWR_DATA 0x8C
405 #define MAC_REG_BPMD_WR 0x8F
406 #define MAC_REG_BPCMD 0x90
407 #define MAC_REG_BPMD_RD 0x91
408 #define MAC_REG_EECHKSUM 0x92
409 #define MAC_REG_EECSR 0x93
410 #define MAC_REG_EERD_DATA 0x94
411 #define MAC_REG_EADDR 0x96
412 #define MAC_REG_EMBCMD 0x97
413 #define MAC_REG_JMPSR0 0x98
414 #define MAC_REG_JMPSR1 0x99
415 #define MAC_REG_JMPSR2 0x9A
416 #define MAC_REG_JMPSR3 0x9B
417 #define MAC_REG_CHIPGSR 0x9C
418 #define MAC_REG_TESTCFG 0x9D
419 #define MAC_REG_DEBUG 0x9E
420 #define MAC_REG_CHIPGCR 0x9F
421 #define MAC_REG_WOLCR0_SET 0xA0
422 #define MAC_REG_WOLCR1_SET 0xA1
423 #define MAC_REG_PWCFG_SET 0xA2
424 #define MAC_REG_WOLCFG_SET 0xA3
425 #define MAC_REG_WOLCR0_CLR 0xA4
426 #define MAC_REG_WOLCR1_CLR 0xA5
427 #define MAC_REG_PWCFG_CLR 0xA6
428 #define MAC_REG_WOLCFG_CLR 0xA7
429 #define MAC_REG_WOLSR0_SET 0xA8
430 #define MAC_REG_WOLSR1_SET 0xA9
431 #define MAC_REG_WOLSR0_CLR 0xAC
432 #define MAC_REG_WOLSR1_CLR 0xAD
433 #define MAC_REG_PATRN_CRC0 0xB0
434 #define MAC_REG_PATRN_CRC1 0xB2
435 #define MAC_REG_PATRN_CRC2 0xB4
436 #define MAC_REG_PATRN_CRC3 0xB6
437 #define MAC_REG_PATRN_CRC4 0xB8
438 #define MAC_REG_PATRN_CRC5 0xBA
439 #define MAC_REG_PATRN_CRC6 0xBC
440 #define MAC_REG_PATRN_CRC7 0xBE
441 #define MAC_REG_BYTEMSK0_0 0xC0
442 #define MAC_REG_BYTEMSK0_1 0xC4
443 #define MAC_REG_BYTEMSK0_2 0xC8
444 #define MAC_REG_BYTEMSK0_3 0xCC
445 #define MAC_REG_BYTEMSK1_0 0xD0
446 #define MAC_REG_BYTEMSK1_1 0xD4
447 #define MAC_REG_BYTEMSK1_2 0xD8
448 #define MAC_REG_BYTEMSK1_3 0xDC
449 #define MAC_REG_BYTEMSK2_0 0xE0
450 #define MAC_REG_BYTEMSK2_1 0xE4
451 #define MAC_REG_BYTEMSK2_2 0xE8
452 #define MAC_REG_BYTEMSK2_3 0xEC
453 #define MAC_REG_BYTEMSK3_0 0xF0
454 #define MAC_REG_BYTEMSK3_1 0xF4
455 #define MAC_REG_BYTEMSK3_2 0xF8
456 #define MAC_REG_BYTEMSK3_3 0xFC
457
458 /*
459 * Bits in the RCR register
460 */
461
462 #define RCR_AS 0x80
463 #define RCR_AP 0x40
464 #define RCR_AL 0x20
465 #define RCR_PROM 0x10
466 #define RCR_AB 0x08
467 #define RCR_AM 0x04
468 #define RCR_AR 0x02
469 #define RCR_SEP 0x01
470
471 /*
472 * Bits in the TCR register
473 */
474
475 #define TCR_TB2BDIS 0x80
476 #define TCR_COLTMC1 0x08
477 #define TCR_COLTMC0 0x04
478 #define TCR_LB1 0x02 /* loopback[1] */
479 #define TCR_LB0 0x01 /* loopback[0] */
480
481 /*
482 * Bits in the CR0 register
483 */
484
485 #define CR0_TXON 0x00000008UL
486 #define CR0_RXON 0x00000004UL
487 #define CR0_STOP 0x00000002UL /* stop MAC, default = 1 */
488 #define CR0_STRT 0x00000001UL /* start MAC */
489 #define CR0_SFRST 0x00008000UL /* software reset */
490 #define CR0_TM1EN 0x00004000UL
491 #define CR0_TM0EN 0x00002000UL
492 #define CR0_DPOLL 0x00000800UL /* disable rx/tx auto polling */
493 #define CR0_DISAU 0x00000100UL
494 #define CR0_XONEN 0x00800000UL
495 #define CR0_FDXTFCEN 0x00400000UL /* full-duplex TX flow control enable */
496 #define CR0_FDXRFCEN 0x00200000UL /* full-duplex RX flow control enable */
497 #define CR0_HDXFCEN 0x00100000UL /* half-duplex flow control enable */
498 #define CR0_XHITH1 0x00080000UL /* TX XON high threshold 1 */
499 #define CR0_XHITH0 0x00040000UL /* TX XON high threshold 0 */
500 #define CR0_XLTH1 0x00020000UL /* TX pause frame low threshold 1 */
501 #define CR0_XLTH0 0x00010000UL /* TX pause frame low threshold 0 */
502 #define CR0_GSPRST 0x80000000UL
503 #define CR0_FORSRST 0x40000000UL
504 #define CR0_FPHYRST 0x20000000UL
505 #define CR0_DIAG 0x10000000UL
506 #define CR0_INTPCTL 0x04000000UL
507 #define CR0_GINTMSK1 0x02000000UL
508 #define CR0_GINTMSK0 0x01000000UL
509
510 /*
511 * Bits in the CR1 register
512 */
513
514 #define CR1_SFRST 0x80 /* software reset */
515 #define CR1_TM1EN 0x40
516 #define CR1_TM0EN 0x20
517 #define CR1_DPOLL 0x08 /* disable rx/tx auto polling */
518 #define CR1_DISAU 0x01
519
520 /*
521 * Bits in the CR2 register
522 */
523
524 #define CR2_XONEN 0x80
525 #define CR2_FDXTFCEN 0x40 /* full-duplex TX flow control enable */
526 #define CR2_FDXRFCEN 0x20 /* full-duplex RX flow control enable */
527 #define CR2_HDXFCEN 0x10 /* half-duplex flow control enable */
528 #define CR2_XHITH1 0x08 /* TX XON high threshold 1 */
529 #define CR2_XHITH0 0x04 /* TX XON high threshold 0 */
530 #define CR2_XLTH1 0x02 /* TX pause frame low threshold 1 */
531 #define CR2_XLTH0 0x01 /* TX pause frame low threshold 0 */
532
533 /*
534 * Bits in the CR3 register
535 */
536
537 #define CR3_GSPRST 0x80
538 #define CR3_FORSRST 0x40
539 #define CR3_FPHYRST 0x20
540 #define CR3_DIAG 0x10
541 #define CR3_INTPCTL 0x04
542 #define CR3_GINTMSK1 0x02
543 #define CR3_GINTMSK0 0x01
544
545 #define ISRCTL_UDPINT 0x8000
546 #define ISRCTL_TSUPDIS 0x4000
547 #define ISRCTL_RSUPDIS 0x2000
548 #define ISRCTL_PMSK1 0x1000
549 #define ISRCTL_PMSK0 0x0800
550 #define ISRCTL_INTPD 0x0400
551 #define ISRCTL_HCRLD 0x0200
552 #define ISRCTL_SCRLD 0x0100
553
554 /*
555 * Bits in the ISR_CTL1 register
556 */
557
558 #define ISRCTL1_UDPINT 0x80
559 #define ISRCTL1_TSUPDIS 0x40
560 #define ISRCTL1_RSUPDIS 0x20
561 #define ISRCTL1_PMSK1 0x10
562 #define ISRCTL1_PMSK0 0x08
563 #define ISRCTL1_INTPD 0x04
564 #define ISRCTL1_HCRLD 0x02
565 #define ISRCTL1_SCRLD 0x01
566
567 /*
568 * Bits in the TXE_SR register
569 */
570
571 #define TXESR_TFDBS 0x08
572 #define TXESR_TDWBS 0x04
573 #define TXESR_TDRBS 0x02
574 #define TXESR_TDSTR 0x01
575
576 /*
577 * Bits in the RXE_SR register
578 */
579
580 #define RXESR_RFDBS 0x08
581 #define RXESR_RDWBS 0x04
582 #define RXESR_RDRBS 0x02
583 #define RXESR_RDSTR 0x01
584
585 /*
586 * Bits in the ISR register
587 */
588
589 #define ISR_ISR3 0x80000000UL
590 #define ISR_ISR2 0x40000000UL
591 #define ISR_ISR1 0x20000000UL
592 #define ISR_ISR0 0x10000000UL
593 #define ISR_TXSTLI 0x02000000UL
594 #define ISR_RXSTLI 0x01000000UL
595 #define ISR_HFLD 0x00800000UL
596 #define ISR_UDPI 0x00400000UL
597 #define ISR_MIBFI 0x00200000UL
598 #define ISR_SHDNI 0x00100000UL
599 #define ISR_PHYI 0x00080000UL
600 #define ISR_PWEI 0x00040000UL
601 #define ISR_TMR1I 0x00020000UL
602 #define ISR_TMR0I 0x00010000UL
603 #define ISR_SRCI 0x00008000UL
604 #define ISR_LSTPEI 0x00004000UL
605 #define ISR_LSTEI 0x00002000UL
606 #define ISR_OVFI 0x00001000UL
607 #define ISR_FLONI 0x00000800UL
608 #define ISR_RACEI 0x00000400UL
609 #define ISR_TXWB1I 0x00000200UL
610 #define ISR_TXWB0I 0x00000100UL
611 #define ISR_PTX3I 0x00000080UL
612 #define ISR_PTX2I 0x00000040UL
613 #define ISR_PTX1I 0x00000020UL
614 #define ISR_PTX0I 0x00000010UL
615 #define ISR_PTXI 0x00000008UL
616 #define ISR_PRXI 0x00000004UL
617 #define ISR_PPTXI 0x00000002UL
618 #define ISR_PPRXI 0x00000001UL
619
620 /*
621 * Bits in the IMR register
622 */
623
624 #define IMR_TXSTLM 0x02000000UL
625 #define IMR_UDPIM 0x00400000UL
626 #define IMR_MIBFIM 0x00200000UL
627 #define IMR_SHDNIM 0x00100000UL
628 #define IMR_PHYIM 0x00080000UL
629 #define IMR_PWEIM 0x00040000UL
630 #define IMR_TMR1IM 0x00020000UL
631 #define IMR_TMR0IM 0x00010000UL
632
633 #define IMR_SRCIM 0x00008000UL
634 #define IMR_LSTPEIM 0x00004000UL
635 #define IMR_LSTEIM 0x00002000UL
636 #define IMR_OVFIM 0x00001000UL
637 #define IMR_FLONIM 0x00000800UL
638 #define IMR_RACEIM 0x00000400UL
639 #define IMR_TXWB1IM 0x00000200UL
640 #define IMR_TXWB0IM 0x00000100UL
641
642 #define IMR_PTX3IM 0x00000080UL
643 #define IMR_PTX2IM 0x00000040UL
644 #define IMR_PTX1IM 0x00000020UL
645 #define IMR_PTX0IM 0x00000010UL
646 #define IMR_PTXIM 0x00000008UL
647 #define IMR_PRXIM 0x00000004UL
648 #define IMR_PPTXIM 0x00000002UL
649 #define IMR_PPRXIM 0x00000001UL
650
651 /* 0x0013FB0FUL = initial value of IMR */
652
653 #define INT_MASK_DEF ( IMR_PPTXIM|IMR_PPRXIM| IMR_PTXIM|IMR_PRXIM | \
654 IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM| \
655 IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\
656 IMR_SHDNIM |IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM )
657
658 /*
659 * Bits in the TDCSR0/1, RDCSR0 register
660 */
661
662 #define TRDCSR_DEAD 0x0008
663 #define TRDCSR_WAK 0x0004
664 #define TRDCSR_ACT 0x0002
665 #define TRDCSR_RUN 0x0001
666
667 /*
668 * Bits in the CAMADDR register
669 */
670
671 #define CAMADDR_CAMEN 0x80
672 #define CAMADDR_VCAMSL 0x40
673
674 /*
675 * Bits in the CAMCR register
676 */
677
678 #define CAMCR_PS1 0x80
679 #define CAMCR_PS0 0x40
680 #define CAMCR_AITRPKT 0x20
681 #define CAMCR_AITR16 0x10
682 #define CAMCR_CAMRD 0x08
683 #define CAMCR_CAMWR 0x04
684 #define CAMCR_PS_CAM_MASK 0x40
685 #define CAMCR_PS_CAM_DATA 0x80
686 #define CAMCR_PS_MAR 0x00
687
688 /*
689 * Bits in the MIICFG register
690 */
691
692 #define MIICFG_MPO1 0x80
693 #define MIICFG_MPO0 0x40
694 #define MIICFG_MFDC 0x20
695
696 /*
697 * Bits in the MIISR register
698 */
699
700 #define MIISR_MIDLE 0x80
701
702 /*
703 * Bits in the PHYSR0 register
704 */
705
706 #define PHYSR0_PHYRST 0x80
707 #define PHYSR0_LINKGD 0x40
708 #define PHYSR0_FDPX 0x10
709 #define PHYSR0_SPDG 0x08
710 #define PHYSR0_SPD10 0x04
711 #define PHYSR0_RXFLC 0x02
712 #define PHYSR0_TXFLC 0x01
713
714 /*
715 * Bits in the PHYSR1 register
716 */
717
718 #define PHYSR1_PHYTBI 0x01
719
720 /*
721 * Bits in the MIICR register
722 */
723
724 #define MIICR_MAUTO 0x80
725 #define MIICR_RCMD 0x40
726 #define MIICR_WCMD 0x20
727 #define MIICR_MDPM 0x10
728 #define MIICR_MOUT 0x08
729 #define MIICR_MDO 0x04
730 #define MIICR_MDI 0x02
731 #define MIICR_MDC 0x01
732
733 /*
734 * Bits in the MIIADR register
735 */
736
737 #define MIIADR_SWMPL 0x80
738
739 /*
740 * Bits in the CFGA register
741 */
742
743 #define CFGA_PMHCTG 0x08
744 #define CFGA_GPIO1PD 0x04
745 #define CFGA_ABSHDN 0x02
746 #define CFGA_PACPI 0x01
747
748 /*
749 * Bits in the CFGB register
750 */
751
752 #define CFGB_GTCKOPT 0x80
753 #define CFGB_MIIOPT 0x40
754 #define CFGB_CRSEOPT 0x20
755 #define CFGB_OFSET 0x10
756 #define CFGB_CRANDOM 0x08
757 #define CFGB_CAP 0x04
758 #define CFGB_MBA 0x02
759 #define CFGB_BAKOPT 0x01
760
761 /*
762 * Bits in the CFGC register
763 */
764
765 #define CFGC_EELOAD 0x80
766 #define CFGC_BROPT 0x40
767 #define CFGC_DLYEN 0x20
768 #define CFGC_DTSEL 0x10
769 #define CFGC_BTSEL 0x08
770 #define CFGC_BPS2 0x04 /* bootrom select[2] */
771 #define CFGC_BPS1 0x02 /* bootrom select[1] */
772 #define CFGC_BPS0 0x01 /* bootrom select[0] */
773
774 /*
775 * Bits in the CFGD register
776 */
777
778 #define CFGD_IODIS 0x80
779 #define CFGD_MSLVDACEN 0x40
780 #define CFGD_CFGDACEN 0x20
781 #define CFGD_PCI64EN 0x10
782 #define CFGD_HTMRL4 0x08
783
784 /*
785 * Bits in the DCFG1 register
786 */
787
788 #define DCFG_XMWI 0x8000
789 #define DCFG_XMRM 0x4000
790 #define DCFG_XMRL 0x2000
791 #define DCFG_PERDIS 0x1000
792 #define DCFG_MRWAIT 0x0400
793 #define DCFG_MWWAIT 0x0200
794 #define DCFG_LATMEN 0x0100
795
796 /*
797 * Bits in the MCFG0 register
798 */
799
800 #define MCFG_RXARB 0x0080
801 #define MCFG_RFT1 0x0020
802 #define MCFG_RFT0 0x0010
803 #define MCFG_LOWTHOPT 0x0008
804 #define MCFG_PQEN 0x0004
805 #define MCFG_RTGOPT 0x0002
806 #define MCFG_VIDFR 0x0001
807
808 /*
809 * Bits in the MCFG1 register
810 */
811
812 #define MCFG_TXARB 0x8000
813 #define MCFG_TXQBK1 0x0800
814 #define MCFG_TXQBK0 0x0400
815 #define MCFG_TXQNOBK 0x0200
816 #define MCFG_SNAPOPT 0x0100
817
818 /*
819 * Bits in the PMCC register
820 */
821
822 #define PMCC_DSI 0x80
823 #define PMCC_D2_DIS 0x40
824 #define PMCC_D1_DIS 0x20
825 #define PMCC_D3C_EN 0x10
826 #define PMCC_D3H_EN 0x08
827 #define PMCC_D2_EN 0x04
828 #define PMCC_D1_EN 0x02
829 #define PMCC_D0_EN 0x01
830
831 /*
832 * Bits in STICKHW
833 */
834
835 #define STICKHW_SWPTAG 0x10
836 #define STICKHW_WOLSR 0x08
837 #define STICKHW_WOLEN 0x04
838 #define STICKHW_DS1 0x02 /* R/W by software/cfg cycle */
839 #define STICKHW_DS0 0x01 /* suspend well DS write port */
840
841 /*
842 * Bits in the MIBCR register
843 */
844
845 #define MIBCR_MIBISTOK 0x80
846 #define MIBCR_MIBISTGO 0x40
847 #define MIBCR_MIBINC 0x20
848 #define MIBCR_MIBHI 0x10
849 #define MIBCR_MIBFRZ 0x08
850 #define MIBCR_MIBFLSH 0x04
851 #define MIBCR_MPTRINI 0x02
852 #define MIBCR_MIBCLR 0x01
853
854 /*
855 * Bits in the EERSV register
856 */
857
858 #define EERSV_BOOT_RPL ((u8) 0x01) /* Boot method selection for VT6110 */
859
860 #define EERSV_BOOT_MASK ((u8) 0x06)
861 #define EERSV_BOOT_INT19 ((u8) 0x00)
862 #define EERSV_BOOT_INT18 ((u8) 0x02)
863 #define EERSV_BOOT_LOCAL ((u8) 0x04)
864 #define EERSV_BOOT_BEV ((u8) 0x06)
865
866
867 /*
868 * Bits in BPCMD
869 */
870
871 #define BPCMD_BPDNE 0x80
872 #define BPCMD_EBPWR 0x02
873 #define BPCMD_EBPRD 0x01
874
875 /*
876 * Bits in the EECSR register
877 */
878
879 #define EECSR_EMBP 0x40 /* eeprom embeded programming */
880 #define EECSR_RELOAD 0x20 /* eeprom content reload */
881 #define EECSR_DPM 0x10 /* eeprom direct programming */
882 #define EECSR_ECS 0x08 /* eeprom CS pin */
883 #define EECSR_ECK 0x04 /* eeprom CK pin */
884 #define EECSR_EDI 0x02 /* eeprom DI pin */
885 #define EECSR_EDO 0x01 /* eeprom DO pin */
886
887 /*
888 * Bits in the EMBCMD register
889 */
890
891 #define EMBCMD_EDONE 0x80
892 #define EMBCMD_EWDIS 0x08
893 #define EMBCMD_EWEN 0x04
894 #define EMBCMD_EWR 0x02
895 #define EMBCMD_ERD 0x01
896
897 /*
898 * Bits in TESTCFG register
899 */
900
901 #define TESTCFG_HBDIS 0x80
902
903 /*
904 * Bits in CHIPGCR register
905 */
906
907 #define CHIPGCR_FCGMII 0x80
908 #define CHIPGCR_FCFDX 0x40
909 #define CHIPGCR_FCRESV 0x20
910 #define CHIPGCR_FCMODE 0x10
911 #define CHIPGCR_LPSOPT 0x08
912 #define CHIPGCR_TM1US 0x04
913 #define CHIPGCR_TM0US 0x02
914 #define CHIPGCR_PHYINTEN 0x01
915
916 /*
917 * Bits in WOLCR0
918 */
919
920 #define WOLCR_MSWOLEN7 0x0080 /* enable pattern match filtering */
921 #define WOLCR_MSWOLEN6 0x0040
922 #define WOLCR_MSWOLEN5 0x0020
923 #define WOLCR_MSWOLEN4 0x0010
924 #define WOLCR_MSWOLEN3 0x0008
925 #define WOLCR_MSWOLEN2 0x0004
926 #define WOLCR_MSWOLEN1 0x0002
927 #define WOLCR_MSWOLEN0 0x0001
928 #define WOLCR_ARP_EN 0x0001
929
930 /*
931 * Bits in WOLCR1
932 */
933
934 #define WOLCR_LINKOFF_EN 0x0800 /* link off detected enable */
935 #define WOLCR_LINKON_EN 0x0400 /* link on detected enable */
936 #define WOLCR_MAGIC_EN 0x0200 /* magic packet filter enable */
937 #define WOLCR_UNICAST_EN 0x0100 /* unicast filter enable */
938
939
940 /*
941 * Bits in PWCFG
942 */
943
944 #define PWCFG_PHYPWOPT 0x80 /* internal MII I/F timing */
945 #define PWCFG_PCISTICK 0x40 /* PCI sticky R/W enable */
946 #define PWCFG_WOLTYPE 0x20 /* pulse(1) or button (0) */
947 #define PWCFG_LEGCY_WOL 0x10
948 #define PWCFG_PMCSR_PME_SR 0x08
949 #define PWCFG_PMCSR_PME_EN 0x04 /* control by PCISTICK */
950 #define PWCFG_LEGACY_WOLSR 0x02 /* Legacy WOL_SR shadow */
951 #define PWCFG_LEGACY_WOLEN 0x01 /* Legacy WOL_EN shadow */
952
953 /*
954 * Bits in WOLCFG
955 */
956
957 #define WOLCFG_PMEOVR 0x80 /* for legacy use, force PMEEN always */
958 #define WOLCFG_SAM 0x20 /* accept multicast case reset, default=0 */
959 #define WOLCFG_SAB 0x10 /* accept broadcast case reset, default=0 */
960 #define WOLCFG_SMIIACC 0x08 /* ?? */
961 #define WOLCFG_SGENWH 0x02
962 #define WOLCFG_PHYINTEN 0x01 /* 0:PHYINT trigger enable, 1:use internal MII
963 to report status change */
964 /*
965 * Bits in WOLSR1
966 */
967
968 #define WOLSR_LINKOFF_INT 0x0800
969 #define WOLSR_LINKON_INT 0x0400
970 #define WOLSR_MAGIC_INT 0x0200
971 #define WOLSR_UNICAST_INT 0x0100
972
973 /*
974 * Ethernet address filter type
975 */
976
977 #define PKT_TYPE_NONE 0x0000 /* Turn off receiver */
978 #define PKT_TYPE_DIRECTED 0x0001 /* obselete, directed address is always accepted */
979 #define PKT_TYPE_MULTICAST 0x0002
980 #define PKT_TYPE_ALL_MULTICAST 0x0004
981 #define PKT_TYPE_BROADCAST 0x0008
982 #define PKT_TYPE_PROMISCUOUS 0x0020
983 #define PKT_TYPE_LONG 0x2000 /* NOTE.... the definition of LONG is >2048 bytes in our chip */
984 #define PKT_TYPE_RUNT 0x4000
985 #define PKT_TYPE_ERROR 0x8000 /* Accept error packets, e.g. CRC error */
986
987 /*
988 * Loopback mode
989 */
990
991 #define MAC_LB_NONE 0x00
992 #define MAC_LB_INTERNAL 0x01
993 #define MAC_LB_EXTERNAL 0x02
994
995 /*
996 * Enabled mask value of irq
997 */
998
999 #if defined(_SIM)
1000 #define IMR_MASK_VALUE 0x0033FF0FUL /* initial value of IMR
1001 set IMR0 to 0x0F according to spec */
1002
1003 #else
1004 #define IMR_MASK_VALUE 0x0013FB0FUL /* initial value of IMR
1005 ignore MIBFI,RACEI to
1006 reduce intr. frequency
1007 NOTE.... do not enable NoBuf int mask at driver driver
1008 when (1) NoBuf -> RxThreshold = SF
1009 (2) OK -> RxThreshold = original value
1010 */
1011 #endif
1012
1013 /*
1014 * Revision id
1015 */
1016
1017 #define REV_ID_VT3119_A0 0x00
1018 #define REV_ID_VT3119_A1 0x01
1019 #define REV_ID_VT3216_A0 0x10
1020
1021 /*
1022 * Max time out delay time
1023 */
1024
1025 #define W_MAX_TIMEOUT 0x0FFFU
1026
1027
1028 /*
1029 * MAC registers as a structure. Cannot be directly accessed this
1030 * way but generates offsets for readl/writel() calls
1031 */
1032
1033 struct mac_regs {
1034 volatile u8 PAR[6]; /* 0x00 */
1035 volatile u8 RCR;
1036 volatile u8 TCR;
1037
1038 volatile u32 CR0Set; /* 0x08 */
1039 volatile u32 CR0Clr; /* 0x0C */
1040
1041 volatile u8 MARCAM[8]; /* 0x10 */
1042
1043 volatile u32 DecBaseHi; /* 0x18 */
1044 volatile u16 DbfBaseHi; /* 0x1C */
1045 volatile u16 reserved_1E;
1046
1047 volatile u16 ISRCTL; /* 0x20 */
1048 volatile u8 TXESR;
1049 volatile u8 RXESR;
1050
1051 volatile u32 ISR; /* 0x24 */
1052 volatile u32 IMR;
1053
1054 volatile u32 TDStatusPort; /* 0x2C */
1055
1056 volatile u16 TDCSRSet; /* 0x30 */
1057 volatile u8 RDCSRSet;
1058 volatile u8 reserved_33;
1059 volatile u16 TDCSRClr;
1060 volatile u8 RDCSRClr;
1061 volatile u8 reserved_37;
1062
1063 volatile u32 RDBaseLo; /* 0x38 */
1064 volatile u16 RDIdx; /* 0x3C */
1065 volatile u16 reserved_3E;
1066
1067 volatile u32 TDBaseLo[4]; /* 0x40 */
1068
1069 volatile u16 RDCSize; /* 0x50 */
1070 volatile u16 TDCSize; /* 0x52 */
1071 volatile u16 TDIdx[4]; /* 0x54 */
1072 volatile u16 tx_pause_timer; /* 0x5C */
1073 volatile u16 RBRDU; /* 0x5E */
1074
1075 volatile u32 FIFOTest0; /* 0x60 */
1076 volatile u32 FIFOTest1; /* 0x64 */
1077
1078 volatile u8 CAMADDR; /* 0x68 */
1079 volatile u8 CAMCR; /* 0x69 */
1080 volatile u8 GFTEST; /* 0x6A */
1081 volatile u8 FTSTCMD; /* 0x6B */
1082
1083 volatile u8 MIICFG; /* 0x6C */
1084 volatile u8 MIISR;
1085 volatile u8 PHYSR0;
1086 volatile u8 PHYSR1;
1087 volatile u8 MIICR;
1088 volatile u8 MIIADR;
1089 volatile u16 MIIDATA;
1090
1091 volatile u16 SoftTimer0; /* 0x74 */
1092 volatile u16 SoftTimer1;
1093
1094 volatile u8 CFGA; /* 0x78 */
1095 volatile u8 CFGB;
1096 volatile u8 CFGC;
1097 volatile u8 CFGD;
1098
1099 volatile u16 DCFG; /* 0x7C */
1100 volatile u16 MCFG;
1101
1102 volatile u8 TBIST; /* 0x80 */
1103 volatile u8 RBIST;
1104 volatile u8 PMCPORT;
1105 volatile u8 STICKHW;
1106
1107 volatile u8 MIBCR; /* 0x84 */
1108 volatile u8 reserved_85;
1109 volatile u8 rev_id;
1110 volatile u8 PORSTS;
1111
1112 volatile u32 MIBData; /* 0x88 */
1113
1114 volatile u16 EEWrData;
1115
1116 volatile u8 reserved_8E;
1117 volatile u8 BPMDWr;
1118 volatile u8 BPCMD;
1119 volatile u8 BPMDRd;
1120
1121 volatile u8 EECHKSUM; /* 0x92 */
1122 volatile u8 EECSR;
1123
1124 volatile u16 EERdData; /* 0x94 */
1125 volatile u8 EADDR;
1126 volatile u8 EMBCMD;
1127
1128
1129 volatile u8 JMPSR0; /* 0x98 */
1130 volatile u8 JMPSR1;
1131 volatile u8 JMPSR2;
1132 volatile u8 JMPSR3;
1133 volatile u8 CHIPGSR; /* 0x9C */
1134 volatile u8 TESTCFG;
1135 volatile u8 DEBUG;
1136 volatile u8 CHIPGCR;
1137
1138 volatile u16 WOLCRSet; /* 0xA0 */
1139 volatile u8 PWCFGSet;
1140 volatile u8 WOLCFGSet;
1141
1142 volatile u16 WOLCRClr; /* 0xA4 */
1143 volatile u8 PWCFGCLR;
1144 volatile u8 WOLCFGClr;
1145
1146 volatile u16 WOLSRSet; /* 0xA8 */
1147 volatile u16 reserved_AA;
1148
1149 volatile u16 WOLSRClr; /* 0xAC */
1150 volatile u16 reserved_AE;
1151
1152 volatile u16 PatternCRC[8]; /* 0xB0 */
1153 volatile u32 ByteMask[4][4]; /* 0xC0 */
1154 } __attribute__ ((__packed__));
1155
1156
1157 enum hw_mib {
1158 HW_MIB_ifRxAllPkts = 0,
1159 HW_MIB_ifRxOkPkts,
1160 HW_MIB_ifTxOkPkts,
1161 HW_MIB_ifRxErrorPkts,
1162 HW_MIB_ifRxRuntOkPkt,
1163 HW_MIB_ifRxRuntErrPkt,
1164 HW_MIB_ifRx64Pkts,
1165 HW_MIB_ifTx64Pkts,
1166 HW_MIB_ifRx65To127Pkts,
1167 HW_MIB_ifTx65To127Pkts,
1168 HW_MIB_ifRx128To255Pkts,
1169 HW_MIB_ifTx128To255Pkts,
1170 HW_MIB_ifRx256To511Pkts,
1171 HW_MIB_ifTx256To511Pkts,
1172 HW_MIB_ifRx512To1023Pkts,
1173 HW_MIB_ifTx512To1023Pkts,
1174 HW_MIB_ifRx1024To1518Pkts,
1175 HW_MIB_ifTx1024To1518Pkts,
1176 HW_MIB_ifTxEtherCollisions,
1177 HW_MIB_ifRxPktCRCE,
1178 HW_MIB_ifRxJumboPkts,
1179 HW_MIB_ifTxJumboPkts,
1180 HW_MIB_ifRxMacControlFrames,
1181 HW_MIB_ifTxMacControlFrames,
1182 HW_MIB_ifRxPktFAE,
1183 HW_MIB_ifRxLongOkPkt,
1184 HW_MIB_ifRxLongPktErrPkt,
1185 HW_MIB_ifTXSQEErrors,
1186 HW_MIB_ifRxNobuf,
1187 HW_MIB_ifRxSymbolErrors,
1188 HW_MIB_ifInRangeLengthErrors,
1189 HW_MIB_ifLateCollisions,
1190 HW_MIB_SIZE
1191 };
1192
1193 enum chip_type {
1194 CHIP_TYPE_VT6110 = 1,
1195 };
1196
1197 struct velocity_info_tbl {
1198 enum chip_type chip_id;
1199 char *name;
1200 int io_size;
1201 int txqueue;
1202 u32 flags;
1203 };
1204
1205 static struct velocity_info_tbl *info;
1206
1207 #define mac_hw_mibs_init(regs) {\
1208 BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1209 BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\
1210 do {}\
1211 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\
1212 BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\
1213 }
1214
1215 #define mac_read_isr(regs) readl(&((regs)->ISR))
1216 #define mac_write_isr(regs, x) writel((x),&((regs)->ISR))
1217 #define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR))
1218
1219 #define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR));
1220 #define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr))
1221 #define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set))
1222
1223 #define mac_hw_mibs_read(regs, MIBs) {\
1224 int i;\
1225 BYTE_REG_BITS_ON(MIBCR_MPTRINI,&((regs)->MIBCR));\
1226 for (i=0;i<HW_MIB_SIZE;i++) {\
1227 (MIBs)[i]=readl(&((regs)->MIBData));\
1228 }\
1229 }
1230
1231 #define mac_set_dma_length(regs, n) {\
1232 BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\
1233 }
1234
1235 #define mac_set_rx_thresh(regs, n) {\
1236 BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\
1237 }
1238
1239 #define mac_rx_queue_run(regs) {\
1240 writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\
1241 }
1242
1243 #define mac_rx_queue_wake(regs) {\
1244 writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\
1245 }
1246
1247 #define mac_tx_queue_run(regs, n) {\
1248 writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\
1249 }
1250
1251 #define mac_tx_queue_wake(regs, n) {\
1252 writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\
1253 }
1254
1255 #define mac_eeprom_reload(regs) {\
1256 int i=0;\
1257 BYTE_REG_BITS_ON(EECSR_RELOAD,&((regs)->EECSR));\
1258 do {\
1259 udelay(10);\
1260 if (i++>0x1000) {\
1261 break;\
1262 }\
1263 }while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&((regs)->EECSR)));\
1264 }
1265
1266 enum velocity_cam_type {
1267 VELOCITY_VLAN_ID_CAM = 0,
1268 VELOCITY_MULTICAST_CAM
1269 };
1270
1271 /**
1272 * mac_get_cam_mask - Read a CAM mask
1273 * @regs: register block for this velocity
1274 * @mask: buffer to store mask
1275 * @cam_type: CAM to fetch
1276 *
1277 * Fetch the mask bits of the selected CAM and store them into the
1278 * provided mask buffer.
1279 */
1280
1281 static inline void mac_get_cam_mask(struct mac_regs *regs, u8 * mask,
1282 enum velocity_cam_type cam_type)
1283 {
1284 int i;
1285 /* Select CAM mask */
1286 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0,
1287 &regs->CAMCR);
1288
1289 if (cam_type == VELOCITY_VLAN_ID_CAM)
1290 writeb(CAMADDR_VCAMSL, &regs->CAMADDR);
1291 else
1292 writeb(0, &regs->CAMADDR);
1293
1294 /* read mask */
1295 for (i = 0; i < 8; i++)
1296 *mask++ = readb(&(regs->MARCAM[i]));
1297
1298 /* disable CAMEN */
1299 writeb(0, &regs->CAMADDR);
1300
1301 /* Select mar */
1302 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0,
1303 &regs->CAMCR);
1304
1305 }
1306
1307 /**
1308 * mac_set_cam_mask - Set a CAM mask
1309 * @regs: register block for this velocity
1310 * @mask: CAM mask to load
1311 * @cam_type: CAM to store
1312 *
1313 * Store a new mask into a CAM
1314 */
1315
1316 static inline void mac_set_cam_mask(struct mac_regs *regs, u8 * mask,
1317 enum velocity_cam_type cam_type)
1318 {
1319 int i;
1320 /* Select CAM mask */
1321 BYTE_REG_BITS_SET(CAMCR_PS_CAM_MASK, CAMCR_PS1 | CAMCR_PS0,
1322 &regs->CAMCR);
1323
1324 if (cam_type == VELOCITY_VLAN_ID_CAM)
1325 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL, &regs->CAMADDR);
1326 else
1327 writeb(CAMADDR_CAMEN, &regs->CAMADDR);
1328
1329 for (i = 0; i < 8; i++) {
1330 writeb(*mask++, &(regs->MARCAM[i]));
1331 }
1332 /* disable CAMEN */
1333 writeb(0, &regs->CAMADDR);
1334
1335 /* Select mar */
1336 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0,
1337 &regs->CAMCR);
1338 }
1339
1340 /**
1341 * mac_set_cam - set CAM data
1342 * @regs: register block of this velocity
1343 * @idx: Cam index
1344 * @addr: 2 or 6 bytes of CAM data
1345 * @cam_type: CAM to load
1346 *
1347 * Load an address or vlan tag into a CAM
1348 */
1349
1350 static inline void mac_set_cam(struct mac_regs *regs, int idx, u8 * addr,
1351 enum velocity_cam_type cam_type)
1352 {
1353 int i;
1354
1355 /* Select CAM mask */
1356 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0,
1357 &regs->CAMCR);
1358
1359 idx &= (64 - 1);
1360
1361 if (cam_type == VELOCITY_VLAN_ID_CAM)
1362 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx,
1363 &regs->CAMADDR);
1364 else
1365 writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
1366
1367 if (cam_type == VELOCITY_VLAN_ID_CAM)
1368 writew(*((u16 *) addr), &regs->MARCAM[0]);
1369 else {
1370 for (i = 0; i < 6; i++) {
1371 writeb(*addr++, &(regs->MARCAM[i]));
1372 }
1373 }
1374 BYTE_REG_BITS_ON(CAMCR_CAMWR, &regs->CAMCR);
1375
1376 udelay(10);
1377
1378 writeb(0, &regs->CAMADDR);
1379
1380 /* Select mar */
1381 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0,
1382 &regs->CAMCR);
1383 }
1384
1385 /**
1386 * mac_get_cam - fetch CAM data
1387 * @regs: register block of this velocity
1388 * @idx: Cam index
1389 * @addr: buffer to hold up to 6 bytes of CAM data
1390 * @cam_type: CAM to load
1391 *
1392 * Load an address or vlan tag from a CAM into the buffer provided by
1393 * the caller. VLAN tags are 2 bytes the address cam entries are 6.
1394 */
1395
1396 static inline void mac_get_cam(struct mac_regs *regs, int idx, u8 * addr,
1397 enum velocity_cam_type cam_type)
1398 {
1399 int i;
1400
1401 /* Select CAM mask */
1402 BYTE_REG_BITS_SET(CAMCR_PS_CAM_DATA, CAMCR_PS1 | CAMCR_PS0,
1403 &regs->CAMCR);
1404
1405 idx &= (64 - 1);
1406
1407 if (cam_type == VELOCITY_VLAN_ID_CAM)
1408 writeb(CAMADDR_CAMEN | CAMADDR_VCAMSL | idx,
1409 &regs->CAMADDR);
1410 else
1411 writeb(CAMADDR_CAMEN | idx, &regs->CAMADDR);
1412
1413 BYTE_REG_BITS_ON(CAMCR_CAMRD, &regs->CAMCR);
1414
1415 udelay(10);
1416
1417 if (cam_type == VELOCITY_VLAN_ID_CAM)
1418 *((u16 *) addr) = readw(&(regs->MARCAM[0]));
1419 else
1420 for (i = 0; i < 6; i++, addr++)
1421 *((u8 *) addr) = readb(&(regs->MARCAM[i]));
1422
1423 writeb(0, &regs->CAMADDR);
1424
1425 /* Select mar */
1426 BYTE_REG_BITS_SET(CAMCR_PS_MAR, CAMCR_PS1 | CAMCR_PS0,
1427 &regs->CAMCR);
1428 }
1429
1430 /**
1431 * mac_wol_reset - reset WOL after exiting low power
1432 * @regs: register block of this velocity
1433 *
1434 * Called after we drop out of wake on lan mode in order to
1435 * reset the Wake on lan features. This function doesn't restore
1436 * the rest of the logic from the result of sleep/wakeup
1437 */
1438
1439 inline static void mac_wol_reset(struct mac_regs *regs)
1440 {
1441
1442 /* Turn off SWPTAG right after leaving power mode */
1443 BYTE_REG_BITS_OFF(STICKHW_SWPTAG, &regs->STICKHW);
1444 /* clear sticky bits */
1445 BYTE_REG_BITS_OFF((STICKHW_DS1 | STICKHW_DS0), &regs->STICKHW);
1446
1447 BYTE_REG_BITS_OFF(CHIPGCR_FCGMII, &regs->CHIPGCR);
1448 BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, &regs->CHIPGCR);
1449 /* disable force PME-enable */
1450 writeb(WOLCFG_PMEOVR, &regs->WOLCFGClr);
1451 /* disable power-event config bit */
1452 writew(0xFFFF, &regs->WOLCRClr);
1453 /* clear power status */
1454 writew(0xFFFF, &regs->WOLSRClr);
1455 }
1456
1457
1458 /*
1459 * Header for WOL definitions. Used to compute hashes
1460 */
1461
1462 typedef u8 MCAM_ADDR[ETH_ALEN];
1463
1464 struct arp_packet {
1465 u8 dest_mac[ETH_ALEN];
1466 u8 src_mac[ETH_ALEN];
1467 u16 type;
1468 u16 ar_hrd;
1469 u16 ar_pro;
1470 u8 ar_hln;
1471 u8 ar_pln;
1472 u16 ar_op;
1473 u8 ar_sha[ETH_ALEN];
1474 u8 ar_sip[4];
1475 u8 ar_tha[ETH_ALEN];
1476 u8 ar_tip[4];
1477 } __attribute__ ((__packed__));
1478
1479 struct _magic_packet {
1480 u8 dest_mac[6];
1481 u8 src_mac[6];
1482 u16 type;
1483 u8 MAC[16][6];
1484 u8 password[6];
1485 } __attribute__ ((__packed__));
1486
1487 /*
1488 * Store for chip context when saving and restoring status. Not
1489 * all fields are saved/restored currently.
1490 */
1491
1492 struct velocity_context {
1493 u8 mac_reg[256];
1494 MCAM_ADDR cam_addr[MCAM_SIZE];
1495 u16 vcam[VCAM_SIZE];
1496 u32 cammask[2];
1497 u32 patcrc[2];
1498 u32 pattern[8];
1499 };
1500
1501
1502 /*
1503 * MII registers.
1504 */
1505
1506
1507 /*
1508 * Registers in the MII (offset unit is WORD)
1509 */
1510
1511 #define MII_REG_BMCR 0x00 // physical address
1512 #define MII_REG_BMSR 0x01 //
1513 #define MII_REG_PHYID1 0x02 // OUI
1514 #define MII_REG_PHYID2 0x03 // OUI + Module ID + REV ID
1515 #define MII_REG_ANAR 0x04 //
1516 #define MII_REG_ANLPAR 0x05 //
1517 #define MII_REG_G1000CR 0x09 //
1518 #define MII_REG_G1000SR 0x0A //
1519 #define MII_REG_MODCFG 0x10 //
1520 #define MII_REG_TCSR 0x16 //
1521 #define MII_REG_PLED 0x1B //
1522 // NS, MYSON only
1523 #define MII_REG_PCR 0x17 //
1524 // ESI only
1525 #define MII_REG_PCSR 0x17 //
1526 #define MII_REG_AUXCR 0x1C //
1527
1528 // Marvell 88E1000/88E1000S
1529 #define MII_REG_PSCR 0x10 // PHY specific control register
1530
1531 //
1532 // Bits in the BMCR register
1533 //
1534 #define BMCR_RESET 0x8000 //
1535 #define BMCR_LBK 0x4000 //
1536 #define BMCR_SPEED100 0x2000 //
1537 #define BMCR_AUTO 0x1000 //
1538 #define BMCR_PD 0x0800 //
1539 #define BMCR_ISO 0x0400 //
1540 #define BMCR_REAUTO 0x0200 //
1541 #define BMCR_FDX 0x0100 //
1542 #define BMCR_SPEED1G 0x0040 //
1543 //
1544 // Bits in the BMSR register
1545 //
1546 #define BMSR_AUTOCM 0x0020 //
1547 #define BMSR_LNK 0x0004 //
1548
1549 //
1550 // Bits in the ANAR register
1551 //
1552 #define ANAR_ASMDIR 0x0800 // Asymmetric PAUSE support
1553 #define ANAR_PAUSE 0x0400 // Symmetric PAUSE Support
1554 #define ANAR_T4 0x0200 //
1555 #define ANAR_TXFD 0x0100 //
1556 #define ANAR_TX 0x0080 //
1557 #define ANAR_10FD 0x0040 //
1558 #define ANAR_10 0x0020 //
1559 //
1560 // Bits in the ANLPAR register
1561 //
1562 #define ANLPAR_ASMDIR 0x0800 // Asymmetric PAUSE support
1563 #define ANLPAR_PAUSE 0x0400 // Symmetric PAUSE Support
1564 #define ANLPAR_T4 0x0200 //
1565 #define ANLPAR_TXFD 0x0100 //
1566 #define ANLPAR_TX 0x0080 //
1567 #define ANLPAR_10FD 0x0040 //
1568 #define ANLPAR_10 0x0020 //
1569
1570 //
1571 // Bits in the G1000CR register
1572 //
1573 #define G1000CR_1000FD 0x0200 // PHY is 1000-T Full-duplex capable
1574 #define G1000CR_1000 0x0100 // PHY is 1000-T Half-duplex capable
1575
1576 //
1577 // Bits in the G1000SR register
1578 //
1579 #define G1000SR_1000FD 0x0800 // LP PHY is 1000-T Full-duplex capable
1580 #define G1000SR_1000 0x0400 // LP PHY is 1000-T Half-duplex capable
1581
1582 #define TCSR_ECHODIS 0x2000 //
1583 #define AUXCR_MDPPS 0x0004 //
1584
1585 // Bits in the PLED register
1586 #define PLED_LALBE 0x0004 //
1587
1588 // Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h)
1589 #define PSCR_ACRSTX 0x0800 // Assert CRS on Transmit
1590
1591 #define PHYID_CICADA_CS8201 0x000FC410UL
1592 #define PHYID_VT3216_32BIT 0x000FC610UL
1593 #define PHYID_VT3216_64BIT 0x000FC600UL
1594 #define PHYID_MARVELL_1000 0x01410C50UL
1595 #define PHYID_MARVELL_1000S 0x01410C40UL
1596
1597 #define PHYID_REV_ID_MASK 0x0000000FUL
1598
1599 #define PHYID_GET_PHY_REV_ID(i) ((i) & PHYID_REV_ID_MASK)
1600 #define PHYID_GET_PHY_ID(i) ((i) & ~PHYID_REV_ID_MASK)
1601
1602 #define MII_REG_BITS_ON(x,i,p) do {\
1603 u16 w;\
1604 velocity_mii_read((p),(i),&(w));\
1605 (w)|=(x);\
1606 velocity_mii_write((p),(i),(w));\
1607 } while (0)
1608
1609 #define MII_REG_BITS_OFF(x,i,p) do {\
1610 u16 w;\
1611 velocity_mii_read((p),(i),&(w));\
1612 (w)&=(~(x));\
1613 velocity_mii_write((p),(i),(w));\
1614 } while (0)
1615
1616 #define MII_REG_BITS_IS_ON(x,i,p) ({\
1617 u16 w;\
1618 velocity_mii_read((p),(i),&(w));\
1619 ((int) ((w) & (x)));})
1620
1621 #define MII_GET_PHY_ID(p) ({\
1622 u32 id; \
1623 u16 id2; \
1624 u16 id1; \
1625 velocity_mii_read((p),MII_REG_PHYID2, &id2);\
1626 velocity_mii_read((p),MII_REG_PHYID1, &id1);\
1627 id = ( ( (u32)id2 ) << 16 ) | id1; \
1628 (id);})
1629
1630 #ifdef LINUX
1631 /*
1632 * Inline debug routine
1633 */
1634
1635
1636 enum velocity_msg_level {
1637 MSG_LEVEL_ERR = 0, //Errors that will cause abnormal operation.
1638 MSG_LEVEL_NOTICE = 1, //Some errors need users to be notified.
1639 MSG_LEVEL_INFO = 2, //Normal message.
1640 MSG_LEVEL_VERBOSE = 3, //Will report all trival errors.
1641 MSG_LEVEL_DEBUG = 4 //Only for debug purpose.
1642 };
1643
1644 #ifdef VELOCITY_DEBUG
1645 #define ASSERT(x) { \
1646 if (!(x)) { \
1647 printk(KERN_ERR "assertion %s failed: file %s line %d\n", #x,\
1648 __FUNCTION__, __LINE__);\
1649 BUG(); \
1650 }\
1651 }
1652 #define VELOCITY_DBG(p,args...) printk(p, ##args)
1653 #else
1654 #define ASSERT(x)
1655 #define VELOCITY_DBG(x)
1656 #endif
1657
1658 #define VELOCITY_PRT(l, p, args...) do {if (l<=msglevel) printf( p ,##args);} while (0)
1659
1660 #define VELOCITY_PRT_CAMMASK(p,t) {\
1661 int i;\
1662 if ((t)==VELOCITY_MULTICAST_CAM) {\
1663 for (i=0;i<(MCAM_SIZE/8);i++)\
1664 printk("%02X",(p)->mCAMmask[i]);\
1665 }\
1666 else {\
1667 for (i=0;i<(VCAM_SIZE/8);i++)\
1668 printk("%02X",(p)->vCAMmask[i]);\
1669 }\
1670 printk("\n");\
1671 }
1672
1673 #endif
1674
1675 #define VELOCITY_WOL_MAGIC 0x00000000UL
1676 #define VELOCITY_WOL_PHY 0x00000001UL
1677 #define VELOCITY_WOL_ARP 0x00000002UL
1678 #define VELOCITY_WOL_UCAST 0x00000004UL
1679 #define VELOCITY_WOL_BCAST 0x00000010UL
1680 #define VELOCITY_WOL_MCAST 0x00000020UL
1681 #define VELOCITY_WOL_MAGIC_SEC 0x00000040UL
1682
1683 /*
1684 * Flags for options
1685 */
1686
1687 #define VELOCITY_FLAGS_TAGGING 0x00000001UL
1688 #define VELOCITY_FLAGS_TX_CSUM 0x00000002UL
1689 #define VELOCITY_FLAGS_RX_CSUM 0x00000004UL
1690 #define VELOCITY_FLAGS_IP_ALIGN 0x00000008UL
1691 #define VELOCITY_FLAGS_VAL_PKT_LEN 0x00000010UL
1692
1693 #define VELOCITY_FLAGS_FLOW_CTRL 0x01000000UL
1694
1695 /*
1696 * Flags for driver status
1697 */
1698
1699 #define VELOCITY_FLAGS_OPENED 0x00010000UL
1700 #define VELOCITY_FLAGS_VMNS_CONNECTED 0x00020000UL
1701 #define VELOCITY_FLAGS_VMNS_COMMITTED 0x00040000UL
1702 #define VELOCITY_FLAGS_WOL_ENABLED 0x00080000UL
1703
1704 /*
1705 * Flags for MII status
1706 */
1707
1708 #define VELOCITY_LINK_FAIL 0x00000001UL
1709 #define VELOCITY_SPEED_10 0x00000002UL
1710 #define VELOCITY_SPEED_100 0x00000004UL
1711 #define VELOCITY_SPEED_1000 0x00000008UL
1712 #define VELOCITY_DUPLEX_FULL 0x00000010UL
1713 #define VELOCITY_AUTONEG_ENABLE 0x00000020UL
1714 #define VELOCITY_FORCED_BY_EEPROM 0x00000040UL
1715
1716 /*
1717 * For velocity_set_media_duplex
1718 */
1719
1720 #define VELOCITY_LINK_CHANGE 0x00000001UL
1721
1722 enum speed_opt {
1723 SPD_DPX_AUTO = 0,
1724 SPD_DPX_100_HALF = 1,
1725 SPD_DPX_100_FULL = 2,
1726 SPD_DPX_10_HALF = 3,
1727 SPD_DPX_10_FULL = 4
1728 };
1729
1730 enum velocity_init_type {
1731 VELOCITY_INIT_COLD = 0,
1732 VELOCITY_INIT_RESET,
1733 VELOCITY_INIT_WOL
1734 };
1735
1736 enum velocity_flow_cntl_type {
1737 FLOW_CNTL_DEFAULT = 1,
1738 FLOW_CNTL_TX,
1739 FLOW_CNTL_RX,
1740 FLOW_CNTL_TX_RX,
1741 FLOW_CNTL_DISABLE,
1742 };
1743
1744 struct velocity_opt {
1745 int numrx; /* Number of RX descriptors */
1746 int numtx; /* Number of TX descriptors */
1747 enum speed_opt spd_dpx; /* Media link mode */
1748 int vid; /* vlan id */
1749 int DMA_length; /* DMA length */
1750 int rx_thresh; /* RX_THRESH */
1751 int flow_cntl;
1752 int wol_opts; /* Wake on lan options */
1753 int td_int_count;
1754 int int_works;
1755 int rx_bandwidth_hi;
1756 int rx_bandwidth_lo;
1757 int rx_bandwidth_en;
1758 u32 flags;
1759 };
1760
1761 #define RX_DESC_MIN 4
1762 #define RX_DESC_MAX 255
1763 #define RX_DESC_DEF RX_DESC_MIN
1764
1765 #define TX_DESC_MIN 1
1766 #define TX_DESC_MAX 256
1767 #define TX_DESC_DEF TX_DESC_MIN
1768
1769 static struct velocity_info {
1770 // struct list_head list;
1771
1772 struct pci_device *pdev;
1773 // struct net_device *dev;
1774 // struct net_device_stats stats;
1775
1776 #ifdef CONFIG_PM
1777 u32 pci_state[16];
1778 #endif
1779
1780 // dma_addr_t rd_pool_dma;
1781 // dma_addr_t td_pool_dma[TX_QUEUE_NO];
1782
1783 // dma_addr_t tx_bufs_dma;
1784 u8 *tx_bufs;
1785
1786 u8 ip_addr[4];
1787 enum chip_type chip_id;
1788
1789 struct mac_regs *mac_regs;
1790 unsigned long memaddr;
1791 unsigned long ioaddr;
1792 u32 io_size;
1793
1794 u8 rev_id;
1795
1796 #define AVAIL_TD(p,q) ((p)->options.numtx-((p)->td_used[(q)]))
1797
1798 int num_txq;
1799
1800 volatile int td_used[TX_QUEUE_NO];
1801 int td_curr;
1802 int td_tail[TX_QUEUE_NO];
1803 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */
1804 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */
1805 unsigned char *tx_buffs;
1806 unsigned char *rx_buffs;
1807
1808 unsigned char *txb;
1809 unsigned char *rxb;
1810 struct tx_desc *td_rings;
1811 struct velocity_td_info *td_infos[TX_QUEUE_NO];
1812
1813 int rd_curr;
1814 int rd_dirty;
1815 u32 rd_filled;
1816 struct rx_desc *rd_ring;
1817 struct velocity_rd_info *rd_info; /* It's an array */
1818
1819 #define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx])
1820 u32 mib_counter[MAX_HW_MIB_COUNTER];
1821 struct velocity_opt options;
1822
1823 u32 int_mask;
1824
1825 u32 flags;
1826
1827 int rx_buf_sz;
1828 u32 mii_status;
1829 u32 phy_id;
1830 int multicast_limit;
1831
1832 u8 vCAMmask[(VCAM_SIZE / 8)];
1833 u8 mCAMmask[(MCAM_SIZE / 8)];
1834
1835 // spinlock_t lock;
1836
1837 int wol_opts;
1838 u8 wol_passwd[6];
1839
1840 struct velocity_context context;
1841
1842 u32 ticks;
1843 u32 rx_bytes;
1844
1845 } vptx;
1846
1847 static struct velocity_info *vptr;
1848
1849 #ifdef LINUX
1850 /**
1851 * velocity_get_ip - find an IP address for the device
1852 * @vptr: Velocity to query
1853 *
1854 * Dig out an IP address for this interface so that we can
1855 * configure wakeup with WOL for ARP. If there are multiple IP
1856 * addresses on this chain then we use the first - multi-IP WOL is not
1857 * supported.
1858 *
1859 * CHECK ME: locking
1860 */
1861
1862 inline static int velocity_get_ip(struct velocity_info *vptr)
1863 {
1864 struct in_device *in_dev = (struct in_device *) vptr->dev->ip_ptr;
1865 struct in_ifaddr *ifa;
1866
1867 if (in_dev != NULL) {
1868 ifa = (struct in_ifaddr *) in_dev->ifa_list;
1869 if (ifa != NULL) {
1870 memcpy(vptr->ip_addr, &ifa->ifa_address, 4);
1871 return 0;
1872 }
1873 }
1874 return -ENOENT;
1875 }
1876
1877 /**
1878 * velocity_update_hw_mibs - fetch MIB counters from chip
1879 * @vptr: velocity to update
1880 *
1881 * The velocity hardware keeps certain counters in the hardware
1882 * side. We need to read these when the user asks for statistics
1883 * or when they overflow (causing an interrupt). The read of the
1884 * statistic clears it, so we keep running master counters in user
1885 * space.
1886 */
1887
1888 static inline void velocity_update_hw_mibs(struct velocity_info *vptr)
1889 {
1890 u32 tmp;
1891 int i;
1892 BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR));
1893
1894 while (BYTE_REG_BITS_IS_ON
1895 (MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)));
1896
1897 BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR));
1898 for (i = 0; i < HW_MIB_SIZE; i++) {
1899 tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL;
1900 vptr->mib_counter[i] += tmp;
1901 }
1902 }
1903 #endif
1904 /**
1905 * init_flow_control_register - set up flow control
1906 * @vptr: velocity to configure
1907 *
1908 * Configure the flow control registers for this velocity device.
1909 */
1910
1911 static inline void init_flow_control_register(struct velocity_info *vptr)
1912 {
1913 struct mac_regs *regs = vptr->mac_regs;
1914
1915 /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1}
1916 depend on RD=64, and Turn on XNOEN in FlowCR1 */
1917 writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0),
1918 &regs->CR0Set);
1919 writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0),
1920 &regs->CR0Clr);
1921
1922 /* Set TxPauseTimer to 0xFFFF */
1923 writew(0xFFFF, &regs->tx_pause_timer);
1924
1925 /* Initialize RBRDU to Rx buffer count. */
1926 writew(vptr->options.numrx, &regs->RBRDU);
1927 }
1928
1929
1930 #endif
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