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[Drivers-r8169] Add support for newer rtl8169 variants from Hilko Bengen
[gpxe.git] / src / drivers / net / r8169.c
blob885f054ac4a556de29039602c168e092bebd5cfc
1 /**************************************************************************
2 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit
3 * Written 2003 by Timothy Legge <tlegge@rogers.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Portions of this code based on:
20 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver
21 * for Linux kernel 2.4.x.
22 *
23 * Written 2002 ShuChen <shuchen@realtek.com.tw>
24 * See Linux Driver for full information
25 *
26 * Linux Driver Versions:
27 * 1.27a, 10.02.2002
28 * RTL8169_VERSION "2.2" <2004/08/09>
29 *
30 * Thanks to:
31 * Jean Chen of RealTek Semiconductor Corp. for
32 * providing the evaluation NIC used to develop
33 * this driver. RealTek's support for Etherboot
34 * is appreciated.
35 *
36 * REVISION HISTORY:
37 * ================
38 *
39 * v1.0 11-26-2003 timlegge Initial port of Linux driver
40 * v1.5 01-17-2004 timlegge Initial driver output cleanup
41 * v1.6 03-27-2004 timlegge Additional Cleanup
42 * v1.7 11-22-2005 timlegge Update to RealTek Driver Version 2.2
43 *
44 * 03-19-2008 Hilko Bengen Cleanups and fixes for newer cards
45 * (successfully tested with 8110SC-d onboard NIC)
46 *
47 * Indent Options: indent -kr -i8
48 ***************************************************************************/
49
50 #include "etherboot.h"
51 #include "nic.h"
52 #include <gpxe/pci.h>
53 #include <gpxe/ethernet.h>
54 #include <gpxe/malloc.h>
55
56 #define drv_version "v1.7+"
57 #define drv_date "03-19-2008"
58
59 #define HZ 1000
60
61 static u32 ioaddr;
62
63 /* Condensed operations for readability. */
64 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
65 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
66
67 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
68
69 #undef RTL8169_DEBUG
70 #undef RTL8169_JUMBO_FRAME_SUPPORT
71 #undef RTL8169_HW_FLOW_CONTROL_SUPPORT
72
73
74 #undef RTL8169_IOCTL_SUPPORT
75 #undef RTL8169_DYNAMIC_CONTROL
76 #define RTL8169_USE_IO
77
78 #if 0
79 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
80 static int max_interrupt_work = 20;
81 #endif
82
83 #if 0
84 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
85 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
86 static int multicast_filter_limit = 32;
87 #endif
88
89 /* MAC address length*/
90 #define MAC_ADDR_LEN 6
91
92 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/
93 #define MAX_ETH_FRAME_SIZE 1536
94
95 #define TX_FIFO_THRESH 256 /* In bytes */
96
97 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
98 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
99 #define TX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
100 #define ETTh 0x3F /* 0x3F means NO threshold */
101
102 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
103 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */
104 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
105
106 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */
107 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */
108 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
109
110 #define RTL_MIN_IO_SIZE 0x80
111 #define TX_TIMEOUT (6*HZ)
112
113 #define RTL8169_TIMER_EXPIRE_TIME 100 //100
114
115 #define ETH_HDR_LEN 14
116 #define DEFAULT_MTU 1500
117 #define DEFAULT_RX_BUF_LEN 1536
118
119
120 #ifdef RTL8169_JUMBO_FRAME_SUPPORT
121 #define MAX_JUMBO_FRAME_MTU ( 10000 )
122 #define MAX_RX_SKBDATA_SIZE ( MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
123 #else
124 #define MAX_RX_SKBDATA_SIZE 1600
125 #endif //end #ifdef RTL8169_JUMBO_FRAME_SUPPORT
126
127 #ifdef RTL8169_USE_IO
128 #define RTL_W8(reg, val8) outb ((val8), ioaddr + (reg))
129 #define RTL_W16(reg, val16) outw ((val16), ioaddr + (reg))
130 #define RTL_W32(reg, val32) outl ((val32), ioaddr + (reg))
131 #define RTL_R8(reg) inb (ioaddr + (reg))
132 #define RTL_R16(reg) inw (ioaddr + (reg))
133 #define RTL_R32(reg) ((unsigned long) inl (ioaddr + (reg)))
134 #else
135 /* write/read MMIO register */
136 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
137 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
138 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
139 #define RTL_R8(reg) readb (ioaddr + (reg))
140 #define RTL_R16(reg) readw (ioaddr + (reg))
141 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
142 #endif
143
144 enum mac_version {
145 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
146 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
147 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
148 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
149 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
150 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
151 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
152 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
153 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
154 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
155 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
156 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
157 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
158 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
159 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
160 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
161 };
162
163 enum cfg_version {
164 RTL_CFG_0 = 0x00,
165 RTL_CFG_1,
166 RTL_CFG_2
167 };
168
169 static struct {
170 const char *name;
171 u8 mac_version; /* depend on RTL8169 docs */
172 u32 RxConfigMask; /* should clear the bits supported by this chip */
173 } rtl_chip_info[] = {
174 {"RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880}, // 8169
175 {"RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880}, // 8169S
176 {"RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880}, // 8110S
177 {"RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880}, // 8169SB
178 {"RTL8169sc/8110sc-d",RTL_GIGA_MAC_VER_05, 0xff7e1880}, // 8110SCd
179 {"RTL8169sc/8110sc-e",RTL_GIGA_MAC_VER_06, 0xff7e1880}, // 8110SCe
180 {"RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880}, // PCI-E
181 {"RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880}, // PCI-E
182 {"RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880}, // PCI-E 8139
183 {"RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880}, // PCI-E 8139
184 {"RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880}, // PCI-E 8139
185 {"RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880}, // PCI-E
186 {"RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880}, // PCI-E
187 {"RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880}, // PCI-E
188 {"RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880}, // PCI-E
189 {"RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880}, // PCI-E
190 };
191
192 enum RTL8169_registers {
193 MAC0 = 0x0, /* Ethernet hardware address. */
194 MAR0 = 0x8, /* Multicast filter. */
195 TxDescAddrLow = 0x20,
196 TxDescAddrHigh = 0x24,
197 TxHDescStartAddr = 0x28,
198 FLASH = 0x30,
199 ERSR = 0x36,
200 ChipCmd = 0x37,
201 TxPoll = 0x38,
202 IntrMask = 0x3C,
203 IntrStatus = 0x3E,
204 TxConfig = 0x40,
205 RxConfig = 0x44,
206 RxMissed = 0x4C,
207 Cfg9346 = 0x50,
208 Config0 = 0x51,
209 Config1 = 0x52,
210 Config2 = 0x53,
211 Config3 = 0x54,
212 Config4 = 0x55,
213 Config5 = 0x56,
214 MultiIntr = 0x5C,
215 PHYAR = 0x60,
216 TBICSR = 0x64,
217 TBI_ANAR = 0x68,
218 TBI_LPAR = 0x6A,
219 PHYstatus = 0x6C,
220 RxMaxSize = 0xda,
221 CPlusCmd = 0xe0,
222 IntrMitigate = 0xe2,
223 RxDescAddrLow = 0xe4,
224 RxDescAddrHigh = 0xe8,
225 ETThReg = 0xEC,
226 FuncEvent = 0xF0,
227 FuncEventMask = 0xF4,
228 FuncPresetState = 0xF8,
229 FuncForceEvent = 0xFC,
230 };
231
232 enum RTL8169_register_content {
233 /*InterruptStatusBits */
234 SYSErr = 0x8000,
235 PCSTimeout = 0x4000,
236 SWInt = 0x0100,
237 TxDescUnavail = 0x80,
238 RxFIFOOver = 0x40,
239 LinkChg = 0x20,
240 RxOverflow = 0x10,
241 TxErr = 0x08,
242 TxOK = 0x04,
243 RxErr = 0x02,
244 RxOK = 0x01,
245
246 /*RxStatusDesc */
247 RxRES = 0x00200000,
248 RxCRC = 0x00080000,
249 RxRUNT = 0x00100000,
250 RxRWT = 0x00400000,
251
252 /*ChipCmdBits */
253 CmdReset = 0x10,
254 CmdRxEnb = 0x08,
255 CmdTxEnb = 0x04,
256 RxBufEmpty = 0x01,
257
258 /*Cfg9346Bits */
259 Cfg9346_Lock = 0x00,
260 Cfg9346_Unlock = 0xC0,
261
262 /*rx_mode_bits */
263 AcceptErr = 0x20,
264 AcceptRunt = 0x10,
265 AcceptBroadcast = 0x08,
266 AcceptMulticast = 0x04,
267 AcceptMyPhys = 0x02,
268 AcceptAllPhys = 0x01,
269
270 /*RxConfigBits */
271 RxCfgFIFOShift = 13,
272 RxCfgDMAShift = 8,
273
274 /*TxConfigBits */
275 TxInterFrameGapShift = 24,
276 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
277
278 /*rtl8169_PHYstatus */
279 TBI_Enable = 0x80,
280 TxFlowCtrl = 0x40,
281 RxFlowCtrl = 0x20,
282 _1000bpsF = 0x10,
283 _100bps = 0x08,
284 _10bps = 0x04,
285 LinkStatus = 0x02,
286 FullDup = 0x01,
287
288 /*GIGABIT_PHY_registers */
289 PHY_CTRL_REG = 0,
290 PHY_STAT_REG = 1,
291 PHY_AUTO_NEGO_REG = 4,
292 PHY_1000_CTRL_REG = 9,
293
294 /*GIGABIT_PHY_REG_BIT */
295 PHY_Restart_Auto_Nego = 0x0200,
296 PHY_Enable_Auto_Nego = 0x1000,
297
298 /* PHY_STAT_REG = 1; */
299 PHY_Auto_Neco_Comp = 0x0020,
300
301 /* PHY_AUTO_NEGO_REG = 4; */
302 PHY_Cap_10_Half = 0x0020,
303 PHY_Cap_10_Full = 0x0040,
304 PHY_Cap_100_Half = 0x0080,
305 PHY_Cap_100_Full = 0x0100,
306
307 /* PHY_1000_CTRL_REG = 9; */
308 PHY_Cap_1000_Full = 0x0200,
309 PHY_Cap_1000_Half = 0x0100,
310
311 PHY_Cap_PAUSE = 0x0400,
312 PHY_Cap_ASYM_PAUSE = 0x0800,
313
314 PHY_Cap_Null = 0x0,
315
316 /*_MediaType*/
317 _10_Half = 0x01,
318 _10_Full = 0x02,
319 _100_Half = 0x04,
320 _100_Full = 0x08,
321 _1000_Full = 0x10,
322
323 /*_TBICSRBit*/
324 TBILinkOK = 0x02000000,
325 };
326
327 enum _DescStatusBit {
328 OWNbit = 0x80000000,
329 EORbit = 0x40000000,
330 FSbit = 0x20000000,
331 LSbit = 0x10000000,
332 };
333
334 struct TxDesc {
335 u32 status;
336 u32 vlan_tag;
337 u32 buf_addr;
338 u32 buf_Haddr;
339 };
340
341 struct RxDesc {
342 u32 status;
343 u32 vlan_tag;
344 u32 buf_addr;
345 u32 buf_Haddr;
346 };
347
348 /* The descriptors for this card are required to be aligned on 256
349 * byte boundaries. As the align attribute does not do more than 16
350 * bytes of alignment it requires some extra steps. Add 256 to the
351 * size of the array and the init_ring adjusts the alignment.
352 *
353 * UPDATE: This is no longer true; we can request arbitrary alignment.
354 */
355
356 /* Define the TX and RX Descriptors and Buffers */
357 #define __align_256 __attribute__ (( aligned ( 256 ) ))
358 struct {
359 struct TxDesc tx_ring[NUM_TX_DESC] __align_256;
360 unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE];
361 struct RxDesc rx_ring[NUM_RX_DESC] __align_256;
362 unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE];
363 } *r8169_bufs;
364 #define tx_ring r8169_bufs->tx_ring
365 #define rx_ring r8169_bufs->rx_ring
366 #define txb r8169_bufs->txb
367 #define rxb r8169_bufs->rxb
368
369 static struct rtl8169_private {
370 void *mmio_addr; /* memory map physical address */
371 int chipset;
372 int pcfg;
373 int mac_version;
374 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
375 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
376 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */
377 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */
378 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */
379 unsigned char *Tx_skbuff[NUM_TX_DESC];
380 } tpx;
381
382 static const u16 rtl8169_intr_mask =
383 LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
384 static const unsigned int rtl8169_rx_config =
385 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift) |
386 0x0000000E;
387
388 static void rtl8169_hw_phy_config(struct nic *nic __unused);
389 //static void rtl8169_hw_phy_reset(struct net_device *dev);
390
391 #define RTL8169_WRITE_GMII_REG_BIT( ioaddr, reg, bitnum, bitval )\
392 { \
393 int val; \
394 if( bitval == 1 ){ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) | (bitval<<bitnum) ) & 0xffff ; } \
395 else{ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) & (~(0x0001<<bitnum)) ) & 0xffff ; } \
396 RTL8169_WRITE_GMII_REG( ioaddr, reg, val ); \
397 }
398
399 //=================================================================
400 // PHYAR
401 // bit Symbol
402 // 31 Flag
403 // 30-21 reserved
404 // 20-16 5-bit GMII/MII register address
405 // 15-0 16-bit GMII/MII register data
406 //=================================================================
407 static void RTL8169_WRITE_GMII_REG(unsigned long ioaddr, int RegAddr, int value)
408 {
409 int i;
410
411 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
412 udelay(1000);
413
414 for (i = 2000; i > 0; i--) {
415 // Check if the RTL8169 has completed writing to the specified MII register
416 if (!(RTL_R32(PHYAR) & 0x80000000)) {
417 break;
418 } else {
419 udelay(100);
420 } // end of if( ! (RTL_R32(PHYAR)&0x80000000) )
421 } // end of for() loop
422 }
423
424 //=================================================================
425 static int RTL8169_READ_GMII_REG(unsigned long ioaddr, int RegAddr)
426 {
427 int i, value = -1;
428
429 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
430 udelay(1000);
431
432 for (i = 2000; i > 0; i--) {
433 // Check if the RTL8169 has completed retrieving data from the specified MII register
434 if (RTL_R32(PHYAR) & 0x80000000) {
435 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
436 break;
437 } else {
438 udelay(100);
439 } // end of if( RTL_R32(PHYAR) & 0x80000000 )
440 } // end of for() loop
441 return value;
442 }
443
444
445 #if 0
446 static void mdio_write(int RegAddr, int value)
447 {
448 int i;
449
450 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
451 udelay(1000);
452
453 for (i = 2000; i > 0; i--) {
454 /* Check if the RTL8169 has completed writing to the specified MII register */
455 if (!(RTL_R32(PHYAR) & 0x80000000)) {
456 break;
457 } else {
458 udelay(100);
459 }
460 }
461 }
462
463 static int mdio_read(int RegAddr)
464 {
465 int i, value = -1;
466
467 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
468 udelay(1000);
469
470 for (i = 2000; i > 0; i--) {
471 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
472 if (RTL_R32(PHYAR) & 0x80000000) {
473 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
474 break;
475 } else {
476 udelay(100);
477 }
478 }
479 return value;
480 }
481 #endif
482
483 static void rtl8169_get_mac_version( struct rtl8169_private *tp,
484 u32 ioaddr )
485 {
486 /*
487 * The driver currently handles the 8168Bf and the 8168Be identically
488 * but they can be identified more specifically through the test below
489 * if needed:
490 *
491 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
492 *
493 * Same thing for the 8101Eb and the 8101Ec:
494 *
495 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
496 */
497 const struct {
498 u32 mask;
499 u32 val;
500 int mac_version;
501 } mac_info[] = {
502 /* 8168B family. */
503 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
504 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
505 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
506 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
507 /* 8168B family. */
508 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
509 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
510 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
511 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
512 /* 8101 family. */
513 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
514 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
515 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
516 /* FIXME: where did these entries come from ? -- FR */
517 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
518 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
519 /* 8110 family. */
520 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
521 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
522 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
523 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
524 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
525 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
526 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
527 }, *p = mac_info;
528
529 unsigned long rv;
530
531 rv = (RTL_R32(TxConfig));
532
533 while ((rv & p->mask) != p->val)
534 p++;
535 tp->mac_version = p->mac_version;
536
537 if (p->mask == 0x00000000) {
538 DBG("unknown MAC (%08lx)\n", rv);
539 }
540 }
541
542 #define IORESOURCE_MEM 0x00000200
543
544 static int rtl8169_init_board(struct pci_device *pdev)
545 {
546 int i;
547 // unsigned long mmio_end, mmio_flags
548 unsigned long mmio_start, mmio_len;
549 struct rtl8169_private *tp = &tpx;
550
551 adjust_pci_device(pdev);
552
553 mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_1);
554 // mmio_end = pci_resource_end (pdev, 1);
555 // mmio_flags = pci_resource_flags (pdev, PCI_BASE_ADDRESS_1);
556 mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_1);
557
558 // make sure PCI base addr 1 is MMIO
559 // if (!(mmio_flags & IORESOURCE_MEM)) {
560 // printf ("region #1 not an MMIO resource, aborting\n");
561 // return 0;
562 // }
563
564 // check for weird/broken PCI region reporting
565 if (mmio_len < RTL_MIN_IO_SIZE) {
566 printf("Invalid PCI region size(s), aborting\n");
567 return 0;
568 }
569 #ifdef RTL8169_USE_IO
570 ioaddr = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
571 #else
572 // ioremap MMIO region
573 ioaddr = (unsigned long) ioremap(mmio_start, mmio_len);
574 if (ioaddr == 0) {
575 printk("cannot remap MMIO, aborting\n");
576 return 0;
577 }
578 #endif
579
580 tp->mmio_addr = (void*)ioaddr;
581 /* Soft reset the chip. */
582 RTL_W8(ChipCmd, CmdReset);
583
584 /* Check that the chip has finished the reset. */
585 for (i = 1000; i > 0; i--)
586 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
587 break;
588 else
589 udelay(10);
590
591 /* Identify chip attached to board */
592 rtl8169_get_mac_version( tp, ioaddr );
593
594 // rtl8169_print_mac_version(tp);
595
596 {
597 unsigned char val8 =
598 (unsigned char) (RTL8169_READ_GMII_REG(ioaddr, 3) &
599 0x000f);
600 if (val8 == 0x00) {
601 tp->pcfg = RTL_CFG_0;
602 } else if (val8 == 0x01) {
603 tp->pcfg = RTL_CFG_1;
604 } else if (val8 == 0x02) {
605 tp->pcfg = RTL_CFG_2;
606 } else {
607 tp->pcfg = RTL_CFG_2;
608 }
609 }
610
611 /* identify chip attached to board */
612
613 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--)
614 if (tp->mac_version == rtl_chip_info[i].mac_version) {
615 tp->chipset = i;
616 goto match;
617 }
618 /* if unknown chip, assume array element #0, original RTL-8169 in this case */
619 DBG ( "PCI device: unknown chip version, assuming RTL-8169\n" );
620 DBG ( "PCI device: TxConfig = %#lX\n", ( unsigned long ) RTL_R32 ( TxConfig ) );
621
622 tp->chipset = 0;
623 return 1;
624
625 match:
626 return 0;
627
628 }
629
630 /**************************************************************************
631 IRQ - Wait for a frame
632 ***************************************************************************/
633 static void r8169_irq(struct nic *nic __unused, irq_action_t action)
634 {
635 int intr_status = 0;
636 int interested = RxOverflow | RxFIFOOver | RxErr | RxOK;
637
638 switch (action) {
639 case DISABLE:
640 case ENABLE:
641 intr_status = RTL_R16(IntrStatus);
642 /* h/w no longer present (hotplug?) or major error,
643 bail */
644 if (intr_status == 0xFFFF)
645 break;
646
647 intr_status = intr_status & ~interested;
648 if (action == ENABLE)
649 intr_status = intr_status | interested;
650 RTL_W16(IntrMask, intr_status);
651 break;
652 case FORCE:
653 RTL_W8(TxPoll, (RTL_R8(TxPoll) | 0x01));
654 break;
655 }
656 }
657
658 /**************************************************************************
659 POLL - Wait for a frame
660 ***************************************************************************/
661 static int r8169_poll(struct nic *nic, int retrieve)
662 {
663 /* return true if there's an ethernet packet ready to read */
664 /* nic->packet should contain data on return */
665 /* nic->packetlen should contain length of data */
666 int cur_rx;
667 unsigned int intr_status = 0;
668 struct rtl8169_private *tp = &tpx;
669
670 cur_rx = tp->cur_rx;
671 if ((tp->RxDescArray[cur_rx].status & OWNbit) == 0) {
672 /* There is a packet ready */
673 DBG("r8169_poll(): packet ready\n");
674 if (!retrieve)
675 return 1;
676 intr_status = RTL_R16(IntrStatus);
677 /* h/w no longer present (hotplug?) or major error,
678 bail */
679 if (intr_status == 0xFFFF) {
680 DBG("r8169_poll(): unknown error\n");
681 return 0;
682 }
683 RTL_W16(IntrStatus, intr_status &
684 ~(RxFIFOOver | RxOverflow | RxOK));
685
686 if (!(tp->RxDescArray[cur_rx].status & RxRES)) {
687 nic->packetlen = (int) (tp->RxDescArray[cur_rx].
688 status & 0x00001FFF) - 4;
689 memcpy(nic->packet, tp->RxBufferRing[cur_rx],
690 nic->packetlen);
691 if (cur_rx == NUM_RX_DESC - 1)
692 tp->RxDescArray[cur_rx].status =
693 (OWNbit | EORbit) + RX_BUF_SIZE;
694 else
695 tp->RxDescArray[cur_rx].status =
696 OWNbit + RX_BUF_SIZE;
697 tp->RxDescArray[cur_rx].buf_addr =
698 virt_to_bus(tp->RxBufferRing[cur_rx]);
699 tp->RxDescArray[cur_rx].buf_Haddr = 0;
700 } else
701 printf("Error Rx");
702 /* FIXME: shouldn't I reset the status on an error */
703 cur_rx = (cur_rx + 1) % NUM_RX_DESC;
704 tp->cur_rx = cur_rx;
705 RTL_W16(IntrStatus, intr_status &
706 (RxFIFOOver | RxOverflow | RxOK));
707
708 return 1;
709
710 }
711 tp->cur_rx = cur_rx;
712 /* FIXME: There is no reason to do this as cur_rx did not change */
713
714 return (0); /* initially as this is called to flush the input */
715
716 }
717
718 /**************************************************************************
719 TRANSMIT - Transmit a frame
720 ***************************************************************************/
721 static void r8169_transmit(struct nic *nic, const char *d, /* Destination */
722 unsigned int t, /* Type */
723 unsigned int s, /* size */
724 const char *p)
725 { /* Packet */
726 /* send the packet to destination */
727
728 u16 nstype;
729 u32 to;
730 u8 *ptxb;
731 struct rtl8169_private *tp = &tpx;
732 int entry = tp->cur_tx % NUM_TX_DESC;
733
734 /* point to the current txb incase multiple tx_rings are used */
735 ptxb = tp->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
736 memcpy(ptxb, d, ETH_ALEN);
737 memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);
738 nstype = htons((u16) t);
739 memcpy(ptxb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
740 memcpy(ptxb + ETH_HLEN, p, s);
741 s += ETH_HLEN;
742 s &= 0x0FFF;
743 while (s < ETH_ZLEN)
744 ptxb[s++] = '\0';
745
746 tp->TxDescArray[entry].buf_addr = virt_to_bus(ptxb);
747 tp->TxDescArray[entry].buf_Haddr = 0;
748 if (entry != (NUM_TX_DESC - 1))
749 tp->TxDescArray[entry].status =
750 (OWNbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s :
751 ETH_ZLEN);
752 else
753 tp->TxDescArray[entry].status =
754 (OWNbit | EORbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s
755 : ETH_ZLEN);
756 RTL_W8(TxPoll, 0x40); /* set polling bit */
757
758 tp->cur_tx++;
759 to = currticks() + TX_TIMEOUT;
760 while ((tp->TxDescArray[entry].status & OWNbit) && (currticks() < to)); /* wait */
761
762 if (currticks() >= to) {
763 printf("TX Time Out");
764 }
765 }
766
767 static void rtl8169_set_rx_mode(struct nic *nic __unused)
768 {
769 u32 mc_filter[2]; /* Multicast hash filter */
770 int rx_mode;
771 u32 tmp = 0;
772 struct rtl8169_private *tp = &tpx;
773
774 /* IFF_ALLMULTI */
775 /* Too many to filter perfectly -- accept all multicasts. */
776 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
777 mc_filter[1] = mc_filter[0] = 0xffffffff;
778
779 tmp =
780 rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
781 rtl_chip_info[tp->chipset].
782 RxConfigMask);
783
784 RTL_W32(RxConfig, tmp);
785 RTL_W32(MAR0 + 0, mc_filter[0]);
786 RTL_W32(MAR0 + 4, mc_filter[1]);
787 }
788 static void rtl8169_hw_start(struct nic *nic)
789 {
790 u32 i;
791 struct rtl8169_private *tp = &tpx;
792
793 /* Soft reset the chip. */
794 RTL_W8(ChipCmd, CmdReset);
795
796 /* Check that the chip has finished the reset. */
797 for (i = 1000; i > 0; i--) {
798 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
799 break;
800 else
801 udelay(10);
802 }
803
804 RTL_W8(Cfg9346, Cfg9346_Unlock);
805 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
806 RTL_W8(ETThReg, ETTh);
807
808 /* For gigabit rtl8169 */
809 RTL_W16(RxMaxSize, RxPacketMaxSize);
810
811 /* Set Rx Config register */
812 i = rtl8169_rx_config | (RTL_R32(RxConfig) &
813 rtl_chip_info[tp->chipset].RxConfigMask);
814 RTL_W32(RxConfig, i);
815
816 /* Set DMA burst size and Interframe Gap Time */
817 RTL_W32(TxConfig,
818 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
819 TxInterFrameGapShift));
820
821
822 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd));
823
824 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || tp->mac_version == RTL_GIGA_MAC_VER_03) {
825 RTL_W16(CPlusCmd,
826 (RTL_R16(CPlusCmd) | (1 << 14) | (1 << 3)));
827 DBG
828 ("Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n");
829 } else {
830 RTL_W16(CPlusCmd, (RTL_R16(CPlusCmd) | (1 << 3)));
831 DBG("Set MAC Reg C+CR Offset 0xE0: bit-3.\n");
832 }
833
834 {
835 //RTL_W16(IntrMitigate, 0x1517);
836 //RTL_W16(IntrMitigate, 0x152a);
837 //RTL_W16(IntrMitigate, 0x282a);
838 RTL_W16(IntrMitigate, 0x0000);
839 }
840
841 tp->cur_rx = 0;
842
843 RTL_W32(TxDescAddrLow, virt_to_le32desc(tp->TxDescArray));
844 RTL_W32(TxDescAddrHigh, virt_to_le32desc(NULL));
845 RTL_W32(RxDescAddrLow, virt_to_le32desc(tp->RxDescArray));
846 RTL_W32(RxDescAddrHigh, virt_to_le32desc(NULL));
847 RTL_W8(Cfg9346, Cfg9346_Lock);
848 udelay(10);
849
850 RTL_W32(RxMissed, 0);
851
852 rtl8169_set_rx_mode(nic);
853
854 /* no early-rx interrupts */
855 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
856
857 RTL_W16(IntrMask, rtl8169_intr_mask);
858
859 }
860
861 static void rtl8169_init_ring(struct nic *nic __unused)
862 {
863 int i;
864 struct rtl8169_private *tp = &tpx;
865
866 tp->cur_rx = 0;
867 tp->cur_tx = 0;
868 memset(tp->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
869 memset(tp->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
870
871 for (i = 0; i < NUM_TX_DESC; i++) {
872 tp->Tx_skbuff[i] = &txb[i];
873 }
874
875 for (i = 0; i < NUM_RX_DESC; i++) {
876 if (i == (NUM_RX_DESC - 1))
877 tp->RxDescArray[i].status =
878 (OWNbit | EORbit) | RX_BUF_SIZE;
879 else
880 tp->RxDescArray[i].status = OWNbit | RX_BUF_SIZE;
881
882 tp->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
883 tp->RxDescArray[i].buf_addr =
884 virt_to_bus(tp->RxBufferRing[i]);
885 tp->RxDescArray[i].buf_Haddr = 0;
886 }
887 }
888
889 /**************************************************************************
890 RESET - Finish setting up the ethernet interface
891 ***************************************************************************/
892 static void r8169_reset(struct nic *nic)
893 {
894 int i;
895 struct rtl8169_private *tp = &tpx;
896
897 tp->TxDescArray = tx_ring;
898 tp->RxDescArray = rx_ring;
899
900 rtl8169_init_ring(nic);
901 rtl8169_hw_start(nic);
902 /* Construct a perfect filter frame with the mac address as first match
903 * and broadcast for all others */
904 for (i = 0; i < 192; i++)
905 txb[i] = 0xFF;
906
907 txb[0] = nic->node_addr[0];
908 txb[1] = nic->node_addr[1];
909 txb[2] = nic->node_addr[2];
910 txb[3] = nic->node_addr[3];
911 txb[4] = nic->node_addr[4];
912 txb[5] = nic->node_addr[5];
913 }
914
915 /**************************************************************************
916 DISABLE - Turn off ethernet interface
917 ***************************************************************************/
918 static void r8169_disable ( struct nic *nic __unused ) {
919 int i;
920 struct rtl8169_private *tp = &tpx;
921
922 /* Stop the chip's Tx and Rx DMA processes. */
923 RTL_W8(ChipCmd, 0x00);
924
925 /* Disable interrupts by clearing the interrupt mask. */
926 RTL_W16(IntrMask, 0x0000);
927
928 RTL_W32(RxMissed, 0);
929
930 tp->TxDescArray = NULL;
931 tp->RxDescArray = NULL;
932 for (i = 0; i < NUM_RX_DESC; i++) {
933 tp->RxBufferRing[i] = NULL;
934 }
935 }
936
937 static struct nic_operations r8169_operations = {
938 .connect = dummy_connect,
939 .poll = r8169_poll,
940 .transmit = r8169_transmit,
941 .irq = r8169_irq,
942
943 };
944
945 static struct pci_device_id r8169_nics[] = {
946 PCI_ROM(0x10ec, 0x8169, "r8169", "RealTek RTL8169 Gigabit Ethernet"),
947 PCI_ROM(0x16ec, 0x0116, "usr-r8169", "US Robotics RTL8169 Gigabit Ethernet"),
948 PCI_ROM(0x1186, 0x4300, "dlink-r8169", "D-Link RTL8169 Gigabit Ethernet"),
949 PCI_ROM(0x1737, 0x1032, "linksys-r8169", "Linksys RTL8169 Gigabit Ethernet"),
950 PCI_ROM(0x10ec, 0x8129, "r8169-8129", "RealTek RT8129 Fast Ethernet Adapter"),
951 PCI_ROM(0x10ec, 0x8136, "r8169-8101e", "RealTek RTL8101E PCI Express Fast Ethernet controller"),
952 PCI_ROM(0x10ec, 0x8167, "r8169-8110sc/8169sc", "RealTek RTL-8110SC/8169SC Gigabit Ethernet"),
953 PCI_ROM(0x10ec, 0x8168, "r8169-8168b", "RealTek RTL8111/8168B PCI Express Gigabit Ethernet controller"),
954 };
955
956 PCI_DRIVER ( r8169_driver, r8169_nics, PCI_NO_CLASS );
957
958 /**************************************************************************
959 PROBE - Look for an adapter, this routine's visible to the outside
960 ***************************************************************************/
961
962 #define board_found 1
963 #define valid_link 0
964 static int r8169_probe ( struct nic *nic, struct pci_device *pci ) {
965
966 static int board_idx = -1;
967 static int printed_version = 0;
968 struct rtl8169_private *tp = &tpx;
969 int i, rc;
970 int option = -1, Cap10_100 = 0, Cap1000 = 0;
971
972 printf ( "r8169.c: Found %s, Vendor=%hX Device=%hX\n",
973 pci->driver_name, pci->vendor, pci->device );
974
975 board_idx++;
976
977 printed_version = 1;
978
979 /* Quick and very dirty hack to get r8169 driver working
980 * again, pre-rewrite
981 */
982 if ( ! r8169_bufs )
983 r8169_bufs = malloc_dma ( sizeof ( *r8169_bufs ), 256 );
984 if ( ! r8169_bufs )
985 return 0;
986 memset ( r8169_bufs, 0, sizeof ( *r8169_bufs ) );
987
988 rc = rtl8169_init_board(pci); /* Return code is meaningless */
989
990 /* Get MAC address. FIXME: read EEPROM */
991 for (i = 0; i < MAC_ADDR_LEN; i++)
992 nic->node_addr[i] = RTL_R8(MAC0 + i);
993
994 DBG ( "%s: Identified chip type is '%s'.\n", pci->driver_name,
995 rtl_chip_info[tp->chipset].name );
996
997 /* Print out some hardware info */
998 DBG ( "%s: %s at ioaddr %#hx, ", pci->driver_name, eth_ntoa ( nic->node_addr ),
999 (unsigned int) ioaddr );
1000
1001 /* Config PHY */
1002 rtl8169_hw_phy_config(nic);
1003
1004 DBG("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1005 RTL_W8(0x82, 0x01);
1006
1007 pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0x40);
1008
1009 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1010 pci_write_config_byte(pci, PCI_CACHE_LINE_SIZE, 0x08);
1011
1012 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1013 DBG("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1014 RTL_W8(0x82, 0x01);
1015 DBG("Set PHY Reg 0x0bh = 0x00h\n");
1016 RTL8169_WRITE_GMII_REG(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1017 }
1018
1019 r8169_reset(nic);
1020
1021 /* if TBI is not endbled */
1022 if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
1023 int val = RTL8169_READ_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG);
1024
1025 #ifdef RTL8169_HW_FLOW_CONTROL_SUPPORT
1026 val |= PHY_Cap_PAUSE | PHY_Cap_ASYM_PAUSE;
1027 #endif //end #define RTL8169_HW_FLOW_CONTROL_SUPPORT
1028
1029 /* Force RTL8169 in 10/100/1000 Full/Half mode. */
1030 if (option > 0) {
1031 printf(" Force-mode Enabled.\n");
1032 Cap10_100 = 0, Cap1000 = 0;
1033 switch (option) {
1034 case _10_Half:
1035 Cap10_100 = PHY_Cap_10_Half;
1036 Cap1000 = PHY_Cap_Null;
1037 break;
1038 case _10_Full:
1039 Cap10_100 = PHY_Cap_10_Full;
1040 Cap1000 = PHY_Cap_Null;
1041 break;
1042 case _100_Half:
1043 Cap10_100 = PHY_Cap_100_Half;
1044 Cap1000 = PHY_Cap_Null;
1045 break;
1046 case _100_Full:
1047 Cap10_100 = PHY_Cap_100_Full;
1048 Cap1000 = PHY_Cap_Null;
1049 break;
1050 case _1000_Full:
1051 Cap10_100 = PHY_Cap_Null;
1052 Cap1000 = PHY_Cap_1000_Full;
1053 break;
1054 default:
1055 break;
1056 }
1057 RTL8169_WRITE_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0xC1F)); //leave PHY_AUTO_NEGO_REG bit4:0 unchanged
1058 RTL8169_WRITE_GMII_REG(ioaddr, PHY_1000_CTRL_REG,
1059 Cap1000);
1060 } else {
1061 DBG ( "%s: Auto-negotiation Enabled.\n", pci->driver_name );
1062
1063 // enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
1064 RTL8169_WRITE_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG,
1065 PHY_Cap_10_Half |
1066 PHY_Cap_10_Full |
1067 PHY_Cap_100_Half |
1068 PHY_Cap_100_Full | (val &
1069 0xC1F));
1070
1071 // enable 1000 Full Mode
1072 // RTL8169_WRITE_GMII_REG( ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full );
1073 RTL8169_WRITE_GMII_REG(ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full | PHY_Cap_1000_Half); //rtl8168
1074
1075 } // end of if( option > 0 )
1076
1077 // Enable auto-negotiation and restart auto-nigotiation
1078 RTL8169_WRITE_GMII_REG(ioaddr, PHY_CTRL_REG,
1079 PHY_Enable_Auto_Nego |
1080 PHY_Restart_Auto_Nego);
1081 udelay(100);
1082
1083 // wait for auto-negotiation process
1084 for (i = 10000; i > 0; i--) {
1085 //check if auto-negotiation complete
1086 if (RTL8169_READ_GMII_REG(ioaddr, PHY_STAT_REG) &
1087 PHY_Auto_Neco_Comp) {
1088 udelay(100);
1089 option = RTL_R8(PHYstatus);
1090 if (option & _1000bpsF) {
1091 printf
1092 ("1000Mbps Full-duplex operation.\n");
1093 } else {
1094 printf
1095 ("%sMbps %s-duplex operation.\n",
1096 (option & _100bps) ? "100" :
1097 "10",
1098 (option & FullDup) ? "Full" :
1099 "Half");
1100 }
1101 break;
1102 } else {
1103 udelay(100);
1104 } // end of if( RTL8169_READ_GMII_REG(ioaddr, 1) & 0x20 )
1105 } // end for-loop to wait for auto-negotiation process
1106
1107
1108 } else {
1109 udelay(100);
1110 printf
1111 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n",
1112 pci->driver_name,
1113 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed");
1114
1115 }
1116
1117 r8169_reset(nic);
1118
1119 /* point to NIC specific routines */
1120 nic->nic_op = &r8169_operations;
1121
1122 nic->irqno = pci->irq;
1123 nic->ioaddr = ioaddr;
1124
1125 return 1;
1126 }
1127
1128 //======================================================================================================
1129 /*
1130 static void rtl8169_hw_PHY_reset(struct nic *nic __unused)
1131 {
1132 int val, phy_reset_expiretime = 50;
1133 struct rtl8169_private *priv = dev->priv;
1134 unsigned long ioaddr = priv->ioaddr;
1135
1136 DBG("%s: Reset RTL8169s PHY\n", dev->name);
1137
1138 val = ( RTL8169_READ_GMII_REG( ioaddr, 0 ) | 0x8000 ) & 0xffff;
1139 RTL8169_WRITE_GMII_REG( ioaddr, 0, val );
1140
1141 do //waiting for phy reset
1142 {
1143 if( RTL8169_READ_GMII_REG( ioaddr, 0 ) & 0x8000 ){
1144 phy_reset_expiretime --;
1145 udelay(100);
1146 }
1147 else{
1148 break;
1149 }
1150 }while( phy_reset_expiretime >= 0 );
1151
1152 assert( phy_reset_expiretime > 0 );
1153 }
1154
1155 */
1156
1157 struct phy_reg {
1158 u16 reg;
1159 u16 val;
1160 };
1161
1162 static void rtl_phy_write(void *ioaddr, struct phy_reg *regs, int len)
1163 {
1164 while (len-- > 0) {
1165 RTL8169_WRITE_GMII_REG((u32)ioaddr, regs->reg, regs->val);
1166 regs++;
1167 }
1168 }
1169
1170 static void rtl8169s_hw_phy_config(void *ioaddr)
1171 {
1172 struct {
1173 u16 regs[5]; /* Beware of bit-sign propagation */
1174 } phy_magic[5] = { {
1175 { 0x0000, //w 4 15 12 0
1176 0x00a1, //w 3 15 0 00a1
1177 0x0008, //w 2 15 0 0008
1178 0x1020, //w 1 15 0 1020
1179 0x1000 } },{ //w 0 15 0 1000
1180 { 0x7000, //w 4 15 12 7
1181 0xff41, //w 3 15 0 ff41
1182 0xde60, //w 2 15 0 de60
1183 0x0140, //w 1 15 0 0140
1184 0x0077 } },{ //w 0 15 0 0077
1185 { 0xa000, //w 4 15 12 a
1186 0xdf01, //w 3 15 0 df01
1187 0xdf20, //w 2 15 0 df20
1188 0xff95, //w 1 15 0 ff95
1189 0xfa00 } },{ //w 0 15 0 fa00
1190 { 0xb000, //w 4 15 12 b
1191 0xff41, //w 3 15 0 ff41
1192 0xde20, //w 2 15 0 de20
1193 0x0140, //w 1 15 0 0140
1194 0x00bb } },{ //w 0 15 0 00bb
1195 { 0xf000, //w 4 15 12 f
1196 0xdf01, //w 3 15 0 df01
1197 0xdf20, //w 2 15 0 df20
1198 0xff95, //w 1 15 0 ff95
1199 0xbf00 } //w 0 15 0 bf00
1200 }
1201 }, *p = phy_magic;
1202 unsigned int i;
1203
1204 RTL8169_WRITE_GMII_REG((u32)ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1205 RTL8169_WRITE_GMII_REG((u32)ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1206 RTL8169_WRITE_GMII_REG((u32)ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1207 RTL8169_WRITE_GMII_REG_BIT((u32)ioaddr, 4, 11, 0); //w 4 11 11 0
1208
1209 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1210 int val, pos = 4;
1211
1212 val = (RTL8169_READ_GMII_REG((u32)ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1213 RTL8169_WRITE_GMII_REG((u32)ioaddr, pos, val);
1214 while (--pos >= 0)
1215 RTL8169_WRITE_GMII_REG((u32)ioaddr, pos, p->regs[4 - pos] & 0xffff);
1216 RTL8169_WRITE_GMII_REG_BIT((u32)ioaddr, 4, 11, 1); //w 4 11 11 1
1217 RTL8169_WRITE_GMII_REG_BIT((u32)ioaddr, 4, 11, 0); //w 4 11 11 0
1218 }
1219 RTL8169_WRITE_GMII_REG((u32)ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1220 }
1221
1222 static void rtl8169sb_hw_phy_config(void *ioaddr)
1223 {
1224 struct phy_reg phy_reg_init[] = {
1225 { 0x1f, 0x0002 },
1226 { 0x01, 0x90d0 },
1227 { 0x1f, 0x0000 }
1228 };
1229
1230 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1231 }
1232
1233 static void rtl8168cp_hw_phy_config(void *ioaddr)
1234 {
1235 struct phy_reg phy_reg_init[] = {
1236 { 0x1f, 0x0000 },
1237 { 0x1d, 0x0f00 },
1238 { 0x1f, 0x0002 },
1239 { 0x0c, 0x1ec8 },
1240 { 0x1f, 0x0000 }
1241 };
1242
1243 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1244 }
1245
1246 static void rtl8168c_hw_phy_config(void *ioaddr)
1247 {
1248 struct phy_reg phy_reg_init[] = {
1249 { 0x1f, 0x0001 },
1250 { 0x12, 0x2300 },
1251 { 0x1f, 0x0002 },
1252 { 0x00, 0x88d4 },
1253 { 0x01, 0x82b1 },
1254 { 0x03, 0x7002 },
1255 { 0x08, 0x9e30 },
1256 { 0x09, 0x01f0 },
1257 { 0x0a, 0x5500 },
1258 { 0x0c, 0x00c8 },
1259 { 0x1f, 0x0003 },
1260 { 0x12, 0xc096 },
1261 { 0x16, 0x000a },
1262 { 0x1f, 0x0000 }
1263 };
1264
1265 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1266 }
1267
1268 static void rtl8168cx_hw_phy_config(void *ioaddr)
1269 {
1270 struct phy_reg phy_reg_init[] = {
1271 { 0x1f, 0x0000 },
1272 { 0x12, 0x2300 },
1273 { 0x1f, 0x0003 },
1274 { 0x16, 0x0f0a },
1275 { 0x1f, 0x0000 },
1276 { 0x1f, 0x0002 },
1277 { 0x0c, 0x7eb8 },
1278 { 0x1f, 0x0000 }
1279 };
1280
1281 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1282 }
1283
1284 static void rtl8169_hw_phy_config(struct nic *nic __unused)
1285 {
1286 struct rtl8169_private *tp = &tpx;
1287 void *ioaddr = tp->mmio_addr;
1288 DBG("rtl8169_hw_phy_config(): card at addr=0x%lx: priv->mac_version=%d, priv->pcfg=%d\n", (unsigned long) ioaddr, tp->mac_version, tp->pcfg);
1289
1290 switch (tp->mac_version) {
1291 case RTL_GIGA_MAC_VER_01:
1292 break;
1293 case RTL_GIGA_MAC_VER_02:
1294 case RTL_GIGA_MAC_VER_03:
1295 rtl8169s_hw_phy_config(ioaddr);
1296 break;
1297 case RTL_GIGA_MAC_VER_04:
1298 rtl8169sb_hw_phy_config(ioaddr);
1299 break;
1300 case RTL_GIGA_MAC_VER_18:
1301 rtl8168cp_hw_phy_config(ioaddr);
1302 break;
1303 case RTL_GIGA_MAC_VER_19:
1304 rtl8168c_hw_phy_config(ioaddr);
1305 break;
1306 case RTL_GIGA_MAC_VER_20:
1307 rtl8168cx_hw_phy_config(ioaddr);
1308 break;
1309 default:
1310 break;
1311 }
1312 }
1313
1314 DRIVER ( "r8169/PCI", nic_driver, pci_driver, r8169_driver,
1315 r8169_probe, r8169_disable );
1316
1317 /*
1318 * Local variables:
1319 * c-basic-offset: 8
1320 * c-indent-level: 8
1321 * tab-width: 8
1322 * End:
1323 */
gPXE - free pxe roms