| commit | 7296f1f21c442e0781e7c3efe1f1a1005cf3e385 | |
| author | Joshua Oreman <oremanj@rwcr.net> | |
| Fri, 16 Oct 2009 23:27:43 +0000 (16 19:27 -0400) | ||
| committer | Marty Connor <mdc@etherboot.org> | |
| Sat, 17 Oct 2009 00:25:17 +0000 (16 20:25 -0400) | ||
| tree | d10b9854d8a7a41c6f23ddb965284d2e78ab64a9 | treesnapshot (tar.gz zip) |
| parent | 489bd2f396e62e2ec1139da93e242017a7f6e9f5 | commitdiff |
[ath5k] Save proper cacheline size when fixing PCI configuration
Some BIOSes set the PCI cacheline size to zero for the card; the ath5k
driver fixes it to a reasonable in PCI config space, but failed to
correct the internal value it had already read. This resulted in
divide-by-zero errors when cacheline-aligning various data structures.
Fix by setting the internal cachelsz to a sane value at the same time
as we write that value to PCI config space.
Signed-off-by: Marty Connor <mdc@etherboot.org>
Some BIOSes set the PCI cacheline size to zero for the card; the ath5k
driver fixes it to a reasonable in PCI config space, but failed to
correct the internal value it had already read. This resulted in
divide-by-zero errors when cacheline-aligning various data structures.
Fix by setting the internal cachelsz to a sane value at the same time
as we write that value to PCI config space.
Signed-off-by: Marty Connor <mdc@etherboot.org>
| src/drivers/net/ath5k/ath5k.c | diffblobblamehistory |