[ath5k] Save proper cacheline size when fixing PCI configuration
treed10b9854d8a7a41c6f23ddb965284d2e78ab64a9
-rw-r--r-- 17982 COPYING
-rw-r--r-- 908 COPYRIGHTS
-rw-r--r-- 342 LOG
-rw-r--r-- 1650 README
drwxr-xr-x - contrib
drwxr-xr-x - src