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Make gpxe build.
[gpxe/hramrach.git] / src / drivers / net / atl1e.c
bloba9c795d46e1d2702b0a3ecf9d030ff7920c8a90b
1 /*
2 * Copyright(c) 2007 Atheros Corporation. All rights reserved.
3 *
4 * Derived from Intel e1000 driver
5 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6 *
7 * Modified for gPXE, October 2009 by Joshua Oreman <oremanj@rwcr.net>.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 */
23
24 FILE_LICENCE ( GPL2_OR_LATER );
25
26 #include "atl1e.h"
27
28 /* User-tweakable parameters: */
29 #define TX_DESC_COUNT 32 /* TX descriptors, minimum 32 */
30 #define RX_MEM_SIZE 8192 /* RX area size, minimum 8kb */
31 #define MAX_FRAME_SIZE 1500 /* Maximum MTU supported, minimum 1500 */
32
33 /* Arcane parameters: */
34 #define PREAMBLE_LEN 7
35 #define RX_JUMBO_THRESH ((MAX_FRAME_SIZE + ETH_HLEN + \
36 VLAN_HLEN + ETH_FCS_LEN + 7) >> 3)
37 #define IMT_VAL 100 /* interrupt moderator timer, us */
38 #define ICT_VAL 50000 /* interrupt clear timer, us */
39 #define SMB_TIMER 200000
40 #define RRD_THRESH 1 /* packets to queue before interrupt */
41 #define TPD_BURST 5
42 #define TPD_THRESH (TX_DESC_COUNT / 2)
43 #define RX_COUNT_DOWN 4
44 #define TX_COUNT_DOWN (IMT_VAL * 4 / 3)
45 #define DMAR_DLY_CNT 15
46 #define DMAW_DLY_CNT 4
47
48 #define PCI_DEVICE_ID_ATTANSIC_L1E 0x1026
49
50 /*
51 * atl1e_pci_tbl - PCI Device ID Table
52 *
53 * Wildcard entries (PCI_ANY_ID) should come last
54 * Last entry must be all 0s
55 *
56 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
57 * Class, Class Mask, private data (not used) }
58 */
59 static struct pci_device_id atl1e_pci_tbl[] = {
60 PCI_ROM(0x1969, 0x1026, "atl1e_26", "Attansic L1E 0x1026", 0),
61 PCI_ROM(0x1969, 0x1066, "atl1e_66", "Attansic L1E 0x1066", 0),
62 };
63
64 static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter);
65
66 static const u16
67 atl1e_rx_page_vld_regs[AT_PAGE_NUM_PER_QUEUE] =
68 {
69 REG_HOST_RXF0_PAGE0_VLD, REG_HOST_RXF0_PAGE1_VLD
70 };
71
72 static const u16
73 atl1e_rx_page_lo_addr_regs[AT_PAGE_NUM_PER_QUEUE] =
74 {
75 REG_HOST_RXF0_PAGE0_LO, REG_HOST_RXF0_PAGE1_LO
76 };
77
78 static const u16
79 atl1e_rx_page_write_offset_regs[AT_PAGE_NUM_PER_QUEUE] =
80 {
81 REG_HOST_RXF0_MB0_LO, REG_HOST_RXF0_MB1_LO
82 };
83
84 static const u16 atl1e_pay_load_size[] = {
85 128, 256, 512, 1024, 2048, 4096,
86 };
87
88 /*
89 * atl1e_irq_enable - Enable default interrupt generation settings
90 * @adapter: board private structure
91 */
92 static inline void atl1e_irq_enable(struct atl1e_adapter *adapter)
93 {
94 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
95 AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
96 AT_WRITE_FLUSH(&adapter->hw);
97 }
98
99 /*
100 * atl1e_irq_disable - Mask off interrupt generation on the NIC
101 * @adapter: board private structure
102 */
103 static inline void atl1e_irq_disable(struct atl1e_adapter *adapter)
104 {
105 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
106 AT_WRITE_FLUSH(&adapter->hw);
107 }
108
109 /*
110 * atl1e_irq_reset - reset interrupt confiure on the NIC
111 * @adapter: board private structure
112 */
113 static inline void atl1e_irq_reset(struct atl1e_adapter *adapter)
114 {
115 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
116 AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
117 AT_WRITE_FLUSH(&adapter->hw);
118 }
119
120 static void atl1e_reset(struct atl1e_adapter *adapter)
121 {
122 atl1e_down(adapter);
123 atl1e_up(adapter);
124 }
125
126 static int atl1e_check_link(struct atl1e_adapter *adapter)
127 {
128 struct atl1e_hw *hw = &adapter->hw;
129 struct net_device *netdev = adapter->netdev;
130 int err = 0;
131 u16 speed, duplex, phy_data;
132
133 /* MII_BMSR must read twise */
134 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
135 atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
136
137 if ((phy_data & BMSR_LSTATUS) == 0) {
138 /* link down */
139 if (netdev_link_ok(netdev)) { /* old link state: Up */
140 u32 value;
141 /* disable rx */
142 value = AT_READ_REG(hw, REG_MAC_CTRL);
143 value &= ~MAC_CTRL_RX_EN;
144 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
145 adapter->link_speed = SPEED_0;
146
147 DBG("atl1e: %s link is down\n", netdev->name);
148 netdev_link_down(netdev);
149 }
150 } else {
151 /* Link Up */
152 err = atl1e_get_speed_and_duplex(hw, &speed, &duplex);
153 if (err)
154 return err;
155
156 /* link result is our setting */
157 if (adapter->link_speed != speed ||
158 adapter->link_duplex != duplex) {
159 adapter->link_speed = speed;
160 adapter->link_duplex = duplex;
161 atl1e_setup_mac_ctrl(adapter);
162
163 DBG("atl1e: %s link is up, %d Mbps, %s duplex\n",
164 netdev->name, adapter->link_speed,
165 adapter->link_duplex == FULL_DUPLEX ?
166 "full" : "half");
167 netdev_link_up(netdev);
168 }
169 }
170 return 0;
171 }
172
173 static int atl1e_mdio_read(struct net_device *netdev, int phy_id __unused,
174 int reg_num)
175 {
176 struct atl1e_adapter *adapter = netdev_priv(netdev);
177 u16 result;
178
179 atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
180 return result;
181 }
182
183 static void atl1e_mdio_write(struct net_device *netdev, int phy_id __unused,
184 int reg_num, int val)
185 {
186 struct atl1e_adapter *adapter = netdev_priv(netdev);
187
188 atl1e_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
189 }
190
191 static void atl1e_setup_pcicmd(struct pci_device *pdev)
192 {
193 u16 cmd;
194
195 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
196 cmd |= (PCI_COMMAND_MEM | PCI_COMMAND_MASTER);
197 pci_write_config_word(pdev, PCI_COMMAND, cmd);
198
199 /*
200 * some motherboards BIOS(PXE/EFI) driver may set PME
201 * while they transfer control to OS (Windows/Linux)
202 * so we should clear this bit before NIC work normally
203 */
204 pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
205 mdelay(1);
206 }
207
208 /*
209 * atl1e_sw_init - Initialize general software structures (struct atl1e_adapter)
210 * @adapter: board private structure to initialize
211 *
212 * atl1e_sw_init initializes the Adapter private data structure.
213 * Fields are initialized based on PCI device information and
214 * OS network device settings (MTU size).
215 */
216 static int atl1e_sw_init(struct atl1e_adapter *adapter)
217 {
218 struct atl1e_hw *hw = &adapter->hw;
219 struct pci_device *pdev = adapter->pdev;
220 u32 phy_status_data = 0;
221 u8 rev_id = 0;
222
223 adapter->link_speed = SPEED_0; /* hardware init */
224 adapter->link_duplex = FULL_DUPLEX;
225
226 /* PCI config space info */
227 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
228
229 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
230 /* nic type */
231 if (rev_id >= 0xF0) {
232 hw->nic_type = athr_l2e_revB;
233 } else {
234 if (phy_status_data & PHY_STATUS_100M)
235 hw->nic_type = athr_l1e;
236 else
237 hw->nic_type = athr_l2e_revA;
238 }
239
240 phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
241
242 hw->emi_ca = !!(phy_status_data & PHY_STATUS_EMI_CA);
243
244 hw->phy_configured = 0;
245
246 /* need confirm */
247
248 hw->dmar_block = atl1e_dma_req_1024;
249 hw->dmaw_block = atl1e_dma_req_1024;
250
251 netdev_link_down(adapter->netdev);
252
253 return 0;
254 }
255
256 /*
257 * atl1e_clean_tx_ring - free all Tx buffers for device close
258 * @adapter: board private structure
259 */
260 static void atl1e_clean_tx_ring(struct atl1e_adapter *adapter)
261 {
262 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
263 &adapter->tx_ring;
264 struct atl1e_tx_buffer *tx_buffer = NULL;
265 u16 index, ring_count = tx_ring->count;
266
267 if (tx_ring->desc == NULL || tx_ring->tx_buffer == NULL)
268 return;
269
270 for (index = 0; index < ring_count; index++) {
271 tx_buffer = &tx_ring->tx_buffer[index];
272 if (tx_buffer->iob) {
273 netdev_tx_complete(adapter->netdev, tx_buffer->iob);
274 tx_buffer->dma = 0;
275 tx_buffer->iob = NULL;
276 }
277 }
278
279 /* Zero out Tx-buffers */
280 memset(tx_ring->desc, 0, sizeof(struct atl1e_tpd_desc) *
281 ring_count);
282 memset(tx_ring->tx_buffer, 0, sizeof(struct atl1e_tx_buffer) *
283 ring_count);
284 }
285
286 /*
287 * atl1e_clean_rx_ring - Free rx-reservation iobs
288 * @adapter: board private structure
289 */
290 static void atl1e_clean_rx_ring(struct atl1e_adapter *adapter)
291 {
292 struct atl1e_rx_ring *rx_ring =
293 (struct atl1e_rx_ring *)&adapter->rx_ring;
294 struct atl1e_rx_page_desc *rx_page_desc = &rx_ring->rx_page_desc;
295 u16 j;
296
297 if (adapter->ring_vir_addr == NULL)
298 return;
299
300 /* Zero out the descriptor ring */
301 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
302 if (rx_page_desc->rx_page[j].addr != NULL) {
303 memset(rx_page_desc->rx_page[j].addr, 0,
304 rx_ring->real_page_size);
305 }
306 }
307 }
308
309 static void atl1e_cal_ring_size(struct atl1e_adapter *adapter, u32 *ring_size)
310 {
311 *ring_size = ((u32)(adapter->tx_ring.count *
312 sizeof(struct atl1e_tpd_desc) + 7
313 /* tx ring, qword align */
314 + adapter->rx_ring.real_page_size * AT_PAGE_NUM_PER_QUEUE
315 + 31
316 /* rx ring, 32 bytes align */
317 + (1 + AT_PAGE_NUM_PER_QUEUE) *
318 sizeof(u32) + 3));
319 /* tx, rx cmd, dword align */
320 }
321
322 static void atl1e_init_ring_resources(struct atl1e_adapter *adapter)
323 {
324 struct atl1e_rx_ring *rx_ring = NULL;
325
326 rx_ring = &adapter->rx_ring;
327
328 rx_ring->real_page_size = adapter->rx_ring.page_size
329 + MAX_FRAME_SIZE
330 + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
331 rx_ring->real_page_size = (rx_ring->real_page_size + 31) & ~31;
332 atl1e_cal_ring_size(adapter, &adapter->ring_size);
333
334 adapter->ring_vir_addr = NULL;
335 adapter->rx_ring.desc = NULL;
336
337 return;
338 }
339
340 /*
341 * Read / Write Ptr Initialize:
342 */
343 static void atl1e_init_ring_ptrs(struct atl1e_adapter *adapter)
344 {
345 struct atl1e_tx_ring *tx_ring = NULL;
346 struct atl1e_rx_ring *rx_ring = NULL;
347 struct atl1e_rx_page_desc *rx_page_desc = NULL;
348 int j;
349
350 tx_ring = &adapter->tx_ring;
351 rx_ring = &adapter->rx_ring;
352 rx_page_desc = &rx_ring->rx_page_desc;
353
354 tx_ring->next_to_use = 0;
355 tx_ring->next_to_clean = 0;
356
357 rx_page_desc->rx_using = 0;
358 rx_page_desc->rx_nxseq = 0;
359 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
360 *rx_page_desc->rx_page[j].write_offset_addr = 0;
361 rx_page_desc->rx_page[j].read_offset = 0;
362 }
363 }
364
365 /*
366 * atl1e_free_ring_resources - Free Tx / RX descriptor Resources
367 * @adapter: board private structure
368 *
369 * Free all transmit software resources
370 */
371 static void atl1e_free_ring_resources(struct atl1e_adapter *adapter)
372 {
373 atl1e_clean_tx_ring(adapter);
374 atl1e_clean_rx_ring(adapter);
375
376 if (adapter->ring_vir_addr) {
377 free_dma(adapter->ring_vir_addr, adapter->ring_size);
378 adapter->ring_vir_addr = NULL;
379 adapter->ring_dma = 0;
380 }
381
382 if (adapter->tx_ring.tx_buffer) {
383 free(adapter->tx_ring.tx_buffer);
384 adapter->tx_ring.tx_buffer = NULL;
385 }
386 }
387
388 /*
389 * atl1e_setup_mem_resources - allocate Tx / RX descriptor resources
390 * @adapter: board private structure
391 *
392 * Return 0 on success, negative on failure
393 */
394 static int atl1e_setup_ring_resources(struct atl1e_adapter *adapter)
395 {
396 struct atl1e_tx_ring *tx_ring;
397 struct atl1e_rx_ring *rx_ring;
398 struct atl1e_rx_page_desc *rx_page_desc;
399 int size, j;
400 u32 offset = 0;
401 int err = 0;
402
403 if (adapter->ring_vir_addr != NULL)
404 return 0; /* alloced already */
405
406 tx_ring = &adapter->tx_ring;
407 rx_ring = &adapter->rx_ring;
408
409 /* real ring DMA buffer */
410
411 size = adapter->ring_size;
412 adapter->ring_vir_addr = malloc_dma(adapter->ring_size, 32);
413
414 if (adapter->ring_vir_addr == NULL) {
415 DBG("atl1e: out of memory allocating %d bytes for %s ring\n",
416 adapter->ring_size, adapter->netdev->name);
417 return -ENOMEM;
418 }
419
420 adapter->ring_dma = virt_to_bus(adapter->ring_vir_addr);
421 memset(adapter->ring_vir_addr, 0, adapter->ring_size);
422
423 rx_page_desc = &rx_ring->rx_page_desc;
424
425 /* Init TPD Ring */
426 tx_ring->dma = (adapter->ring_dma + 7) & ~7;
427 offset = tx_ring->dma - adapter->ring_dma;
428 tx_ring->desc = (struct atl1e_tpd_desc *)
429 (adapter->ring_vir_addr + offset);
430 size = sizeof(struct atl1e_tx_buffer) * (tx_ring->count);
431 tx_ring->tx_buffer = zalloc(size);
432 if (tx_ring->tx_buffer == NULL) {
433 DBG("atl1e: out of memory allocating %d bytes for %s txbuf\n",
434 size, adapter->netdev->name);
435 err = -ENOMEM;
436 goto failed;
437 }
438
439 /* Init RXF-Pages */
440 offset += (sizeof(struct atl1e_tpd_desc) * tx_ring->count);
441 offset = (offset + 31) & ~31;
442
443 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
444 rx_page_desc->rx_page[j].dma =
445 adapter->ring_dma + offset;
446 rx_page_desc->rx_page[j].addr =
447 adapter->ring_vir_addr + offset;
448 offset += rx_ring->real_page_size;
449 }
450
451 /* Init CMB dma address */
452 tx_ring->cmb_dma = adapter->ring_dma + offset;
453 tx_ring->cmb = (u32 *)(adapter->ring_vir_addr + offset);
454 offset += sizeof(u32);
455
456 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
457 rx_page_desc->rx_page[j].write_offset_dma =
458 adapter->ring_dma + offset;
459 rx_page_desc->rx_page[j].write_offset_addr =
460 adapter->ring_vir_addr + offset;
461 offset += sizeof(u32);
462 }
463
464 if (offset > adapter->ring_size) {
465 DBG("atl1e: ring miscalculation! need %d > %d bytes\n",
466 offset, adapter->ring_size);
467 err = -EINVAL;
468 goto failed;
469 }
470
471 return 0;
472 failed:
473 atl1e_free_ring_resources(adapter);
474 return err;
475 }
476
477 static inline void atl1e_configure_des_ring(const struct atl1e_adapter *adapter)
478 {
479
480 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
481 struct atl1e_rx_ring *rx_ring =
482 (struct atl1e_rx_ring *)&adapter->rx_ring;
483 struct atl1e_tx_ring *tx_ring =
484 (struct atl1e_tx_ring *)&adapter->tx_ring;
485 struct atl1e_rx_page_desc *rx_page_desc = NULL;
486 int j;
487
488 AT_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, 0);
489 AT_WRITE_REG(hw, REG_TPD_BASE_ADDR_LO, tx_ring->dma);
490 AT_WRITE_REG(hw, REG_TPD_RING_SIZE, (u16)(tx_ring->count));
491 AT_WRITE_REG(hw, REG_HOST_TX_CMB_LO, tx_ring->cmb_dma);
492
493 rx_page_desc = &rx_ring->rx_page_desc;
494
495 /* RXF Page Physical address / Page Length */
496 AT_WRITE_REG(hw, REG_RXF0_BASE_ADDR_HI, 0);
497
498 for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
499 u32 page_phy_addr;
500 u32 offset_phy_addr;
501
502 page_phy_addr = rx_page_desc->rx_page[j].dma;
503 offset_phy_addr = rx_page_desc->rx_page[j].write_offset_dma;
504
505 AT_WRITE_REG(hw, atl1e_rx_page_lo_addr_regs[j], page_phy_addr);
506 AT_WRITE_REG(hw, atl1e_rx_page_write_offset_regs[j],
507 offset_phy_addr);
508 AT_WRITE_REGB(hw, atl1e_rx_page_vld_regs[j], 1);
509 }
510
511 /* Page Length */
512 AT_WRITE_REG(hw, REG_HOST_RXFPAGE_SIZE, rx_ring->page_size);
513 /* Load all of base address above */
514 AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
515
516 return;
517 }
518
519 static inline void atl1e_configure_tx(struct atl1e_adapter *adapter)
520 {
521 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
522 u32 dev_ctrl_data = 0;
523 u32 max_pay_load = 0;
524 u32 jumbo_thresh = 0;
525 u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */
526
527 /* configure TXQ param */
528 if (hw->nic_type != athr_l2e_revB) {
529 extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
530 jumbo_thresh = MAX_FRAME_SIZE + extra_size;
531 AT_WRITE_REG(hw, REG_TX_EARLY_TH, (jumbo_thresh + 7) >> 3);
532 }
533
534 dev_ctrl_data = AT_READ_REG(hw, REG_DEVICE_CTRL);
535
536 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT)) &
537 DEVICE_CTRL_MAX_PAYLOAD_MASK;
538 if (max_pay_load < hw->dmaw_block)
539 hw->dmaw_block = max_pay_load;
540
541 max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT)) &
542 DEVICE_CTRL_MAX_RREQ_SZ_MASK;
543 if (max_pay_load < hw->dmar_block)
544 hw->dmar_block = max_pay_load;
545
546 if (hw->nic_type != athr_l2e_revB)
547 AT_WRITE_REGW(hw, REG_TXQ_CTRL + 2,
548 atl1e_pay_load_size[hw->dmar_block]);
549 /* enable TXQ */
550 AT_WRITE_REGW(hw, REG_TXQ_CTRL,
551 ((TPD_BURST & TXQ_CTRL_NUM_TPD_BURST_MASK)
552 << TXQ_CTRL_NUM_TPD_BURST_SHIFT)
553 | TXQ_CTRL_ENH_MODE | TXQ_CTRL_EN);
554 return;
555 }
556
557 static inline void atl1e_configure_rx(struct atl1e_adapter *adapter)
558 {
559 struct atl1e_hw *hw = (struct atl1e_hw *)&adapter->hw;
560 u32 rxf_len = 0;
561 u32 rxf_low = 0;
562 u32 rxf_high = 0;
563 u32 rxf_thresh_data = 0;
564 u32 rxq_ctrl_data = 0;
565
566 if (hw->nic_type != athr_l2e_revB) {
567 AT_WRITE_REGW(hw, REG_RXQ_JMBOSZ_RRDTIM,
568 (u16)((RX_JUMBO_THRESH & RXQ_JMBOSZ_TH_MASK) <<
569 RXQ_JMBOSZ_TH_SHIFT |
570 (1 & RXQ_JMBO_LKAH_MASK) <<
571 RXQ_JMBO_LKAH_SHIFT));
572
573 rxf_len = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
574 rxf_high = rxf_len * 4 / 5;
575 rxf_low = rxf_len / 5;
576 rxf_thresh_data = ((rxf_high & RXQ_RXF_PAUSE_TH_HI_MASK)
577 << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
578 ((rxf_low & RXQ_RXF_PAUSE_TH_LO_MASK)
579 << RXQ_RXF_PAUSE_TH_LO_SHIFT);
580
581 AT_WRITE_REG(hw, REG_RXQ_RXF_PAUSE_THRESH, rxf_thresh_data);
582 }
583
584 /* RRS */
585 AT_WRITE_REG(hw, REG_IDT_TABLE, 0);
586 AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, 0);
587
588 rxq_ctrl_data |= RXQ_CTRL_PBA_ALIGN_32 |
589 RXQ_CTRL_CUT_THRU_EN | RXQ_CTRL_EN;
590
591 AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
592 return;
593 }
594
595 static inline void atl1e_configure_dma(struct atl1e_adapter *adapter)
596 {
597 struct atl1e_hw *hw = &adapter->hw;
598 u32 dma_ctrl_data = 0;
599
600 dma_ctrl_data = DMA_CTRL_RXCMB_EN;
601 dma_ctrl_data |= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
602 << DMA_CTRL_DMAR_BURST_LEN_SHIFT;
603 dma_ctrl_data |= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
604 << DMA_CTRL_DMAW_BURST_LEN_SHIFT;
605 dma_ctrl_data |= DMA_CTRL_DMAR_REQ_PRI | DMA_CTRL_DMAR_OUT_ORDER;
606 dma_ctrl_data |= (DMAR_DLY_CNT & DMA_CTRL_DMAR_DLY_CNT_MASK)
607 << DMA_CTRL_DMAR_DLY_CNT_SHIFT;
608 dma_ctrl_data |= (DMAW_DLY_CNT & DMA_CTRL_DMAW_DLY_CNT_MASK)
609 << DMA_CTRL_DMAW_DLY_CNT_SHIFT;
610
611 AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
612 return;
613 }
614
615 static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter)
616 {
617 u32 value;
618 struct atl1e_hw *hw = &adapter->hw;
619
620 /* Config MAC CTRL Register */
621 value = MAC_CTRL_TX_EN |
622 MAC_CTRL_RX_EN ;
623
624 if (FULL_DUPLEX == adapter->link_duplex)
625 value |= MAC_CTRL_DUPLX;
626
627 value |= ((u32)((SPEED_1000 == adapter->link_speed) ?
628 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
629 MAC_CTRL_SPEED_SHIFT);
630 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
631
632 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
633 value |= ((PREAMBLE_LEN & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
634
635 value |= MAC_CTRL_BC_EN;
636 value |= MAC_CTRL_MC_ALL_EN;
637
638 AT_WRITE_REG(hw, REG_MAC_CTRL, value);
639 }
640
641 /*
642 * atl1e_configure - Configure Transmit&Receive Unit after Reset
643 * @adapter: board private structure
644 *
645 * Configure the Tx /Rx unit of the MAC after a reset.
646 */
647 static int atl1e_configure(struct atl1e_adapter *adapter)
648 {
649 struct atl1e_hw *hw = &adapter->hw;
650 u32 intr_status_data = 0;
651
652 /* clear interrupt status */
653 AT_WRITE_REG(hw, REG_ISR, ~0);
654
655 /* 1. set MAC Address */
656 atl1e_hw_set_mac_addr(hw);
657
658 /* 2. Init the Multicast HASH table (clear) */
659 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
660 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
661
662 /* 3. Clear any WOL status */
663 AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
664
665 /* 4. Descripter Ring BaseMem/Length/Read ptr/Write ptr
666 * TPD Ring/SMB/RXF0 Page CMBs, they use the same
667 * High 32bits memory */
668 atl1e_configure_des_ring(adapter);
669
670 /* 5. set Interrupt Moderator Timer */
671 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, IMT_VAL);
672 AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER2_INIT, IMT_VAL);
673 AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_LED_MODE |
674 MASTER_CTRL_ITIMER_EN | MASTER_CTRL_ITIMER2_EN);
675
676 /* 6. rx/tx threshold to trig interrupt */
677 AT_WRITE_REGW(hw, REG_TRIG_RRD_THRESH, RRD_THRESH);
678 AT_WRITE_REGW(hw, REG_TRIG_TPD_THRESH, TPD_THRESH);
679 AT_WRITE_REGW(hw, REG_TRIG_RXTIMER, RX_COUNT_DOWN);
680 AT_WRITE_REGW(hw, REG_TRIG_TXTIMER, TX_COUNT_DOWN);
681
682 /* 7. set Interrupt Clear Timer */
683 AT_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, ICT_VAL);
684
685 /* 8. set MTU */
686 AT_WRITE_REG(hw, REG_MTU, MAX_FRAME_SIZE + ETH_HLEN +
687 VLAN_HLEN + ETH_FCS_LEN);
688
689 /* 9. config TXQ early tx threshold */
690 atl1e_configure_tx(adapter);
691
692 /* 10. config RXQ */
693 atl1e_configure_rx(adapter);
694
695 /* 11. config DMA Engine */
696 atl1e_configure_dma(adapter);
697
698 /* 12. smb timer to trig interrupt */
699 AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, SMB_TIMER);
700
701 intr_status_data = AT_READ_REG(hw, REG_ISR);
702 if ((intr_status_data & ISR_PHY_LINKDOWN) != 0) {
703 DBG("atl1e: configure failed, PCIE phy link down\n");
704 return -1;
705 }
706
707 AT_WRITE_REG(hw, REG_ISR, 0x7fffffff);
708 return 0;
709 }
710
711 static inline void atl1e_clear_phy_int(struct atl1e_adapter *adapter)
712 {
713 u16 phy_data;
714
715 atl1e_read_phy_reg(&adapter->hw, MII_INT_STATUS, &phy_data);
716 }
717
718 static int atl1e_clean_tx_irq(struct atl1e_adapter *adapter)
719 {
720 struct atl1e_tx_ring *tx_ring = (struct atl1e_tx_ring *)
721 &adapter->tx_ring;
722 struct atl1e_tx_buffer *tx_buffer = NULL;
723 u16 hw_next_to_clean = AT_READ_REGW(&adapter->hw, REG_TPD_CONS_IDX);
724 u16 next_to_clean = tx_ring->next_to_clean;
725
726 while (next_to_clean != hw_next_to_clean) {
727 tx_buffer = &tx_ring->tx_buffer[next_to_clean];
728
729 tx_buffer->dma = 0;
730 if (tx_buffer->iob) {
731 netdev_tx_complete(adapter->netdev, tx_buffer->iob);
732 tx_buffer->iob = NULL;
733 }
734
735 if (++next_to_clean == tx_ring->count)
736 next_to_clean = 0;
737 }
738
739 tx_ring->next_to_clean = next_to_clean;
740
741 return 1;
742 }
743
744 static struct atl1e_rx_page *atl1e_get_rx_page(struct atl1e_adapter *adapter)
745 {
746 struct atl1e_rx_page_desc *rx_page_desc =
747 (struct atl1e_rx_page_desc *) &adapter->rx_ring.rx_page_desc;
748 u8 rx_using = rx_page_desc->rx_using;
749
750 return (struct atl1e_rx_page *)&(rx_page_desc->rx_page[rx_using]);
751 }
752
753 static void atl1e_clean_rx_irq(struct atl1e_adapter *adapter)
754 {
755 struct net_device *netdev = adapter->netdev;
756 struct atl1e_rx_ring *rx_ring = (struct atl1e_rx_ring *)
757 &adapter->rx_ring;
758 struct atl1e_rx_page_desc *rx_page_desc =
759 (struct atl1e_rx_page_desc *) &rx_ring->rx_page_desc;
760 struct io_buffer *iob = NULL;
761 struct atl1e_rx_page *rx_page = atl1e_get_rx_page(adapter);
762 u32 packet_size, write_offset;
763 struct atl1e_recv_ret_status *prrs;
764
765 write_offset = *(rx_page->write_offset_addr);
766 if (rx_page->read_offset >= write_offset)
767 return;
768
769 do {
770 /* get new packet's rrs */
771 prrs = (struct atl1e_recv_ret_status *) (rx_page->addr +
772 rx_page->read_offset);
773 /* check sequence number */
774 if (prrs->seq_num != rx_page_desc->rx_nxseq) {
775 DBG("atl1e %s: RX sequence number error (%d != %d)\n",
776 netdev->name, prrs->seq_num,
777 rx_page_desc->rx_nxseq);
778 rx_page_desc->rx_nxseq++;
779 goto fatal_err;
780 }
781
782 rx_page_desc->rx_nxseq++;
783
784 /* error packet */
785 if (prrs->pkt_flag & RRS_IS_ERR_FRAME) {
786 if (prrs->err_flag & (RRS_ERR_BAD_CRC |
787 RRS_ERR_DRIBBLE | RRS_ERR_CODE |
788 RRS_ERR_TRUNC)) {
789 /* hardware error, discard this
790 packet */
791 netdev_rx_err(netdev, NULL, EIO);
792 goto skip_pkt;
793 }
794 }
795
796 packet_size = ((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
797 RRS_PKT_SIZE_MASK) - ETH_FCS_LEN;
798 iob = alloc_iob(packet_size + NET_IP_ALIGN);
799 if (iob == NULL) {
800 DBG("atl1e %s: dropping packet under memory pressure\n",
801 netdev->name);
802 goto skip_pkt;
803 }
804 iob_reserve(iob, NET_IP_ALIGN);
805 memcpy(iob->data, (u8 *)(prrs + 1), packet_size);
806 iob_put(iob, packet_size);
807
808 netdev_rx(netdev, iob);
809
810 skip_pkt:
811 /* skip current packet whether it's ok or not. */
812 rx_page->read_offset +=
813 (((u32)((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
814 RRS_PKT_SIZE_MASK) +
815 sizeof(struct atl1e_recv_ret_status) + 31) &
816 0xFFFFFFE0);
817
818 if (rx_page->read_offset >= rx_ring->page_size) {
819 /* mark this page clean */
820 u16 reg_addr;
821 u8 rx_using;
822
823 rx_page->read_offset =
824 *(rx_page->write_offset_addr) = 0;
825 rx_using = rx_page_desc->rx_using;
826 reg_addr =
827 atl1e_rx_page_vld_regs[rx_using];
828 AT_WRITE_REGB(&adapter->hw, reg_addr, 1);
829 rx_page_desc->rx_using ^= 1;
830 rx_page = atl1e_get_rx_page(adapter);
831 }
832 write_offset = *(rx_page->write_offset_addr);
833 } while (rx_page->read_offset < write_offset);
834
835 return;
836
837 fatal_err:
838 if (!netdev_link_ok(adapter->netdev))
839 atl1e_reset(adapter);
840 }
841
842 /*
843 * atl1e_poll - poll for completed transmissions and received packets
844 * @netdev: network device
845 */
846 static void atl1e_poll(struct net_device *netdev)
847 {
848 struct atl1e_adapter *adapter = netdev_priv(netdev);
849 struct atl1e_hw *hw = &adapter->hw;
850 int max_ints = 64;
851 u32 status;
852
853 do {
854 status = AT_READ_REG(hw, REG_ISR);
855 if ((status & IMR_NORMAL_MASK) == 0)
856 break;
857
858 /* link event */
859 if (status & ISR_GPHY)
860 atl1e_clear_phy_int(adapter);
861 /* Ack ISR */
862 AT_WRITE_REG(hw, REG_ISR, status | ISR_DIS_INT);
863
864 /* check if PCIE PHY Link down */
865 if (status & ISR_PHY_LINKDOWN) {
866 DBG("atl1e: PCI-E PHY link down: %x\n", status);
867 if (netdev_link_ok(adapter->netdev)) {
868 /* reset MAC */
869 atl1e_irq_reset(adapter);
870 atl1e_reset(adapter);
871 break;
872 }
873 }
874
875 /* check if DMA read/write error */
876 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
877 DBG("atl1e: PCI-E DMA RW error: %x\n", status);
878 atl1e_irq_reset(adapter);
879 atl1e_reset(adapter);
880 break;
881 }
882
883 /* link event */
884 if (status & (ISR_GPHY | ISR_MANUAL)) {
885 atl1e_check_link(adapter);
886 break;
887 }
888
889 /* transmit event */
890 if (status & ISR_TX_EVENT)
891 atl1e_clean_tx_irq(adapter);
892
893 if (status & ISR_RX_EVENT)
894 atl1e_clean_rx_irq(adapter);
895 } while (--max_ints > 0);
896
897 /* re-enable Interrupt*/
898 AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
899
900 return;
901 }
902
903 static inline u16 atl1e_tpd_avail(struct atl1e_adapter *adapter)
904 {
905 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
906 u16 next_to_use = 0;
907 u16 next_to_clean = 0;
908
909 next_to_clean = tx_ring->next_to_clean;
910 next_to_use = tx_ring->next_to_use;
911
912 return (u16)(next_to_clean > next_to_use) ?
913 (next_to_clean - next_to_use - 1) :
914 (tx_ring->count + next_to_clean - next_to_use - 1);
915 }
916
917 /*
918 * get next usable tpd
919 * Note: should call atl1e_tdp_avail to make sure
920 * there is enough tpd to use
921 */
922 static struct atl1e_tpd_desc *atl1e_get_tpd(struct atl1e_adapter *adapter)
923 {
924 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
925 u16 next_to_use = 0;
926
927 next_to_use = tx_ring->next_to_use;
928 if (++tx_ring->next_to_use == tx_ring->count)
929 tx_ring->next_to_use = 0;
930
931 memset(&tx_ring->desc[next_to_use], 0, sizeof(struct atl1e_tpd_desc));
932 return (struct atl1e_tpd_desc *)&tx_ring->desc[next_to_use];
933 }
934
935 static struct atl1e_tx_buffer *
936 atl1e_get_tx_buffer(struct atl1e_adapter *adapter, struct atl1e_tpd_desc *tpd)
937 {
938 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
939
940 return &tx_ring->tx_buffer[tpd - tx_ring->desc];
941 }
942
943 static void atl1e_tx_map(struct atl1e_adapter *adapter,
944 struct io_buffer *iob, struct atl1e_tpd_desc *tpd)
945 {
946 struct atl1e_tx_buffer *tx_buffer = NULL;
947 u16 buf_len = iob_len(iob);
948
949 tx_buffer = atl1e_get_tx_buffer(adapter, tpd);
950 tx_buffer->iob = iob;
951 tx_buffer->length = buf_len;
952 tx_buffer->dma = virt_to_bus(iob->data);
953 tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
954 tpd->word2 = ((tpd->word2 & ~TPD_BUFLEN_MASK) |
955 ((cpu_to_le32(buf_len) & TPD_BUFLEN_MASK) <<
956 TPD_BUFLEN_SHIFT));
957 tpd->word3 |= 1 << TPD_EOP_SHIFT;
958 }
959
960 static void atl1e_tx_queue(struct atl1e_adapter *adapter, u16 count __unused,
961 struct atl1e_tpd_desc *tpd __unused)
962 {
963 struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
964 wmb();
965 AT_WRITE_REG(&adapter->hw, REG_MB_TPD_PROD_IDX, tx_ring->next_to_use);
966 }
967
968 static int atl1e_xmit_frame(struct net_device *netdev, struct io_buffer *iob)
969 {
970 struct atl1e_adapter *adapter = netdev_priv(netdev);
971 u16 tpd_req = 1;
972 struct atl1e_tpd_desc *tpd;
973
974 if (!netdev_link_ok(netdev)) {
975 return -EINVAL;
976 }
977
978 if (atl1e_tpd_avail(adapter) < tpd_req) {
979 return -EBUSY;
980 }
981
982 tpd = atl1e_get_tpd(adapter);
983
984 atl1e_tx_map(adapter, iob, tpd);
985 atl1e_tx_queue(adapter, tpd_req, tpd);
986
987 return 0;
988 }
989
990 int atl1e_up(struct atl1e_adapter *adapter)
991 {
992 struct net_device *netdev = adapter->netdev;
993 int err = 0;
994 u32 val;
995
996 /* hardware has been reset, we need to reload some things */
997 err = atl1e_init_hw(&adapter->hw);
998 if (err) {
999 return -EIO;
1000 }
1001 atl1e_init_ring_ptrs(adapter);
1002
1003 memcpy(adapter->hw.mac_addr, netdev->ll_addr, ETH_ALEN);
1004
1005 if (atl1e_configure(adapter) != 0) {
1006 return -EIO;
1007 }
1008
1009 atl1e_irq_disable(adapter);
1010
1011 val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1012 AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
1013 val | MASTER_CTRL_MANUAL_INT);
1014
1015 return err;
1016 }
1017
1018 void atl1e_irq(struct net_device *netdev, int enable)
1019 {
1020 struct atl1e_adapter *adapter = netdev_priv(netdev);
1021
1022 if (enable)
1023 atl1e_irq_enable(adapter);
1024 else
1025 atl1e_irq_disable(adapter);
1026 }
1027
1028 void atl1e_down(struct atl1e_adapter *adapter)
1029 {
1030 struct net_device *netdev = adapter->netdev;
1031
1032 /* reset MAC to disable all RX/TX */
1033 atl1e_reset_hw(&adapter->hw);
1034 mdelay(1);
1035
1036 netdev_link_down(netdev);
1037 adapter->link_speed = SPEED_0;
1038 adapter->link_duplex = -1;
1039
1040 atl1e_clean_tx_ring(adapter);
1041 atl1e_clean_rx_ring(adapter);
1042 }
1043
1044 /*
1045 * atl1e_open - Called when a network interface is made active
1046 * @netdev: network interface device structure
1047 *
1048 * Returns 0 on success, negative value on failure
1049 *
1050 * The open entry point is called when a network interface is made
1051 * active by the system (IFF_UP). At this point all resources needed
1052 * for transmit and receive operations are allocated, the interrupt
1053 * handler is registered with the OS, the watchdog timer is started,
1054 * and the stack is notified that the interface is ready.
1055 */
1056 static int atl1e_open(struct net_device *netdev)
1057 {
1058 struct atl1e_adapter *adapter = netdev_priv(netdev);
1059 int err;
1060
1061 /* allocate rx/tx dma buffer & descriptors */
1062 atl1e_init_ring_resources(adapter);
1063 err = atl1e_setup_ring_resources(adapter);
1064 if (err)
1065 return err;
1066
1067 err = atl1e_up(adapter);
1068 if (err)
1069 goto err_up;
1070
1071 return 0;
1072
1073 err_up:
1074 atl1e_free_ring_resources(adapter);
1075 atl1e_reset_hw(&adapter->hw);
1076
1077 return err;
1078 }
1079
1080 /*
1081 * atl1e_close - Disables a network interface
1082 * @netdev: network interface device structure
1083 *
1084 * Returns 0, this is not allowed to fail
1085 *
1086 * The close entry point is called when an interface is de-activated
1087 * by the OS. The hardware is still under the drivers control, but
1088 * needs to be disabled. A global MAC reset is issued to stop the
1089 * hardware, and all transmit and receive resources are freed.
1090 */
1091 static void atl1e_close(struct net_device *netdev)
1092 {
1093 struct atl1e_adapter *adapter = netdev_priv(netdev);
1094
1095 atl1e_down(adapter);
1096 atl1e_free_ring_resources(adapter);
1097 }
1098
1099 static struct net_device_operations atl1e_netdev_ops = {
1100 .open = atl1e_open,
1101 .close = atl1e_close,
1102 .transmit = atl1e_xmit_frame,
1103 .poll = atl1e_poll,
1104 .irq = atl1e_irq,
1105 };
1106
1107 static void atl1e_init_netdev(struct net_device *netdev, struct pci_device *pdev)
1108 {
1109 netdev_init(netdev, &atl1e_netdev_ops);
1110
1111 netdev->dev = &pdev->dev;
1112 pci_set_drvdata(pdev, netdev);
1113 }
1114
1115 /*
1116 * atl1e_probe - Device Initialization Routine
1117 * @pdev: PCI device information struct
1118 * @ent: entry in atl1e_pci_tbl
1119 *
1120 * Returns 0 on success, negative on failure
1121 *
1122 * atl1e_probe initializes an adapter identified by a pci_device structure.
1123 * The OS initialization, configuring of the adapter private structure,
1124 * and a hardware reset occur.
1125 */
1126 static int atl1e_probe(struct pci_device *pdev,
1127 const struct pci_device_id *ent __unused)
1128 {
1129 struct net_device *netdev;
1130 struct atl1e_adapter *adapter = NULL;
1131 static int cards_found;
1132
1133 int err = 0;
1134
1135 adjust_pci_device(pdev);
1136
1137 netdev = alloc_etherdev(sizeof(struct atl1e_adapter));
1138 if (netdev == NULL) {
1139 err = -ENOMEM;
1140 DBG("atl1e: out of memory allocating net_device\n");
1141 goto err;
1142 }
1143
1144 atl1e_init_netdev(netdev, pdev);
1145
1146 adapter = netdev_priv(netdev);
1147 adapter->bd_number = cards_found;
1148 adapter->netdev = netdev;
1149 adapter->pdev = pdev;
1150 adapter->hw.adapter = adapter;
1151 if (!pdev->membase) {
1152 err = -EIO;
1153 DBG("atl1e: cannot map device registers\n");
1154 goto err_free_netdev;
1155 }
1156 adapter->hw.hw_addr = bus_to_virt(pdev->membase);
1157
1158 /* init mii data */
1159 adapter->mii.dev = netdev;
1160 adapter->mii.mdio_read = atl1e_mdio_read;
1161 adapter->mii.mdio_write = atl1e_mdio_write;
1162 adapter->mii.phy_id_mask = 0x1f;
1163 adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
1164
1165 /* get user settings */
1166 adapter->tx_ring.count = TX_DESC_COUNT;
1167 adapter->rx_ring.page_size = RX_MEM_SIZE;
1168
1169 atl1e_setup_pcicmd(pdev);
1170
1171 /* setup the private structure */
1172 err = atl1e_sw_init(adapter);
1173 if (err) {
1174 DBG("atl1e: private data init failed\n");
1175 goto err_free_netdev;
1176 }
1177
1178 /* Init GPHY as early as possible due to power saving issue */
1179 atl1e_phy_init(&adapter->hw);
1180
1181 /* reset the controller to
1182 * put the device in a known good starting state */
1183 err = atl1e_reset_hw(&adapter->hw);
1184 if (err) {
1185 err = -EIO;
1186 goto err_free_netdev;
1187 }
1188
1189 /* This may have been run by a zero-wait timer around
1190 now... unclear. */
1191 atl1e_restart_autoneg(&adapter->hw);
1192
1193 if (atl1e_read_mac_addr(&adapter->hw) != 0) {
1194 DBG("atl1e: cannot read MAC address from EEPROM\n");
1195 err = -EIO;
1196 goto err_free_netdev;
1197 }
1198
1199 memcpy(netdev->hw_addr, adapter->hw.perm_mac_addr, ETH_ALEN);
1200 memcpy(netdev->ll_addr, adapter->hw.mac_addr, ETH_ALEN);
1201 DBG("atl1e: Attansic L1E Ethernet controller on %s, "
1202 "%02x:%02x:%02x:%02x:%02x:%02x\n", adapter->netdev->name,
1203 adapter->hw.mac_addr[0], adapter->hw.mac_addr[1],
1204 adapter->hw.mac_addr[2], adapter->hw.mac_addr[3],
1205 adapter->hw.mac_addr[4], adapter->hw.mac_addr[5]);
1206
1207 err = register_netdev(netdev);
1208 if (err) {
1209 DBG("atl1e: cannot register network device\n");
1210 goto err_free_netdev;
1211 }
1212
1213 netdev_link_down(netdev);
1214
1215 cards_found++;
1216 return 0;
1217
1218 err_free_netdev:
1219 netdev_nullify(netdev);
1220 netdev_put(netdev);
1221 err:
1222 return err;
1223 }
1224
1225 /*
1226 * atl1e_remove - Device Removal Routine
1227 * @pdev: PCI device information struct
1228 *
1229 * atl1e_remove is called by the PCI subsystem to alert the driver
1230 * that it should release a PCI device. The could be caused by a
1231 * Hot-Plug event, or because the driver is going to be removed from
1232 * memory.
1233 */
1234 static void atl1e_remove(struct pci_device *pdev)
1235 {
1236 struct net_device *netdev = pci_get_drvdata(pdev);
1237 struct atl1e_adapter *adapter = netdev_priv(netdev);
1238
1239 unregister_netdev(netdev);
1240 atl1e_free_ring_resources(adapter);
1241 atl1e_force_ps(&adapter->hw);
1242 netdev_nullify(netdev);
1243 netdev_put(netdev);
1244 }
1245
1246 struct pci_driver atl1e_driver __pci_driver = {
1247 .ids = atl1e_pci_tbl,
1248 .id_count = (sizeof(atl1e_pci_tbl) / sizeof(atl1e_pci_tbl[0])),
1249 .probe = atl1e_probe,
1250 .remove = atl1e_remove,
1251 };
1252
1253 /********** Hardware-level functions: **********/
1254
1255 /*
1256 * check_eeprom_exist
1257 * return 0 if eeprom exist
1258 */
1259 int atl1e_check_eeprom_exist(struct atl1e_hw *hw)
1260 {
1261 u32 value;
1262
1263 value = AT_READ_REG(hw, REG_SPI_FLASH_CTRL);
1264 if (value & SPI_FLASH_CTRL_EN_VPD) {
1265 value &= ~SPI_FLASH_CTRL_EN_VPD;
1266 AT_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
1267 }
1268 value = AT_READ_REGW(hw, REG_PCIE_CAP_LIST);
1269 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
1270 }
1271
1272 void atl1e_hw_set_mac_addr(struct atl1e_hw *hw)
1273 {
1274 u32 value;
1275 /*
1276 * 00-0B-6A-F6-00-DC
1277 * 0: 6AF600DC 1: 000B
1278 * low dword
1279 */
1280 value = (((u32)hw->mac_addr[2]) << 24) |
1281 (((u32)hw->mac_addr[3]) << 16) |
1282 (((u32)hw->mac_addr[4]) << 8) |
1283 (((u32)hw->mac_addr[5])) ;
1284 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
1285 /* hight dword */
1286 value = (((u32)hw->mac_addr[0]) << 8) |
1287 (((u32)hw->mac_addr[1])) ;
1288 AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
1289 }
1290
1291 /*
1292 * atl1e_get_permanent_address
1293 * return 0 if get valid mac address,
1294 */
1295 static int atl1e_get_permanent_address(struct atl1e_hw *hw)
1296 {
1297 union {
1298 u32 dword[2];
1299 u8 byte[8];
1300 } hw_addr;
1301 u32 i;
1302 u32 twsi_ctrl_data;
1303 u8 eth_addr[ETH_ALEN];
1304
1305 if (!atl1e_check_eeprom_exist(hw)) {
1306 /* eeprom exist */
1307 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
1308 twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
1309 AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
1310 for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) {
1311 mdelay(10);
1312 twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
1313 if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0)
1314 break;
1315 }
1316 if (i >= AT_TWSI_EEPROM_TIMEOUT)
1317 return AT_ERR_TIMEOUT;
1318 }
1319
1320 /* maybe MAC-address is from BIOS */
1321 hw_addr.dword[0] = AT_READ_REG(hw, REG_MAC_STA_ADDR);
1322 hw_addr.dword[1] = AT_READ_REG(hw, REG_MAC_STA_ADDR + 4);
1323 for (i = 0; i < ETH_ALEN; i++) {
1324 eth_addr[ETH_ALEN - i - 1] = hw_addr.byte[i];
1325 }
1326
1327 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
1328 return 0;
1329 }
1330
1331 void atl1e_force_ps(struct atl1e_hw *hw)
1332 {
1333 AT_WRITE_REGW(hw, REG_GPHY_CTRL,
1334 GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET);
1335 }
1336
1337 /*
1338 * Reads the adapter's MAC address from the EEPROM
1339 *
1340 * hw - Struct containing variables accessed by shared code
1341 */
1342 int atl1e_read_mac_addr(struct atl1e_hw *hw)
1343 {
1344 int err = 0;
1345
1346 err = atl1e_get_permanent_address(hw);
1347 if (err)
1348 return AT_ERR_EEPROM;
1349 memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
1350 return 0;
1351 }
1352
1353 /*
1354 * Reads the value from a PHY register
1355 * hw - Struct containing variables accessed by shared code
1356 * reg_addr - address of the PHY register to read
1357 */
1358 int atl1e_read_phy_reg(struct atl1e_hw *hw, u16 reg_addr, u16 *phy_data)
1359 {
1360 u32 val;
1361 int i;
1362
1363 val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
1364 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW |
1365 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
1366
1367 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
1368
1369 wmb();
1370
1371 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
1372 udelay(2);
1373 val = AT_READ_REG(hw, REG_MDIO_CTRL);
1374 if (!(val & (MDIO_START | MDIO_BUSY)))
1375 break;
1376 wmb();
1377 }
1378 if (!(val & (MDIO_START | MDIO_BUSY))) {
1379 *phy_data = (u16)val;
1380 return 0;
1381 }
1382
1383 return AT_ERR_PHY;
1384 }
1385
1386 /*
1387 * Writes a value to a PHY register
1388 * hw - Struct containing variables accessed by shared code
1389 * reg_addr - address of the PHY register to write
1390 * data - data to write to the PHY
1391 */
1392 int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data)
1393 {
1394 int i;
1395 u32 val;
1396
1397 val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
1398 (reg_addr&MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
1399 MDIO_SUP_PREAMBLE |
1400 MDIO_START |
1401 MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
1402
1403 AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
1404 wmb();
1405
1406 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
1407 udelay(2);
1408 val = AT_READ_REG(hw, REG_MDIO_CTRL);
1409 if (!(val & (MDIO_START | MDIO_BUSY)))
1410 break;
1411 wmb();
1412 }
1413
1414 if (!(val & (MDIO_START | MDIO_BUSY)))
1415 return 0;
1416
1417 return AT_ERR_PHY;
1418 }
1419
1420 /*
1421 * atl1e_init_pcie - init PCIE module
1422 */
1423 static void atl1e_init_pcie(struct atl1e_hw *hw)
1424 {
1425 u32 value;
1426 /* comment 2lines below to save more power when sususpend
1427 value = LTSSM_TEST_MODE_DEF;
1428 AT_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
1429 */
1430
1431 /* pcie flow control mode change */
1432 value = AT_READ_REG(hw, 0x1008);
1433 value |= 0x8000;
1434 AT_WRITE_REG(hw, 0x1008, value);
1435 }
1436 /*
1437 * Configures PHY autoneg and flow control advertisement settings
1438 *
1439 * hw - Struct containing variables accessed by shared code
1440 */
1441 static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw)
1442 {
1443 s32 ret_val;
1444 u16 mii_autoneg_adv_reg;
1445 u16 mii_1000t_ctrl_reg;
1446
1447 if (0 != hw->mii_autoneg_adv_reg)
1448 return 0;
1449 /* Read the MII Auto-Neg Advertisement Register (Address 4/9). */
1450 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
1451 mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
1452
1453 /*
1454 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1455 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1456 * the 1000Base-T control Register (Address 9).
1457 */
1458 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
1459 mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
1460
1461 /* Assume auto-detect media type */
1462 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
1463 MII_AR_10T_FD_CAPS |
1464 MII_AR_100TX_HD_CAPS |
1465 MII_AR_100TX_FD_CAPS);
1466 if (hw->nic_type == athr_l1e) {
1467 mii_1000t_ctrl_reg |= MII_AT001_CR_1000T_FD_CAPS;
1468 }
1469
1470 /* flow control fixed to enable all */
1471 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
1472
1473 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
1474 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
1475
1476 ret_val = atl1e_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1477 if (ret_val)
1478 return ret_val;
1479
1480 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
1481 ret_val = atl1e_write_phy_reg(hw, MII_AT001_CR,
1482 mii_1000t_ctrl_reg);
1483 if (ret_val)
1484 return ret_val;
1485 }
1486
1487 return 0;
1488 }
1489
1490
1491 /*
1492 * Resets the PHY and make all config validate
1493 *
1494 * hw - Struct containing variables accessed by shared code
1495 *
1496 * Sets bit 15 and 12 of the MII control regiser (for F001 bug)
1497 */
1498 int atl1e_phy_commit(struct atl1e_hw *hw)
1499 {
1500 int ret_val;
1501 u16 phy_data;
1502
1503 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1504
1505 ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data);
1506 if (ret_val) {
1507 u32 val;
1508 int i;
1509 /**************************************
1510 * pcie serdes link may be down !
1511 **************************************/
1512 for (i = 0; i < 25; i++) {
1513 mdelay(1);
1514 val = AT_READ_REG(hw, REG_MDIO_CTRL);
1515 if (!(val & (MDIO_START | MDIO_BUSY)))
1516 break;
1517 }
1518
1519 if (0 != (val & (MDIO_START | MDIO_BUSY))) {
1520 DBG("atl1e: PCI-E link down for at least 25ms\n");
1521 return ret_val;
1522 }
1523
1524 DBG("atl1e: PCI-E link up after %d ms\n", i);
1525 }
1526 return 0;
1527 }
1528
1529 int atl1e_phy_init(struct atl1e_hw *hw)
1530 {
1531 s32 ret_val;
1532 u16 phy_val;
1533
1534 if (hw->phy_configured) {
1535 if (hw->re_autoneg) {
1536 hw->re_autoneg = 0;
1537 return atl1e_restart_autoneg(hw);
1538 }
1539 return 0;
1540 }
1541
1542 /* RESET GPHY Core */
1543 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
1544 mdelay(2);
1545 AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT |
1546 GPHY_CTRL_EXT_RESET);
1547 mdelay(2);
1548
1549 /* patches */
1550 /* p1. eable hibernation mode */
1551 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0xB);
1552 if (ret_val)
1553 return ret_val;
1554 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0xBC00);
1555 if (ret_val)
1556 return ret_val;
1557 /* p2. set Class A/B for all modes */
1558 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0);
1559 if (ret_val)
1560 return ret_val;
1561 phy_val = 0x02ef;
1562 /* remove Class AB */
1563 /* phy_val = hw->emi_ca ? 0x02ef : 0x02df; */
1564 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, phy_val);
1565 if (ret_val)
1566 return ret_val;
1567 /* p3. 10B ??? */
1568 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x12);
1569 if (ret_val)
1570 return ret_val;
1571 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x4C04);
1572 if (ret_val)
1573 return ret_val;
1574 /* p4. 1000T power */
1575 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x4);
1576 if (ret_val)
1577 return ret_val;
1578 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x8BBB);
1579 if (ret_val)
1580 return ret_val;
1581
1582 ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x5);
1583 if (ret_val)
1584 return ret_val;
1585 ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x2C46);
1586 if (ret_val)
1587 return ret_val;
1588
1589 mdelay(1);
1590
1591 /*Enable PHY LinkChange Interrupt */
1592 ret_val = atl1e_write_phy_reg(hw, MII_INT_CTRL, 0xC00);
1593 if (ret_val) {
1594 DBG("atl1e: Error enable PHY linkChange Interrupt\n");
1595 return ret_val;
1596 }
1597 /* setup AutoNeg parameters */
1598 ret_val = atl1e_phy_setup_autoneg_adv(hw);
1599 if (ret_val) {
1600 DBG("atl1e: Error Setting up Auto-Negotiation\n");
1601 return ret_val;
1602 }
1603 /* SW.Reset & En-Auto-Neg to restart Auto-Neg*/
1604 DBG("atl1e: Restarting Auto-Neg");
1605 ret_val = atl1e_phy_commit(hw);
1606 if (ret_val) {
1607 DBG("atl1e: Error Resetting the phy");
1608 return ret_val;
1609 }
1610
1611 hw->phy_configured = 1;
1612
1613 return 0;
1614 }
1615
1616 /*
1617 * Reset the transmit and receive units; mask and clear all interrupts.
1618 * hw - Struct containing variables accessed by shared code
1619 * return : 0 or idle status (if error)
1620 */
1621 int atl1e_reset_hw(struct atl1e_hw *hw)
1622 {
1623 struct atl1e_adapter *adapter = hw->adapter;
1624 struct pci_device *pdev = adapter->pdev;
1625 int timeout = 0;
1626 u32 idle_status_data = 0;
1627 u16 pci_cfg_cmd_word = 0;
1628
1629 /* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
1630 pci_read_config_word(pdev, PCI_COMMAND, &pci_cfg_cmd_word);
1631 if ((pci_cfg_cmd_word & (PCI_COMMAND_IO | PCI_COMMAND_MEM |
1632 PCI_COMMAND_MASTER))
1633 != (PCI_COMMAND_IO | PCI_COMMAND_MEM |
1634 PCI_COMMAND_MASTER)) {
1635 pci_cfg_cmd_word |= (PCI_COMMAND_IO | PCI_COMMAND_MEM |
1636 PCI_COMMAND_MASTER);
1637 pci_write_config_word(pdev, PCI_COMMAND, pci_cfg_cmd_word);
1638 }
1639
1640 /*
1641 * Issue Soft Reset to the MAC. This will reset the chip's
1642 * transmit, receive, DMA. It will not effect
1643 * the current PCI configuration. The global reset bit is self-
1644 * clearing, and should clear within a microsecond.
1645 */
1646 AT_WRITE_REG(hw, REG_MASTER_CTRL,
1647 MASTER_CTRL_LED_MODE | MASTER_CTRL_SOFT_RST);
1648 wmb();
1649 mdelay(1);
1650
1651 /* Wait at least 10ms for All module to be Idle */
1652 for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
1653 idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS);
1654 if (idle_status_data == 0)
1655 break;
1656 mdelay(1);
1657 }
1658
1659 if (timeout >= AT_HW_MAX_IDLE_DELAY) {
1660 DBG("atl1e: MAC reset timeout\n");
1661 return AT_ERR_TIMEOUT;
1662 }
1663
1664 return 0;
1665 }
1666
1667
1668 /*
1669 * Performs basic configuration of the adapter.
1670 *
1671 * hw - Struct containing variables accessed by shared code
1672 * Assumes that the controller has previously been reset and is in a
1673 * post-reset uninitialized state. Initializes multicast table,
1674 * and Calls routines to setup link
1675 * Leaves the transmit and receive units disabled and uninitialized.
1676 */
1677 int atl1e_init_hw(struct atl1e_hw *hw)
1678 {
1679 s32 ret_val = 0;
1680
1681 atl1e_init_pcie(hw);
1682
1683 /* Zero out the Multicast HASH table */
1684 /* clear the old settings from the multicast hash table */
1685 AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
1686 AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
1687
1688 ret_val = atl1e_phy_init(hw);
1689
1690 return ret_val;
1691 }
1692
1693 /*
1694 * Detects the current speed and duplex settings of the hardware.
1695 *
1696 * hw - Struct containing variables accessed by shared code
1697 * speed - Speed of the connection
1698 * duplex - Duplex setting of the connection
1699 */
1700 int atl1e_get_speed_and_duplex(struct atl1e_hw *hw, u16 *speed, u16 *duplex)
1701 {
1702 int err;
1703 u16 phy_data;
1704
1705 /* Read PHY Specific Status Register (17) */
1706 err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
1707 if (err)
1708 return err;
1709
1710 if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
1711 return AT_ERR_PHY_RES;
1712
1713 switch (phy_data & MII_AT001_PSSR_SPEED) {
1714 case MII_AT001_PSSR_1000MBS:
1715 *speed = SPEED_1000;
1716 break;
1717 case MII_AT001_PSSR_100MBS:
1718 *speed = SPEED_100;
1719 break;
1720 case MII_AT001_PSSR_10MBS:
1721 *speed = SPEED_10;
1722 break;
1723 default:
1724 return AT_ERR_PHY_SPEED;
1725 break;
1726 }
1727
1728 if (phy_data & MII_AT001_PSSR_DPLX)
1729 *duplex = FULL_DUPLEX;
1730 else
1731 *duplex = HALF_DUPLEX;
1732
1733 return 0;
1734 }
1735
1736 int atl1e_restart_autoneg(struct atl1e_hw *hw)
1737 {
1738 int err = 0;
1739
1740 err = atl1e_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1741 if (err)
1742 return err;
1743
1744 if (hw->nic_type == athr_l1e || hw->nic_type == athr_l2e_revA) {
1745 err = atl1e_write_phy_reg(hw, MII_AT001_CR,
1746 hw->mii_1000t_ctrl_reg);
1747 if (err)
1748 return err;
1749 }
1750
1751 err = atl1e_write_phy_reg(hw, MII_BMCR,
1752 MII_CR_RESET | MII_CR_AUTO_NEG_EN |
1753 MII_CR_RESTART_AUTO_NEG);
1754 return err;
1755 }
1756