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Make gpxe build.
[gpxe/hramrach.git] / src / drivers / net / e1000 / e1000_mac.c
blob235138798168d1fc24dddc14c9de61ad27b0da75
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 FILE_LICENCE ( GPL2_OR_LATER );
30
31 #include "e1000_api.h"
32
33 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
34 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
35
36 /**
37 * e1000_init_mac_ops_generic - Initialize MAC function pointers
38 * @hw: pointer to the HW structure
39 *
40 * Setups up the function pointers to no-op functions
41 **/
42 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
43 {
44 struct e1000_mac_info *mac = &hw->mac;
45 DEBUGFUNC("e1000_init_mac_ops_generic");
46
47 /* General Setup */
48 mac->ops.init_params = e1000_null_ops_generic;
49 mac->ops.init_hw = e1000_null_ops_generic;
50 mac->ops.reset_hw = e1000_null_ops_generic;
51 mac->ops.setup_physical_interface = e1000_null_ops_generic;
52 mac->ops.get_bus_info = e1000_null_ops_generic;
53 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
54 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
55 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
56 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
57 /* LED */
58 mac->ops.cleanup_led = e1000_null_ops_generic;
59 mac->ops.setup_led = e1000_null_ops_generic;
60 mac->ops.blink_led = e1000_null_ops_generic;
61 mac->ops.led_on = e1000_null_ops_generic;
62 mac->ops.led_off = e1000_null_ops_generic;
63 /* LINK */
64 mac->ops.setup_link = e1000_null_ops_generic;
65 mac->ops.get_link_up_info = e1000_null_link_info;
66 mac->ops.check_for_link = e1000_null_ops_generic;
67 mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
68 #if 0
69 /* Management */
70 mac->ops.check_mng_mode = e1000_null_mng_mode;
71 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
72 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
73 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
74 #endif
75 /* VLAN, MC, etc. */
76 mac->ops.update_mc_addr_list = e1000_null_update_mc;
77 mac->ops.clear_vfta = e1000_null_mac_generic;
78 mac->ops.write_vfta = e1000_null_write_vfta;
79 mac->ops.mta_set = e1000_null_mta_set;
80 mac->ops.rar_set = e1000_rar_set_generic;
81 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
82 }
83
84 /**
85 * e1000_null_ops_generic - No-op function, returns 0
86 * @hw: pointer to the HW structure
87 **/
88 s32 e1000_null_ops_generic(struct e1000_hw *hw __unused)
89 {
90 DEBUGFUNC("e1000_null_ops_generic");
91 return E1000_SUCCESS;
92 }
93
94 /**
95 * e1000_null_mac_generic - No-op function, return void
96 * @hw: pointer to the HW structure
97 **/
98 void e1000_null_mac_generic(struct e1000_hw *hw __unused)
99 {
100 DEBUGFUNC("e1000_null_mac_generic");
101 return;
102 }
103
104 /**
105 * e1000_null_link_info - No-op function, return 0
106 * @hw: pointer to the HW structure
107 **/
108 s32 e1000_null_link_info(struct e1000_hw *hw __unused,
109 u16 *s __unused, u16 *d __unused)
110 {
111 DEBUGFUNC("e1000_null_link_info");
112 return E1000_SUCCESS;
113 }
114
115 /**
116 * e1000_null_mng_mode - No-op function, return false
117 * @hw: pointer to the HW structure
118 **/
119 bool e1000_null_mng_mode(struct e1000_hw *hw __unused)
120 {
121 DEBUGFUNC("e1000_null_mng_mode");
122 return false;
123 }
124
125 /**
126 * e1000_null_update_mc - No-op function, return void
127 * @hw: pointer to the HW structure
128 **/
129 void e1000_null_update_mc(struct e1000_hw *hw __unused,
130 u8 *h __unused, u32 a __unused)
131 {
132 DEBUGFUNC("e1000_null_update_mc");
133 return;
134 }
135
136 /**
137 * e1000_null_write_vfta - No-op function, return void
138 * @hw: pointer to the HW structure
139 **/
140 void e1000_null_write_vfta(struct e1000_hw *hw __unused,
141 u32 a __unused, u32 b __unused)
142 {
143 DEBUGFUNC("e1000_null_write_vfta");
144 return;
145 }
146
147 /**
148 * e1000_null_set_mta - No-op function, return void
149 * @hw: pointer to the HW structure
150 **/
151 void e1000_null_mta_set(struct e1000_hw *hw __unused, u32 a __unused)
152 {
153 DEBUGFUNC("e1000_null_mta_set");
154 return;
155 }
156
157 /**
158 * e1000_null_rar_set - No-op function, return void
159 * @hw: pointer to the HW structure
160 **/
161 void e1000_null_rar_set(struct e1000_hw *hw __unused, u8 *h __unused,
162 u32 a __unused)
163 {
164 DEBUGFUNC("e1000_null_rar_set");
165 return;
166 }
167
168 /**
169 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
170 * @hw: pointer to the HW structure
171 *
172 * Determines and stores the system bus information for a particular
173 * network interface. The following bus information is determined and stored:
174 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
175 **/
176 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw __unused)
177 {
178 #if 0
179 struct e1000_mac_info *mac = &hw->mac;
180 struct e1000_bus_info *bus = &hw->bus;
181 u32 status = E1000_READ_REG(hw, E1000_STATUS);
182 s32 ret_val = E1000_SUCCESS;
183
184 DEBUGFUNC("e1000_get_bus_info_pci_generic");
185
186 /* PCI or PCI-X? */
187 bus->type = (status & E1000_STATUS_PCIX_MODE)
188 ? e1000_bus_type_pcix
189 : e1000_bus_type_pci;
190
191 /* Bus speed */
192 if (bus->type == e1000_bus_type_pci) {
193 bus->speed = (status & E1000_STATUS_PCI66)
194 ? e1000_bus_speed_66
195 : e1000_bus_speed_33;
196 } else {
197 switch (status & E1000_STATUS_PCIX_SPEED) {
198 case E1000_STATUS_PCIX_SPEED_66:
199 bus->speed = e1000_bus_speed_66;
200 break;
201 case E1000_STATUS_PCIX_SPEED_100:
202 bus->speed = e1000_bus_speed_100;
203 break;
204 case E1000_STATUS_PCIX_SPEED_133:
205 bus->speed = e1000_bus_speed_133;
206 break;
207 default:
208 bus->speed = e1000_bus_speed_reserved;
209 break;
210 }
211 }
212
213 /* Bus width */
214 bus->width = (status & E1000_STATUS_BUS64)
215 ? e1000_bus_width_64
216 : e1000_bus_width_32;
217
218 /* Which PCI(-X) function? */
219 mac->ops.set_lan_id(hw);
220
221 return ret_val;
222 #endif
223 return 0;
224 }
225
226 /**
227 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
228 * @hw: pointer to the HW structure
229 *
230 * Determines and stores the system bus information for a particular
231 * network interface. The following bus information is determined and stored:
232 * bus speed, bus width, type (PCIe), and PCIe function.
233 **/
234 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw __unused)
235 {
236 #if 0
237 struct e1000_mac_info *mac = &hw->mac;
238 struct e1000_bus_info *bus = &hw->bus;
239
240 s32 ret_val;
241 u16 pcie_link_status;
242
243 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
244
245 bus->type = e1000_bus_type_pci_express;
246 bus->speed = e1000_bus_speed_2500;
247
248 ret_val = e1000_read_pcie_cap_reg(hw,
249 PCIE_LINK_STATUS,
250 &pcie_link_status);
251 if (ret_val)
252 bus->width = e1000_bus_width_unknown;
253 else
254 bus->width = (enum e1000_bus_width)((pcie_link_status &
255 PCIE_LINK_WIDTH_MASK) >>
256 PCIE_LINK_WIDTH_SHIFT);
257
258 mac->ops.set_lan_id(hw);
259
260 return E1000_SUCCESS;
261 #endif
262 return 0;
263 }
264
265 /**
266 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
267 *
268 * @hw: pointer to the HW structure
269 *
270 * Determines the LAN function id by reading memory-mapped registers
271 * and swaps the port value if requested.
272 **/
273 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
274 {
275 struct e1000_bus_info *bus = &hw->bus;
276 u32 reg;
277
278 /*
279 * The status register reports the correct function number
280 * for the device regardless of function swap state.
281 */
282 reg = E1000_READ_REG(hw, E1000_STATUS);
283 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
284 }
285
286 /**
287 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
288 * @hw: pointer to the HW structure
289 *
290 * Determines the LAN function id by reading PCI config space.
291 **/
292 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
293 {
294 struct e1000_bus_info *bus = &hw->bus;
295 u16 pci_header_type;
296 u32 status;
297
298 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
299 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
300 status = E1000_READ_REG(hw, E1000_STATUS);
301 bus->func = (status & E1000_STATUS_FUNC_MASK)
302 >> E1000_STATUS_FUNC_SHIFT;
303 } else {
304 bus->func = 0;
305 }
306 }
307
308 /**
309 * e1000_set_lan_id_single_port - Set LAN id for a single port device
310 * @hw: pointer to the HW structure
311 *
312 * Sets the LAN function id to zero for a single port device.
313 **/
314 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
315 {
316 struct e1000_bus_info *bus = &hw->bus;
317
318 bus->func = 0;
319 }
320
321 /**
322 * e1000_clear_vfta_generic - Clear VLAN filter table
323 * @hw: pointer to the HW structure
324 *
325 * Clears the register array which contains the VLAN filter table by
326 * setting all the values to 0.
327 **/
328 void e1000_clear_vfta_generic(struct e1000_hw *hw)
329 {
330 u32 offset;
331
332 DEBUGFUNC("e1000_clear_vfta_generic");
333
334 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
335 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
336 E1000_WRITE_FLUSH(hw);
337 }
338 }
339
340 /**
341 * e1000_write_vfta_generic - Write value to VLAN filter table
342 * @hw: pointer to the HW structure
343 * @offset: register offset in VLAN filter table
344 * @value: register value written to VLAN filter table
345 *
346 * Writes value at the given offset in the register array which stores
347 * the VLAN filter table.
348 **/
349 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
350 {
351 DEBUGFUNC("e1000_write_vfta_generic");
352
353 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
354 E1000_WRITE_FLUSH(hw);
355 }
356
357 /**
358 * e1000_init_rx_addrs_generic - Initialize receive address's
359 * @hw: pointer to the HW structure
360 * @rar_count: receive address registers
361 *
362 * Setups the receive address registers by setting the base receive address
363 * register to the devices MAC address and clearing all the other receive
364 * address registers to 0.
365 **/
366 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
367 {
368 u32 i;
369 u8 mac_addr[ETH_ADDR_LEN] = {0};
370
371 DEBUGFUNC("e1000_init_rx_addrs_generic");
372
373 /* Setup the receive address */
374 DEBUGOUT("Programming MAC Address into RAR[0]\n");
375
376 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
377
378 /* Zero out the other (rar_entry_count - 1) receive addresses */
379 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
380 for (i = 1; i < rar_count; i++)
381 hw->mac.ops.rar_set(hw, mac_addr, i);
382 }
383
384 /**
385 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
386 * @hw: pointer to the HW structure
387 *
388 * Checks the nvm for an alternate MAC address. An alternate MAC address
389 * can be setup by pre-boot software and must be treated like a permanent
390 * address and must override the actual permanent MAC address. If an
391 * alternate MAC address is found it is programmed into RAR0, replacing
392 * the permanent address that was installed into RAR0 by the Si on reset.
393 * This function will return SUCCESS unless it encounters an error while
394 * reading the EEPROM.
395 **/
396 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
397 {
398 u32 i;
399 s32 ret_val = E1000_SUCCESS;
400 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
401 u8 alt_mac_addr[ETH_ADDR_LEN];
402
403 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
404
405 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
406 &nvm_alt_mac_addr_offset);
407 if (ret_val) {
408 DEBUGOUT("NVM Read Error\n");
409 goto out;
410 }
411
412 if (nvm_alt_mac_addr_offset == 0xFFFF) {
413 /* There is no Alternate MAC Address */
414 goto out;
415 }
416
417 if (hw->bus.func == E1000_FUNC_1)
418 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
419 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
420 offset = nvm_alt_mac_addr_offset + (i >> 1);
421 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
422 if (ret_val) {
423 DEBUGOUT("NVM Read Error\n");
424 goto out;
425 }
426
427 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
428 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
429 }
430
431 /* if multicast bit is set, the alternate address will not be used */
432 if (alt_mac_addr[0] & 0x01) {
433 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
434 goto out;
435 }
436
437 /*
438 * We have a valid alternate MAC address, and we want to treat it the
439 * same as the normal permanent MAC address stored by the HW into the
440 * RAR. Do this by mapping this address into RAR0.
441 */
442 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
443
444 out:
445 return ret_val;
446 }
447
448 /**
449 * e1000_rar_set_generic - Set receive address register
450 * @hw: pointer to the HW structure
451 * @addr: pointer to the receive address
452 * @index: receive address array register
453 *
454 * Sets the receive address array register at index to the address passed
455 * in by addr.
456 **/
457 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
458 {
459 u32 rar_low, rar_high;
460
461 DEBUGFUNC("e1000_rar_set_generic");
462
463 /*
464 * HW expects these in little endian so we reverse the byte order
465 * from network order (big endian) to little endian
466 */
467 rar_low = ((u32) addr[0] |
468 ((u32) addr[1] << 8) |
469 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
470
471 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
472
473 /* If MAC address zero, no need to set the AV bit */
474 if (rar_low || rar_high)
475 rar_high |= E1000_RAH_AV;
476
477 /*
478 * Some bridges will combine consecutive 32-bit writes into
479 * a single burst write, which will malfunction on some parts.
480 * The flushes avoid this.
481 */
482 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
483 E1000_WRITE_FLUSH(hw);
484 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
485 E1000_WRITE_FLUSH(hw);
486 }
487
488 /**
489 * e1000_mta_set_generic - Set multicast filter table address
490 * @hw: pointer to the HW structure
491 * @hash_value: determines the MTA register and bit to set
492 *
493 * The multicast table address is a register array of 32-bit registers.
494 * The hash_value is used to determine what register the bit is in, the
495 * current value is read, the new bit is OR'd in and the new value is
496 * written back into the register.
497 **/
498 void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value)
499 {
500 u32 hash_bit, hash_reg, mta;
501
502 DEBUGFUNC("e1000_mta_set_generic");
503 /*
504 * The MTA is a register array of 32-bit registers. It is
505 * treated like an array of (32*mta_reg_count) bits. We want to
506 * set bit BitArray[hash_value]. So we figure out what register
507 * the bit is in, read it, OR in the new bit, then write
508 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
509 * mask to bits 31:5 of the hash value which gives us the
510 * register we're modifying. The hash bit within that register
511 * is determined by the lower 5 bits of the hash value.
512 */
513 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
514 hash_bit = hash_value & 0x1F;
515
516 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg);
517
518 mta |= (1 << hash_bit);
519
520 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta);
521 E1000_WRITE_FLUSH(hw);
522 }
523
524 /**
525 * e1000_update_mc_addr_list_generic - Update Multicast addresses
526 * @hw: pointer to the HW structure
527 * @mc_addr_list: array of multicast addresses to program
528 * @mc_addr_count: number of multicast addresses to program
529 *
530 * Updates entire Multicast Table Array.
531 * The caller must have a packed mc_addr_list of multicast addresses.
532 **/
533 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
534 u8 *mc_addr_list, u32 mc_addr_count)
535 {
536 u32 hash_value, hash_bit, hash_reg;
537 int i;
538
539 DEBUGFUNC("e1000_update_mc_addr_list_generic");
540
541 /* clear mta_shadow */
542 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
543
544 /* update mta_shadow from mc_addr_list */
545 for (i = 0; (u32) i < mc_addr_count; i++) {
546 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
547
548 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
549 hash_bit = hash_value & 0x1F;
550
551 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
552 mc_addr_list += (ETH_ADDR_LEN);
553 }
554
555 /* replace the entire MTA table */
556 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
557 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
558 E1000_WRITE_FLUSH(hw);
559 }
560
561 /**
562 * e1000_hash_mc_addr_generic - Generate a multicast hash value
563 * @hw: pointer to the HW structure
564 * @mc_addr: pointer to a multicast address
565 *
566 * Generates a multicast address hash value which is used to determine
567 * the multicast filter table array address and new table value. See
568 * e1000_mta_set_generic()
569 **/
570 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
571 {
572 u32 hash_value, hash_mask;
573 u8 bit_shift = 0;
574
575 DEBUGFUNC("e1000_hash_mc_addr_generic");
576
577 /* Register count multiplied by bits per register */
578 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
579
580 /*
581 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
582 * where 0xFF would still fall within the hash mask.
583 */
584 while (hash_mask >> bit_shift != 0xFF)
585 bit_shift++;
586
587 /*
588 * The portion of the address that is used for the hash table
589 * is determined by the mc_filter_type setting.
590 * The algorithm is such that there is a total of 8 bits of shifting.
591 * The bit_shift for a mc_filter_type of 0 represents the number of
592 * left-shifts where the MSB of mc_addr[5] would still fall within
593 * the hash_mask. Case 0 does this exactly. Since there are a total
594 * of 8 bits of shifting, then mc_addr[4] will shift right the
595 * remaining number of bits. Thus 8 - bit_shift. The rest of the
596 * cases are a variation of this algorithm...essentially raising the
597 * number of bits to shift mc_addr[5] left, while still keeping the
598 * 8-bit shifting total.
599 *
600 * For example, given the following Destination MAC Address and an
601 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
602 * we can see that the bit_shift for case 0 is 4. These are the hash
603 * values resulting from each mc_filter_type...
604 * [0] [1] [2] [3] [4] [5]
605 * 01 AA 00 12 34 56
606 * LSB MSB
607 *
608 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
609 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
610 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
611 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
612 */
613 switch (hw->mac.mc_filter_type) {
614 default:
615 case 0:
616 break;
617 case 1:
618 bit_shift += 1;
619 break;
620 case 2:
621 bit_shift += 2;
622 break;
623 case 3:
624 bit_shift += 4;
625 break;
626 }
627
628 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
629 (((u16) mc_addr[5]) << bit_shift)));
630
631 return hash_value;
632 }
633
634 /**
635 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
636 * @hw: pointer to the HW structure
637 *
638 * In certain situations, a system BIOS may report that the PCIx maximum
639 * memory read byte count (MMRBC) value is higher than than the actual
640 * value. We check the PCIx command register with the current PCIx status
641 * register.
642 **/
643 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
644 {
645 u16 cmd_mmrbc;
646 u16 pcix_cmd;
647 u16 pcix_stat_hi_word;
648 u16 stat_mmrbc;
649
650 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
651
652 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
653 if (hw->bus.type != e1000_bus_type_pcix)
654 return;
655
656 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
657 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
658 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
659 PCIX_COMMAND_MMRBC_SHIFT;
660 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
661 PCIX_STATUS_HI_MMRBC_SHIFT;
662 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
663 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
664 if (cmd_mmrbc > stat_mmrbc) {
665 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
666 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
667 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
668 }
669 }
670
671 /**
672 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
673 * @hw: pointer to the HW structure
674 *
675 * Clears the base hardware counters by reading the counter registers.
676 **/
677 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw __unused)
678 {
679 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
680
681 #if 0
682 E1000_READ_REG(hw, E1000_CRCERRS);
683 E1000_READ_REG(hw, E1000_SYMERRS);
684 E1000_READ_REG(hw, E1000_MPC);
685 E1000_READ_REG(hw, E1000_SCC);
686 E1000_READ_REG(hw, E1000_ECOL);
687 E1000_READ_REG(hw, E1000_MCC);
688 E1000_READ_REG(hw, E1000_LATECOL);
689 E1000_READ_REG(hw, E1000_COLC);
690 E1000_READ_REG(hw, E1000_DC);
691 E1000_READ_REG(hw, E1000_SEC);
692 E1000_READ_REG(hw, E1000_RLEC);
693 E1000_READ_REG(hw, E1000_XONRXC);
694 E1000_READ_REG(hw, E1000_XONTXC);
695 E1000_READ_REG(hw, E1000_XOFFRXC);
696 E1000_READ_REG(hw, E1000_XOFFTXC);
697 E1000_READ_REG(hw, E1000_FCRUC);
698 E1000_READ_REG(hw, E1000_GPRC);
699 E1000_READ_REG(hw, E1000_BPRC);
700 E1000_READ_REG(hw, E1000_MPRC);
701 E1000_READ_REG(hw, E1000_GPTC);
702 E1000_READ_REG(hw, E1000_GORCL);
703 E1000_READ_REG(hw, E1000_GORCH);
704 E1000_READ_REG(hw, E1000_GOTCL);
705 E1000_READ_REG(hw, E1000_GOTCH);
706 E1000_READ_REG(hw, E1000_RNBC);
707 E1000_READ_REG(hw, E1000_RUC);
708 E1000_READ_REG(hw, E1000_RFC);
709 E1000_READ_REG(hw, E1000_ROC);
710 E1000_READ_REG(hw, E1000_RJC);
711 E1000_READ_REG(hw, E1000_TORL);
712 E1000_READ_REG(hw, E1000_TORH);
713 E1000_READ_REG(hw, E1000_TOTL);
714 E1000_READ_REG(hw, E1000_TOTH);
715 E1000_READ_REG(hw, E1000_TPR);
716 E1000_READ_REG(hw, E1000_TPT);
717 E1000_READ_REG(hw, E1000_MPTC);
718 E1000_READ_REG(hw, E1000_BPTC);
719 #endif
720 }
721
722 /**
723 * e1000_check_for_copper_link_generic - Check for link (Copper)
724 * @hw: pointer to the HW structure
725 *
726 * Checks to see of the link status of the hardware has changed. If a
727 * change in link status has been detected, then we read the PHY registers
728 * to get the current speed/duplex if link exists.
729 **/
730 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
731 {
732 struct e1000_mac_info *mac = &hw->mac;
733 s32 ret_val;
734 bool link;
735
736 DEBUGFUNC("e1000_check_for_copper_link");
737
738 /*
739 * We only want to go out to the PHY registers to see if Auto-Neg
740 * has completed and/or if our link status has changed. The
741 * get_link_status flag is set upon receiving a Link Status
742 * Change or Rx Sequence Error interrupt.
743 */
744 if (!mac->get_link_status) {
745 ret_val = E1000_SUCCESS;
746 goto out;
747 }
748
749 /*
750 * First we want to see if the MII Status Register reports
751 * link. If so, then we want to get the current speed/duplex
752 * of the PHY.
753 */
754 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
755 if (ret_val)
756 goto out;
757
758 if (!link)
759 goto out; /* No link detected */
760
761 mac->get_link_status = false;
762
763 /*
764 * Check if there was DownShift, must be checked
765 * immediately after link-up
766 */
767 e1000_check_downshift_generic(hw);
768
769 /*
770 * If we are forcing speed/duplex, then we simply return since
771 * we have already determined whether we have link or not.
772 */
773 if (!mac->autoneg) {
774 ret_val = -E1000_ERR_CONFIG;
775 goto out;
776 }
777
778 /*
779 * Auto-Neg is enabled. Auto Speed Detection takes care
780 * of MAC speed/duplex configuration. So we only need to
781 * configure Collision Distance in the MAC.
782 */
783 e1000_config_collision_dist_generic(hw);
784
785 /*
786 * Configure Flow Control now that Auto-Neg has completed.
787 * First, we need to restore the desired flow control
788 * settings because we may have had to re-autoneg with a
789 * different link partner.
790 */
791 ret_val = e1000_config_fc_after_link_up_generic(hw);
792 if (ret_val)
793 DEBUGOUT("Error configuring flow control\n");
794
795 out:
796 return ret_val;
797 }
798
799 /**
800 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
801 * @hw: pointer to the HW structure
802 *
803 * Checks for link up on the hardware. If link is not up and we have
804 * a signal, then we need to force link up.
805 **/
806 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
807 {
808 struct e1000_mac_info *mac = &hw->mac;
809 u32 rxcw;
810 u32 ctrl;
811 u32 status;
812 s32 ret_val = E1000_SUCCESS;
813
814 DEBUGFUNC("e1000_check_for_fiber_link_generic");
815
816 ctrl = E1000_READ_REG(hw, E1000_CTRL);
817 status = E1000_READ_REG(hw, E1000_STATUS);
818 rxcw = E1000_READ_REG(hw, E1000_RXCW);
819
820 /*
821 * If we don't have link (auto-negotiation failed or link partner
822 * cannot auto-negotiate), the cable is plugged in (we have signal),
823 * and our link partner is not trying to auto-negotiate with us (we
824 * are receiving idles or data), we need to force link up. We also
825 * need to give auto-negotiation time to complete, in case the cable
826 * was just plugged in. The autoneg_failed flag does this.
827 */
828 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
829 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
830 (!(rxcw & E1000_RXCW_C))) {
831 if (mac->autoneg_failed == 0) {
832 mac->autoneg_failed = 1;
833 goto out;
834 }
835 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
836
837 /* Disable auto-negotiation in the TXCW register */
838 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
839
840 /* Force link-up and also force full-duplex. */
841 ctrl = E1000_READ_REG(hw, E1000_CTRL);
842 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
843 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
844
845 /* Configure Flow Control after forcing link up. */
846 ret_val = e1000_config_fc_after_link_up_generic(hw);
847 if (ret_val) {
848 DEBUGOUT("Error configuring flow control\n");
849 goto out;
850 }
851 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
852 /*
853 * If we are forcing link and we are receiving /C/ ordered
854 * sets, re-enable auto-negotiation in the TXCW register
855 * and disable forced link in the Device Control register
856 * in an attempt to auto-negotiate with our link partner.
857 */
858 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
859 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
860 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
861
862 mac->serdes_has_link = true;
863 }
864
865 out:
866 return ret_val;
867 }
868
869 /**
870 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
871 * @hw: pointer to the HW structure
872 *
873 * Checks for link up on the hardware. If link is not up and we have
874 * a signal, then we need to force link up.
875 **/
876 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
877 {
878 struct e1000_mac_info *mac = &hw->mac;
879 u32 rxcw;
880 u32 ctrl;
881 u32 status;
882 s32 ret_val = E1000_SUCCESS;
883
884 DEBUGFUNC("e1000_check_for_serdes_link_generic");
885
886 ctrl = E1000_READ_REG(hw, E1000_CTRL);
887 status = E1000_READ_REG(hw, E1000_STATUS);
888 rxcw = E1000_READ_REG(hw, E1000_RXCW);
889
890 /*
891 * If we don't have link (auto-negotiation failed or link partner
892 * cannot auto-negotiate), and our link partner is not trying to
893 * auto-negotiate with us (we are receiving idles or data),
894 * we need to force link up. We also need to give auto-negotiation
895 * time to complete.
896 */
897 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
898 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
899 if (mac->autoneg_failed == 0) {
900 mac->autoneg_failed = 1;
901 goto out;
902 }
903 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
904
905 /* Disable auto-negotiation in the TXCW register */
906 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
907
908 /* Force link-up and also force full-duplex. */
909 ctrl = E1000_READ_REG(hw, E1000_CTRL);
910 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
911 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
912
913 /* Configure Flow Control after forcing link up. */
914 ret_val = e1000_config_fc_after_link_up_generic(hw);
915 if (ret_val) {
916 DEBUGOUT("Error configuring flow control\n");
917 goto out;
918 }
919 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
920 /*
921 * If we are forcing link and we are receiving /C/ ordered
922 * sets, re-enable auto-negotiation in the TXCW register
923 * and disable forced link in the Device Control register
924 * in an attempt to auto-negotiate with our link partner.
925 */
926 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
927 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
928 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
929
930 mac->serdes_has_link = true;
931 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
932 /*
933 * If we force link for non-auto-negotiation switch, check
934 * link status based on MAC synchronization for internal
935 * serdes media type.
936 */
937 /* SYNCH bit and IV bit are sticky. */
938 usec_delay(10);
939 rxcw = E1000_READ_REG(hw, E1000_RXCW);
940 if (rxcw & E1000_RXCW_SYNCH) {
941 if (!(rxcw & E1000_RXCW_IV)) {
942 mac->serdes_has_link = true;
943 DEBUGOUT("SERDES: Link up - forced.\n");
944 }
945 } else {
946 mac->serdes_has_link = false;
947 DEBUGOUT("SERDES: Link down - force failed.\n");
948 }
949 }
950
951 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
952 status = E1000_READ_REG(hw, E1000_STATUS);
953 if (status & E1000_STATUS_LU) {
954 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
955 usec_delay(10);
956 rxcw = E1000_READ_REG(hw, E1000_RXCW);
957 if (rxcw & E1000_RXCW_SYNCH) {
958 if (!(rxcw & E1000_RXCW_IV)) {
959 mac->serdes_has_link = true;
960 DEBUGOUT("SERDES: Link up - autoneg "
961 "completed sucessfully.\n");
962 } else {
963 mac->serdes_has_link = false;
964 DEBUGOUT("SERDES: Link down - invalid"
965 "codewords detected in autoneg.\n");
966 }
967 } else {
968 mac->serdes_has_link = false;
969 DEBUGOUT("SERDES: Link down - no sync.\n");
970 }
971 } else {
972 mac->serdes_has_link = false;
973 DEBUGOUT("SERDES: Link down - autoneg failed\n");
974 }
975 }
976
977 out:
978 return ret_val;
979 }
980
981 /**
982 * e1000_setup_link_generic - Setup flow control and link settings
983 * @hw: pointer to the HW structure
984 *
985 * Determines which flow control settings to use, then configures flow
986 * control. Calls the appropriate media-specific link configuration
987 * function. Assuming the adapter has a valid link partner, a valid link
988 * should be established. Assumes the hardware has previously been reset
989 * and the transmitter and receiver are not enabled.
990 **/
991 s32 e1000_setup_link_generic(struct e1000_hw *hw)
992 {
993 s32 ret_val = E1000_SUCCESS;
994
995 DEBUGFUNC("e1000_setup_link_generic");
996
997 /*
998 * In the case of the phy reset being blocked, we already have a link.
999 * We do not need to set it up again.
1000 */
1001 if (hw->phy.ops.check_reset_block)
1002 if (hw->phy.ops.check_reset_block(hw))
1003 goto out;
1004
1005 /*
1006 * If requested flow control is set to default, set flow control
1007 * based on the EEPROM flow control settings.
1008 */
1009 if (hw->fc.requested_mode == e1000_fc_default) {
1010 ret_val = e1000_set_default_fc_generic(hw);
1011 if (ret_val)
1012 goto out;
1013 }
1014
1015 /*
1016 * Save off the requested flow control mode for use later. Depending
1017 * on the link partner's capabilities, we may or may not use this mode.
1018 */
1019 hw->fc.current_mode = hw->fc.requested_mode;
1020
1021 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
1022 hw->fc.current_mode);
1023
1024 /* Call the necessary media_type subroutine to configure the link. */
1025 ret_val = hw->mac.ops.setup_physical_interface(hw);
1026 if (ret_val)
1027 goto out;
1028
1029 /*
1030 * Initialize the flow control address, type, and PAUSE timer
1031 * registers to their default values. This is done even if flow
1032 * control is disabled, because it does not hurt anything to
1033 * initialize these registers.
1034 */
1035 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1036 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1037 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1038 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1039
1040 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1041
1042 ret_val = e1000_set_fc_watermarks_generic(hw);
1043
1044 out:
1045 return ret_val;
1046 }
1047
1048 /**
1049 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1050 * @hw: pointer to the HW structure
1051 *
1052 * Configures collision distance and flow control for fiber and serdes
1053 * links. Upon successful setup, poll for link.
1054 **/
1055 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1056 {
1057 u32 ctrl;
1058 s32 ret_val = E1000_SUCCESS;
1059
1060 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1061
1062 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1063
1064 /* Take the link out of reset */
1065 ctrl &= ~E1000_CTRL_LRST;
1066
1067 e1000_config_collision_dist_generic(hw);
1068
1069 ret_val = e1000_commit_fc_settings_generic(hw);
1070 if (ret_val)
1071 goto out;
1072
1073 /*
1074 * Since auto-negotiation is enabled, take the link out of reset (the
1075 * link will be in reset, because we previously reset the chip). This
1076 * will restart auto-negotiation. If auto-negotiation is successful
1077 * then the link-up status bit will be set and the flow control enable
1078 * bits (RFCE and TFCE) will be set according to their negotiated value.
1079 */
1080 DEBUGOUT("Auto-negotiation enabled\n");
1081
1082 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1083 E1000_WRITE_FLUSH(hw);
1084 msec_delay(1);
1085
1086 /*
1087 * For these adapters, the SW definable pin 1 is set when the optics
1088 * detect a signal. If we have a signal, then poll for a "Link-Up"
1089 * indication.
1090 */
1091 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1092 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1093 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1094 } else {
1095 DEBUGOUT("No signal detected\n");
1096 }
1097
1098 out:
1099 return ret_val;
1100 }
1101
1102 /**
1103 * e1000_config_collision_dist_generic - Configure collision distance
1104 * @hw: pointer to the HW structure
1105 *
1106 * Configures the collision distance to the default value and is used
1107 * during link setup. Currently no func pointer exists and all
1108 * implementations are handled in the generic version of this function.
1109 **/
1110 void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1111 {
1112 u32 tctl;
1113
1114 DEBUGFUNC("e1000_config_collision_dist_generic");
1115
1116 tctl = E1000_READ_REG(hw, E1000_TCTL);
1117
1118 tctl &= ~E1000_TCTL_COLD;
1119 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1120
1121 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1122 E1000_WRITE_FLUSH(hw);
1123 }
1124
1125 /**
1126 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1127 * @hw: pointer to the HW structure
1128 *
1129 * Polls for link up by reading the status register, if link fails to come
1130 * up with auto-negotiation, then the link is forced if a signal is detected.
1131 **/
1132 s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1133 {
1134 struct e1000_mac_info *mac = &hw->mac;
1135 u32 i, status;
1136 s32 ret_val = E1000_SUCCESS;
1137
1138 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1139
1140 /*
1141 * If we have a signal (the cable is plugged in, or assumed true for
1142 * serdes media) then poll for a "Link-Up" indication in the Device
1143 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1144 * seconds (Auto-negotiation should complete in less than 500
1145 * milliseconds even if the other end is doing it in SW).
1146 */
1147 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1148 msec_delay(10);
1149 status = E1000_READ_REG(hw, E1000_STATUS);
1150 if (status & E1000_STATUS_LU)
1151 break;
1152 }
1153 if (i == FIBER_LINK_UP_LIMIT) {
1154 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1155 mac->autoneg_failed = 1;
1156 /*
1157 * AutoNeg failed to achieve a link, so we'll call
1158 * mac->check_for_link. This routine will force the
1159 * link up if we detect a signal. This will allow us to
1160 * communicate with non-autonegotiating link partners.
1161 */
1162 ret_val = hw->mac.ops.check_for_link(hw);
1163 if (ret_val) {
1164 DEBUGOUT("Error while checking for link\n");
1165 goto out;
1166 }
1167 mac->autoneg_failed = 0;
1168 } else {
1169 mac->autoneg_failed = 0;
1170 DEBUGOUT("Valid Link Found\n");
1171 }
1172
1173 out:
1174 return ret_val;
1175 }
1176
1177 /**
1178 * e1000_commit_fc_settings_generic - Configure flow control
1179 * @hw: pointer to the HW structure
1180 *
1181 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1182 * base on the flow control settings in e1000_mac_info.
1183 **/
1184 s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1185 {
1186 struct e1000_mac_info *mac = &hw->mac;
1187 u32 txcw;
1188 s32 ret_val = E1000_SUCCESS;
1189
1190 DEBUGFUNC("e1000_commit_fc_settings_generic");
1191
1192 /*
1193 * Check for a software override of the flow control settings, and
1194 * setup the device accordingly. If auto-negotiation is enabled, then
1195 * software will have to set the "PAUSE" bits to the correct value in
1196 * the Transmit Config Word Register (TXCW) and re-start auto-
1197 * negotiation. However, if auto-negotiation is disabled, then
1198 * software will have to manually configure the two flow control enable
1199 * bits in the CTRL register.
1200 *
1201 * The possible values of the "fc" parameter are:
1202 * 0: Flow control is completely disabled
1203 * 1: Rx flow control is enabled (we can receive pause frames,
1204 * but not send pause frames).
1205 * 2: Tx flow control is enabled (we can send pause frames but we
1206 * do not support receiving pause frames).
1207 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1208 */
1209 switch (hw->fc.current_mode) {
1210 case e1000_fc_none:
1211 /* Flow control completely disabled by a software over-ride. */
1212 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1213 break;
1214 case e1000_fc_rx_pause:
1215 /*
1216 * Rx Flow control is enabled and Tx Flow control is disabled
1217 * by a software over-ride. Since there really isn't a way to
1218 * advertise that we are capable of Rx Pause ONLY, we will
1219 * advertise that we support both symmetric and asymmetric RX
1220 * PAUSE. Later, we will disable the adapter's ability to send
1221 * PAUSE frames.
1222 */
1223 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1224 break;
1225 case e1000_fc_tx_pause:
1226 /*
1227 * Tx Flow control is enabled, and Rx Flow control is disabled,
1228 * by a software over-ride.
1229 */
1230 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1231 break;
1232 case e1000_fc_full:
1233 /*
1234 * Flow control (both Rx and Tx) is enabled by a software
1235 * over-ride.
1236 */
1237 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1238 break;
1239 default:
1240 DEBUGOUT("Flow control param set incorrectly\n");
1241 ret_val = -E1000_ERR_CONFIG;
1242 goto out;
1243 break;
1244 }
1245
1246 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1247 mac->txcw = txcw;
1248
1249 out:
1250 return ret_val;
1251 }
1252
1253 /**
1254 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1255 * @hw: pointer to the HW structure
1256 *
1257 * Sets the flow control high/low threshold (watermark) registers. If
1258 * flow control XON frame transmission is enabled, then set XON frame
1259 * transmission as well.
1260 **/
1261 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1262 {
1263 s32 ret_val = E1000_SUCCESS;
1264 u32 fcrtl = 0, fcrth = 0;
1265
1266 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1267
1268 /*
1269 * Set the flow control receive threshold registers. Normally,
1270 * these registers will be set to a default threshold that may be
1271 * adjusted later by the driver's runtime code. However, if the
1272 * ability to transmit pause frames is not enabled, then these
1273 * registers will be set to 0.
1274 */
1275 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1276 /*
1277 * We need to set up the Receive Threshold high and low water
1278 * marks as well as (optionally) enabling the transmission of
1279 * XON frames.
1280 */
1281 fcrtl = hw->fc.low_water;
1282 if (hw->fc.send_xon)
1283 fcrtl |= E1000_FCRTL_XONE;
1284
1285 fcrth = hw->fc.high_water;
1286 }
1287 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1288 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1289
1290 return ret_val;
1291 }
1292
1293 /**
1294 * e1000_set_default_fc_generic - Set flow control default values
1295 * @hw: pointer to the HW structure
1296 *
1297 * Read the EEPROM for the default values for flow control and store the
1298 * values.
1299 **/
1300 s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
1301 {
1302 s32 ret_val = E1000_SUCCESS;
1303 u16 nvm_data;
1304
1305 DEBUGFUNC("e1000_set_default_fc_generic");
1306
1307 /*
1308 * Read and store word 0x0F of the EEPROM. This word contains bits
1309 * that determine the hardware's default PAUSE (flow control) mode,
1310 * a bit that determines whether the HW defaults to enabling or
1311 * disabling auto-negotiation, and the direction of the
1312 * SW defined pins. If there is no SW over-ride of the flow
1313 * control setting, then the variable hw->fc will
1314 * be initialized based on a value in the EEPROM.
1315 */
1316 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1317
1318 if (ret_val) {
1319 DEBUGOUT("NVM Read Error\n");
1320 goto out;
1321 }
1322
1323 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
1324 hw->fc.requested_mode = e1000_fc_none;
1325 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
1326 NVM_WORD0F_ASM_DIR)
1327 hw->fc.requested_mode = e1000_fc_tx_pause;
1328 else
1329 hw->fc.requested_mode = e1000_fc_full;
1330
1331 out:
1332 return ret_val;
1333 }
1334
1335 /**
1336 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1337 * @hw: pointer to the HW structure
1338 *
1339 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1340 * device control register to reflect the adapter settings. TFCE and RFCE
1341 * need to be explicitly set by software when a copper PHY is used because
1342 * autonegotiation is managed by the PHY rather than the MAC. Software must
1343 * also configure these bits when link is forced on a fiber connection.
1344 **/
1345 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1346 {
1347 u32 ctrl;
1348 s32 ret_val = E1000_SUCCESS;
1349
1350 DEBUGFUNC("e1000_force_mac_fc_generic");
1351
1352 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1353
1354 /*
1355 * Because we didn't get link via the internal auto-negotiation
1356 * mechanism (we either forced link or we got link via PHY
1357 * auto-neg), we have to manually enable/disable transmit an
1358 * receive flow control.
1359 *
1360 * The "Case" statement below enables/disable flow control
1361 * according to the "hw->fc.current_mode" parameter.
1362 *
1363 * The possible values of the "fc" parameter are:
1364 * 0: Flow control is completely disabled
1365 * 1: Rx flow control is enabled (we can receive pause
1366 * frames but not send pause frames).
1367 * 2: Tx flow control is enabled (we can send pause frames
1368 * frames but we do not receive pause frames).
1369 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1370 * other: No other values should be possible at this point.
1371 */
1372 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1373
1374 switch (hw->fc.current_mode) {
1375 case e1000_fc_none:
1376 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1377 break;
1378 case e1000_fc_rx_pause:
1379 ctrl &= (~E1000_CTRL_TFCE);
1380 ctrl |= E1000_CTRL_RFCE;
1381 break;
1382 case e1000_fc_tx_pause:
1383 ctrl &= (~E1000_CTRL_RFCE);
1384 ctrl |= E1000_CTRL_TFCE;
1385 break;
1386 case e1000_fc_full:
1387 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1388 break;
1389 default:
1390 DEBUGOUT("Flow control param set incorrectly\n");
1391 ret_val = -E1000_ERR_CONFIG;
1392 goto out;
1393 }
1394
1395 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1396
1397 out:
1398 return ret_val;
1399 }
1400
1401 /**
1402 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1403 * @hw: pointer to the HW structure
1404 *
1405 * Checks the status of auto-negotiation after link up to ensure that the
1406 * speed and duplex were not forced. If the link needed to be forced, then
1407 * flow control needs to be forced also. If auto-negotiation is enabled
1408 * and did not fail, then we configure flow control based on our link
1409 * partner.
1410 **/
1411 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1412 {
1413 struct e1000_mac_info *mac = &hw->mac;
1414 s32 ret_val = E1000_SUCCESS;
1415 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1416 u16 speed, duplex;
1417
1418 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1419
1420 /*
1421 * Check for the case where we have fiber media and auto-neg failed
1422 * so we had to force link. In this case, we need to force the
1423 * configuration of the MAC to match the "fc" parameter.
1424 */
1425 if (mac->autoneg_failed) {
1426 if (hw->phy.media_type == e1000_media_type_fiber ||
1427 hw->phy.media_type == e1000_media_type_internal_serdes)
1428 ret_val = e1000_force_mac_fc_generic(hw);
1429 } else {
1430 if (hw->phy.media_type == e1000_media_type_copper)
1431 ret_val = e1000_force_mac_fc_generic(hw);
1432 }
1433
1434 if (ret_val) {
1435 DEBUGOUT("Error forcing flow control settings\n");
1436 goto out;
1437 }
1438
1439 /*
1440 * Check for the case where we have copper media and auto-neg is
1441 * enabled. In this case, we need to check and see if Auto-Neg
1442 * has completed, and if so, how the PHY and link partner has
1443 * flow control configured.
1444 */
1445 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1446 /*
1447 * Read the MII Status Register and check to see if AutoNeg
1448 * has completed. We read this twice because this reg has
1449 * some "sticky" (latched) bits.
1450 */
1451 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1452 if (ret_val)
1453 goto out;
1454 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1455 if (ret_val)
1456 goto out;
1457
1458 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1459 DEBUGOUT("Copper PHY and Auto Neg "
1460 "has not completed.\n");
1461 goto out;
1462 }
1463
1464 /*
1465 * The AutoNeg process has completed, so we now need to
1466 * read both the Auto Negotiation Advertisement
1467 * Register (Address 4) and the Auto_Negotiation Base
1468 * Page Ability Register (Address 5) to determine how
1469 * flow control was negotiated.
1470 */
1471 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1472 &mii_nway_adv_reg);
1473 if (ret_val)
1474 goto out;
1475 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1476 &mii_nway_lp_ability_reg);
1477 if (ret_val)
1478 goto out;
1479
1480 /*
1481 * Two bits in the Auto Negotiation Advertisement Register
1482 * (Address 4) and two bits in the Auto Negotiation Base
1483 * Page Ability Register (Address 5) determine flow control
1484 * for both the PHY and the link partner. The following
1485 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1486 * 1999, describes these PAUSE resolution bits and how flow
1487 * control is determined based upon these settings.
1488 * NOTE: DC = Don't Care
1489 *
1490 * LOCAL DEVICE | LINK PARTNER
1491 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1492 *-------|---------|-------|---------|--------------------
1493 * 0 | 0 | DC | DC | e1000_fc_none
1494 * 0 | 1 | 0 | DC | e1000_fc_none
1495 * 0 | 1 | 1 | 0 | e1000_fc_none
1496 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1497 * 1 | 0 | 0 | DC | e1000_fc_none
1498 * 1 | DC | 1 | DC | e1000_fc_full
1499 * 1 | 1 | 0 | 0 | e1000_fc_none
1500 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1501 *
1502 * Are both PAUSE bits set to 1? If so, this implies
1503 * Symmetric Flow Control is enabled at both ends. The
1504 * ASM_DIR bits are irrelevant per the spec.
1505 *
1506 * For Symmetric Flow Control:
1507 *
1508 * LOCAL DEVICE | LINK PARTNER
1509 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1510 *-------|---------|-------|---------|--------------------
1511 * 1 | DC | 1 | DC | E1000_fc_full
1512 *
1513 */
1514 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1515 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1516 /*
1517 * Now we need to check if the user selected Rx ONLY
1518 * of pause frames. In this case, we had to advertise
1519 * FULL flow control because we could not advertise RX
1520 * ONLY. Hence, we must now check to see if we need to
1521 * turn OFF the TRANSMISSION of PAUSE frames.
1522 */
1523 if (hw->fc.requested_mode == e1000_fc_full) {
1524 hw->fc.current_mode = e1000_fc_full;
1525 DEBUGOUT("Flow Control = FULL.\r\n");
1526 } else {
1527 hw->fc.current_mode = e1000_fc_rx_pause;
1528 DEBUGOUT("Flow Control = "
1529 "RX PAUSE frames only.\r\n");
1530 }
1531 }
1532 /*
1533 * For receiving PAUSE frames ONLY.
1534 *
1535 * LOCAL DEVICE | LINK PARTNER
1536 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1537 *-------|---------|-------|---------|--------------------
1538 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1539 */
1540 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1541 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1542 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1543 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1544 hw->fc.current_mode = e1000_fc_tx_pause;
1545 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1546 }
1547 /*
1548 * For transmitting PAUSE frames ONLY.
1549 *
1550 * LOCAL DEVICE | LINK PARTNER
1551 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1552 *-------|---------|-------|---------|--------------------
1553 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1554 */
1555 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1556 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1557 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1558 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1559 hw->fc.current_mode = e1000_fc_rx_pause;
1560 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1561 } else {
1562 /*
1563 * Per the IEEE spec, at this point flow control
1564 * should be disabled.
1565 */
1566 hw->fc.current_mode = e1000_fc_none;
1567 DEBUGOUT("Flow Control = NONE.\r\n");
1568 }
1569
1570 /*
1571 * Now we need to do one last check... If we auto-
1572 * negotiated to HALF DUPLEX, flow control should not be
1573 * enabled per IEEE 802.3 spec.
1574 */
1575 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1576 if (ret_val) {
1577 DEBUGOUT("Error getting link speed and duplex\n");
1578 goto out;
1579 }
1580
1581 if (duplex == HALF_DUPLEX)
1582 hw->fc.current_mode = e1000_fc_none;
1583
1584 /*
1585 * Now we call a subroutine to actually force the MAC
1586 * controller to use the correct flow control settings.
1587 */
1588 ret_val = e1000_force_mac_fc_generic(hw);
1589 if (ret_val) {
1590 DEBUGOUT("Error forcing flow control settings\n");
1591 goto out;
1592 }
1593 }
1594
1595 out:
1596 return ret_val;
1597 }
1598
1599 /**
1600 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1601 * @hw: pointer to the HW structure
1602 * @speed: stores the current speed
1603 * @duplex: stores the current duplex
1604 *
1605 * Read the status register for the current speed/duplex and store the current
1606 * speed and duplex for copper connections.
1607 **/
1608 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1609 u16 *duplex)
1610 {
1611 u32 status;
1612
1613 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1614
1615 status = E1000_READ_REG(hw, E1000_STATUS);
1616 if (status & E1000_STATUS_SPEED_1000) {
1617 *speed = SPEED_1000;
1618 DEBUGOUT("1000 Mbs, ");
1619 } else if (status & E1000_STATUS_SPEED_100) {
1620 *speed = SPEED_100;
1621 DEBUGOUT("100 Mbs, ");
1622 } else {
1623 *speed = SPEED_10;
1624 DEBUGOUT("10 Mbs, ");
1625 }
1626
1627 if (status & E1000_STATUS_FD) {
1628 *duplex = FULL_DUPLEX;
1629 DEBUGOUT("Full Duplex\n");
1630 } else {
1631 *duplex = HALF_DUPLEX;
1632 DEBUGOUT("Half Duplex\n");
1633 }
1634
1635 return E1000_SUCCESS;
1636 }
1637
1638 /**
1639 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1640 * @hw: pointer to the HW structure
1641 * @speed: stores the current speed
1642 * @duplex: stores the current duplex
1643 *
1644 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1645 * for fiber/serdes links.
1646 **/
1647 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw __unused,
1648 u16 *speed, u16 *duplex)
1649 {
1650 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1651
1652 *speed = SPEED_1000;
1653 *duplex = FULL_DUPLEX;
1654
1655 return E1000_SUCCESS;
1656 }
1657
1658 /**
1659 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1660 * @hw: pointer to the HW structure
1661 *
1662 * Acquire the HW semaphore to access the PHY or NVM
1663 **/
1664 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw __unused)
1665 {
1666 #if 0
1667 u32 swsm;
1668 s32 ret_val = E1000_SUCCESS;
1669 s32 timeout = hw->nvm.word_size + 1;
1670 s32 i = 0;
1671
1672 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1673
1674 /* Get the SW semaphore */
1675 while (i < timeout) {
1676 swsm = E1000_READ_REG(hw, E1000_SWSM);
1677 if (!(swsm & E1000_SWSM_SMBI))
1678 break;
1679
1680 usec_delay(50);
1681 i++;
1682 }
1683
1684 if (i == timeout) {
1685 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1686 ret_val = -E1000_ERR_NVM;
1687 goto out;
1688 }
1689
1690 /* Get the FW semaphore. */
1691 for (i = 0; i < timeout; i++) {
1692 swsm = E1000_READ_REG(hw, E1000_SWSM);
1693 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1694
1695 /* Semaphore acquired if bit latched */
1696 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1697 break;
1698
1699 usec_delay(50);
1700 }
1701
1702 if (i == timeout) {
1703 /* Release semaphores */
1704 e1000_put_hw_semaphore_generic(hw);
1705 DEBUGOUT("Driver can't access the NVM\n");
1706 ret_val = -E1000_ERR_NVM;
1707 goto out;
1708 }
1709
1710 out:
1711 return ret_val;
1712 #endif
1713 return 0;
1714 }
1715
1716 /**
1717 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1718 * @hw: pointer to the HW structure
1719 *
1720 * Release hardware semaphore used to access the PHY or NVM
1721 **/
1722 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw __unused)
1723 {
1724 #if 0
1725 u32 swsm;
1726
1727 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1728
1729 swsm = E1000_READ_REG(hw, E1000_SWSM);
1730
1731 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1732
1733 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1734 #endif
1735 }
1736
1737 /**
1738 * e1000_get_auto_rd_done_generic - Check for auto read completion
1739 * @hw: pointer to the HW structure
1740 *
1741 * Check EEPROM for Auto Read done bit.
1742 **/
1743 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1744 {
1745 s32 i = 0;
1746 s32 ret_val = E1000_SUCCESS;
1747
1748 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1749
1750 while (i < AUTO_READ_DONE_TIMEOUT) {
1751 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1752 break;
1753 msec_delay(1);
1754 i++;
1755 }
1756
1757 if (i == AUTO_READ_DONE_TIMEOUT) {
1758 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1759 ret_val = -E1000_ERR_RESET;
1760 goto out;
1761 }
1762
1763 out:
1764 return ret_val;
1765 }
1766
1767 /**
1768 * e1000_valid_led_default_generic - Verify a valid default LED config
1769 * @hw: pointer to the HW structure
1770 * @data: pointer to the NVM (EEPROM)
1771 *
1772 * Read the EEPROM for the current default LED configuration. If the
1773 * LED configuration is not valid, set to a valid LED configuration.
1774 **/
1775 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1776 {
1777 s32 ret_val;
1778
1779 DEBUGFUNC("e1000_valid_led_default_generic");
1780
1781 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1782 if (ret_val) {
1783 DEBUGOUT("NVM Read Error\n");
1784 goto out;
1785 }
1786
1787 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1788 *data = ID_LED_DEFAULT;
1789
1790 out:
1791 return ret_val;
1792 }
1793
1794 /**
1795 * e1000_id_led_init_generic -
1796 * @hw: pointer to the HW structure
1797 *
1798 **/
1799 s32 e1000_id_led_init_generic(struct e1000_hw *hw __unused)
1800 {
1801 #if 0
1802 struct e1000_mac_info *mac = &hw->mac;
1803 s32 ret_val;
1804 const u32 ledctl_mask = 0x000000FF;
1805 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1806 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1807 u16 data, i, temp;
1808 const u16 led_mask = 0x0F;
1809
1810 DEBUGFUNC("e1000_id_led_init_generic");
1811
1812 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1813 if (ret_val)
1814 goto out;
1815
1816 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1817 mac->ledctl_mode1 = mac->ledctl_default;
1818 mac->ledctl_mode2 = mac->ledctl_default;
1819
1820 for (i = 0; i < 4; i++) {
1821 temp = (data >> (i << 2)) & led_mask;
1822 switch (temp) {
1823 case ID_LED_ON1_DEF2:
1824 case ID_LED_ON1_ON2:
1825 case ID_LED_ON1_OFF2:
1826 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1827 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1828 break;
1829 case ID_LED_OFF1_DEF2:
1830 case ID_LED_OFF1_ON2:
1831 case ID_LED_OFF1_OFF2:
1832 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1833 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1834 break;
1835 default:
1836 /* Do nothing */
1837 break;
1838 }
1839 switch (temp) {
1840 case ID_LED_DEF1_ON2:
1841 case ID_LED_ON1_ON2:
1842 case ID_LED_OFF1_ON2:
1843 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1844 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1845 break;
1846 case ID_LED_DEF1_OFF2:
1847 case ID_LED_ON1_OFF2:
1848 case ID_LED_OFF1_OFF2:
1849 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1850 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1851 break;
1852 default:
1853 /* Do nothing */
1854 break;
1855 }
1856 }
1857
1858 out:
1859 return ret_val;
1860 #endif
1861 return 0;
1862 }
1863
1864 /**
1865 * e1000_setup_led_generic - Configures SW controllable LED
1866 * @hw: pointer to the HW structure
1867 *
1868 * This prepares the SW controllable LED for use and saves the current state
1869 * of the LED so it can be later restored.
1870 **/
1871 s32 e1000_setup_led_generic(struct e1000_hw *hw __unused)
1872 {
1873 #if 0
1874 u32 ledctl;
1875 s32 ret_val = E1000_SUCCESS;
1876
1877 DEBUGFUNC("e1000_setup_led_generic");
1878
1879 if (hw->mac.ops.setup_led != e1000_setup_led_generic) {
1880 ret_val = -E1000_ERR_CONFIG;
1881 goto out;
1882 }
1883
1884 if (hw->phy.media_type == e1000_media_type_fiber) {
1885 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1886 hw->mac.ledctl_default = ledctl;
1887 /* Turn off LED0 */
1888 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1889 E1000_LEDCTL_LED0_BLINK |
1890 E1000_LEDCTL_LED0_MODE_MASK);
1891 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1892 E1000_LEDCTL_LED0_MODE_SHIFT);
1893 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1894 } else if (hw->phy.media_type == e1000_media_type_copper) {
1895 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1896 }
1897
1898 out:
1899 return ret_val;
1900 #endif
1901 return 0;
1902 }
1903
1904 /**
1905 * e1000_cleanup_led_generic - Set LED config to default operation
1906 * @hw: pointer to the HW structure
1907 *
1908 * Remove the current LED configuration and set the LED configuration
1909 * to the default value, saved from the EEPROM.
1910 **/
1911 s32 e1000_cleanup_led_generic(struct e1000_hw *hw __unused)
1912 {
1913 #if 0
1914 s32 ret_val = E1000_SUCCESS;
1915
1916 DEBUGFUNC("e1000_cleanup_led_generic");
1917
1918 if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) {
1919 ret_val = -E1000_ERR_CONFIG;
1920 goto out;
1921 }
1922
1923 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1924
1925 out:
1926 return ret_val;
1927 #endif
1928 return 0;
1929 }
1930
1931 /**
1932 * e1000_blink_led_generic - Blink LED
1933 * @hw: pointer to the HW structure
1934 *
1935 * Blink the LEDs which are set to be on.
1936 **/
1937 s32 e1000_blink_led_generic(struct e1000_hw *hw __unused)
1938 {
1939 #if 0
1940 u32 ledctl_blink = 0;
1941 u32 i;
1942
1943 DEBUGFUNC("e1000_blink_led_generic");
1944
1945 if (hw->phy.media_type == e1000_media_type_fiber) {
1946 /* always blink LED0 for PCI-E fiber */
1947 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1948 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1949 } else {
1950 /*
1951 * set the blink bit for each LED that's "on" (0x0E)
1952 * in ledctl_mode2
1953 */
1954 ledctl_blink = hw->mac.ledctl_mode2;
1955 for (i = 0; i < 4; i++)
1956 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1957 E1000_LEDCTL_MODE_LED_ON)
1958 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1959 (i * 8));
1960 }
1961
1962 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1963
1964 return E1000_SUCCESS;
1965 #endif
1966 return 0;
1967 }
1968
1969 /**
1970 * e1000_led_on_generic - Turn LED on
1971 * @hw: pointer to the HW structure
1972 *
1973 * Turn LED on.
1974 **/
1975 s32 e1000_led_on_generic(struct e1000_hw *hw __unused)
1976 {
1977 #if 0
1978 u32 ctrl;
1979
1980 DEBUGFUNC("e1000_led_on_generic");
1981
1982 switch (hw->phy.media_type) {
1983 case e1000_media_type_fiber:
1984 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1985 ctrl &= ~E1000_CTRL_SWDPIN0;
1986 ctrl |= E1000_CTRL_SWDPIO0;
1987 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1988 break;
1989 case e1000_media_type_copper:
1990 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1991 break;
1992 default:
1993 break;
1994 }
1995
1996 return E1000_SUCCESS;
1997 #endif
1998 return 0;
1999 }
2000
2001 /**
2002 * e1000_led_off_generic - Turn LED off
2003 * @hw: pointer to the HW structure
2004 *
2005 * Turn LED off.
2006 **/
2007 s32 e1000_led_off_generic(struct e1000_hw *hw __unused)
2008 {
2009 #if 0
2010 u32 ctrl;
2011
2012 DEBUGFUNC("e1000_led_off_generic");
2013
2014 switch (hw->phy.media_type) {
2015 case e1000_media_type_fiber:
2016 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2017 ctrl |= E1000_CTRL_SWDPIN0;
2018 ctrl |= E1000_CTRL_SWDPIO0;
2019 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2020 break;
2021 case e1000_media_type_copper:
2022 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
2023 break;
2024 default:
2025 break;
2026 }
2027
2028 return E1000_SUCCESS;
2029 #endif
2030 return 0;
2031 }
2032
2033 /**
2034 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
2035 * @hw: pointer to the HW structure
2036 * @no_snoop: bitmap of snoop events
2037 *
2038 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
2039 **/
2040 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
2041 {
2042 u32 gcr;
2043
2044 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
2045
2046 if (hw->bus.type != e1000_bus_type_pci_express)
2047 goto out;
2048
2049 if (no_snoop) {
2050 gcr = E1000_READ_REG(hw, E1000_GCR);
2051 gcr &= ~(PCIE_NO_SNOOP_ALL);
2052 gcr |= no_snoop;
2053 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2054 }
2055 out:
2056 return;
2057 }
2058
2059 /**
2060 * e1000_disable_pcie_master_generic - Disables PCI-express master access
2061 * @hw: pointer to the HW structure
2062 *
2063 * Returns 0 (E1000_SUCCESS) if successful, else returns -10
2064 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2065 * the master requests to be disabled.
2066 *
2067 * Disables PCI-Express master access and verifies there are no pending
2068 * requests.
2069 **/
2070 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2071 {
2072 u32 ctrl;
2073 s32 timeout = MASTER_DISABLE_TIMEOUT;
2074 s32 ret_val = E1000_SUCCESS;
2075
2076 DEBUGFUNC("e1000_disable_pcie_master_generic");
2077
2078 if (hw->bus.type != e1000_bus_type_pci_express)
2079 goto out;
2080
2081 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2082 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2083 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2084
2085 while (timeout) {
2086 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2087 E1000_STATUS_GIO_MASTER_ENABLE))
2088 break;
2089 usec_delay(100);
2090 timeout--;
2091 }
2092
2093 if (!timeout) {
2094 DEBUGOUT("Master requests are pending.\n");
2095 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
2096 goto out;
2097 }
2098
2099 out:
2100 return ret_val;
2101 }
2102
2103 /**
2104 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2105 * @hw: pointer to the HW structure
2106 *
2107 * Reset the Adaptive Interframe Spacing throttle to default values.
2108 **/
2109 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2110 {
2111 struct e1000_mac_info *mac = &hw->mac;
2112
2113 DEBUGFUNC("e1000_reset_adaptive_generic");
2114
2115 if (!mac->adaptive_ifs) {
2116 DEBUGOUT("Not in Adaptive IFS mode!\n");
2117 goto out;
2118 }
2119
2120 mac->current_ifs_val = 0;
2121 mac->ifs_min_val = IFS_MIN;
2122 mac->ifs_max_val = IFS_MAX;
2123 mac->ifs_step_size = IFS_STEP;
2124 mac->ifs_ratio = IFS_RATIO;
2125
2126 mac->in_ifs_mode = false;
2127 E1000_WRITE_REG(hw, E1000_AIT, 0);
2128 out:
2129 return;
2130 }
2131
2132 /**
2133 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2134 * @hw: pointer to the HW structure
2135 *
2136 * Update the Adaptive Interframe Spacing Throttle value based on the
2137 * time between transmitted packets and time between collisions.
2138 **/
2139 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2140 {
2141 struct e1000_mac_info *mac = &hw->mac;
2142
2143 DEBUGFUNC("e1000_update_adaptive_generic");
2144
2145 if (!mac->adaptive_ifs) {
2146 DEBUGOUT("Not in Adaptive IFS mode!\n");
2147 goto out;
2148 }
2149
2150 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2151 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2152 mac->in_ifs_mode = true;
2153 if (mac->current_ifs_val < mac->ifs_max_val) {
2154 if (!mac->current_ifs_val)
2155 mac->current_ifs_val = mac->ifs_min_val;
2156 else
2157 mac->current_ifs_val +=
2158 mac->ifs_step_size;
2159 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val);
2160 }
2161 }
2162 } else {
2163 if (mac->in_ifs_mode &&
2164 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2165 mac->current_ifs_val = 0;
2166 mac->in_ifs_mode = false;
2167 E1000_WRITE_REG(hw, E1000_AIT, 0);
2168 }
2169 }
2170 out:
2171 return;
2172 }
2173
2174 /**
2175 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2176 * @hw: pointer to the HW structure
2177 *
2178 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2179 * set, which is forced to MDI mode only.
2180 **/
2181 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2182 {
2183 s32 ret_val = E1000_SUCCESS;
2184
2185 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2186
2187 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2188 DEBUGOUT("Invalid MDI setting detected\n");
2189 hw->phy.mdix = 1;
2190 ret_val = -E1000_ERR_CONFIG;
2191 goto out;
2192 }
2193
2194 out:
2195 return ret_val;
2196 }