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Make UEFI boot-platform build again
[haiku.git] / headers / private / graphics / nvidia / nv_acc.h
blobcf1b48a704a7e29b25750d674ea74084038ae4f5
1 /*
2 definitions for used nVidia acceleration engine commands.
3
4 Written by Rudolf Cornelissen 12/2004-12/2005
5 */
6
7 #ifndef NV_ACC_H
8 #define NV_ACC_H
9
10 typedef struct {
11 uint32 reserved00[0x0004];
12 uint16 FifoFree; /* little endian (FIFO internal register) */
13 uint16 Nop; /* little endian (FIFO internal register) */
14 uint32 reserved01[0x000b];
15 uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
16 uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
17 uint32 reserved02[0x00ae];
18 uint32 SetRop5; /* b0-7 is ROP5 */
19 } cmd_nv_rop5_solid;
20
21 typedef struct {
22 uint32 reserved00[0x0004];
23 uint16 FifoFree; /* little endian (FIFO internal register) */
24 uint16 Nop; /* little endian (FIFO internal register) */
25 uint32 reserved01[0x000b];
26 uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
27 uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
28 uint32 reserved02[0x00ae];
29 uint32 TopLeft; /* b0-15 is left, b16-31 is top */
30 uint32 HeightWidth; /* b0-15 is width, b16-31 is height */
31 } cmd_nv_image_black_rectangle;
32
33 typedef struct {
34 uint32 reserved00[0x0004];
35 uint16 FifoFree; /* little endian (FIFO internal register) */
36 uint16 Nop; /* little endian (FIFO internal register) */
37 uint32 reserved01[0x000b];
38 uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
39 uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
40 uint32 reserved02[0x00ae];
41 uint32 SetColorFormat; /* colorspace */
42 uint32 reserved03[0x0001];
43 uint32 SetShape; /* b0-1: %00 = 8X_8Y; %01 = 64X_1Y; %10 = 1X_64Y */
44 uint32 reserved04[0x0001];
45 uint32 SetColor0; /* b0-31 is color */
46 uint32 SetColor1; /* b0-31 is color */
47 uint32 SetPattern[0x0002]; /* b0-31 is bitmap */
48 } cmd_nv_image_pattern;
49
50 typedef struct {
51 uint32 reserved00[0x0004];
52 uint16 FifoFree; /* little endian (FIFO internal register) */
53 uint16 Nop; /* little endian (FIFO internal register) */
54 uint32 reserved01[0x000b];
55 uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
56 uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
57 uint32 reserved02[0x00ae];
58 uint32 SourceOrg; /* b0-15 is X, b16-31 is Y */
59 uint32 DestOrg; /* b0-15 is X, b16-31 is Y */
60 uint32 HeightWidth; /* b0-15 is width, b16-31 is height */
61 } cmd_nv_image_blit;
62
63 //fixme: using nv4_gdi_rectangle_text for DMA acc. Differs slightly from this one!
64 //WARNING: nv4_gdi_rectangle_text can only do 32 unclipped rects at once!
65 typedef struct {
66 uint32 reserved00[0x0004];
67 uint16 FifoFree; /* little endian (FIFO internal register) */
68 uint16 Nop; /* little endian (FIFO internal register) */
69 uint32 reserved01[0x000b];
70 uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
71 uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
72 uint32 reserved02[0x00ae];
73 uint32 SetColorFormat; /* colorspace */
74 uint32 reserved03[0x003e];
75 uint32 Color1A; /* b0-31 is color */
76 struct {
77 uint32 LeftTop; /* b0-15 is top, b16-31 is left */
78 uint32 WidthHeight; /* b0-15 is height, b16-31 is width */
79 } UnclippedRectangle[0x40]; /* command can handle upto 64 unclipped rects */
80 /* fixme: XFree also defines the registers below:
81 * (used for the 2D 'ScanlineCPUToScreenColorExpandFill' and 'ColorExpandScanline'
82 * functions.)
83 * We don't use this currently. */
84 /*
85 U032 reserved04[(0x080)-3];
86 struct
87 {
88 U032 TopLeft;
89 U032 BottomRight;
90 } ClipB;
91 U032 Color1B;
92 struct
93 {
94 U032 TopLeft;
95 U032 BottomRight;
96 } ClippedRectangle[64];
97 U032 reserved05[(0x080)-5];
98 struct
99 {
100 U032 TopLeft;
101 U032 BottomRight;
102 } ClipC;
103 U032 Color1C;
104 U032 WidthHeightC;
105 U032 PointC;
106 U032 MonochromeData1C;
107 U032 reserved06[(0x080)+121];
108 struct
109 {
110 U032 TopLeft;
111 U032 BottomRight;
112 } ClipD;
113 U032 Color1D;
114 U032 WidthHeightInD;
115 U032 WidthHeightOutD;
116 U032 PointD;
117 U032 MonochromeData1D;
118 U032 reserved07[(0x080)+120];
119 struct
120 {
121 U032 TopLeft;
122 U032 BottomRight;
123 } ClipE;
124 U032 Color0E;
125 U032 Color1E;
126 U032 WidthHeightInE;
127 U032 WidthHeightOutE;
128 U032 PointE;
129 U032 MonochromeData01E;
130 */
131 } cmd_nv3_gdi_rectangle_text;
132
133 /* This command could (at least) potentially speed-up our fill_span command... :-) */
134 //fixme: test this 2D command!
135 typedef struct {
136 uint32 reserved00[0x0004];
137 uint16 FifoFree; /* little endian (FIFO internal register) */
138 uint16 Nop; /* little endian (FIFO internal register) */
139 uint32 reserved01[0x000b];
140 uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
141 uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
142 uint32 reserved02[0x00af];
143 uint32 Color; /* b0-31 is color */
144 uint32 reserved03[0x003e];
145 struct {
146 uint32 Point0; /* b0-15 is X, b16-31 is Y: starting coordinate */
147 uint32 Point1; /* b0-15 is X, b16-31 is Y: ending coordinate */
148 } Line[0x10]; /* command can handle upto 16 lines */
149 struct {
150 uint32 Point0X; /* b0-31 is X: starting coordinate */
151 uint32 Point0Y; /* b0-31 is Y: starting coordinate */
152 uint32 Point1X; /* b0-31 is X: ending coordinate */
153 uint32 Point1Y; /* b0-31 is Y: ending coordinate */
154 } Line32[0x08]; /* cmd can handle upto 8 lines with 32-bit coordinates */
155 struct {
156 uint32 Point; /* b0-15 is X, b16-31 is Y */
157 } Polyline[0x20]; /* cmd can handle upto 32 points polylines */
158 struct {
159 uint32 PointX; /* b0-31 is X */
160 uint32 PointY; /* b0-31 is Y */
161 } Polyline32[0x10]; /* cmd can handle upto 16 point polylines with 32-bit coord's */
162 struct {
163 uint32 Color; /* b0-31 is color */
164 uint32 Point; /* b0-15 is X, b16-31 is Y */
165 } ColorPolyline[0x10]; /* cmd can handle upto 16 point polylines with individually
166 * colored sections */
167 } cmd_nv1_render_solid_lin;
168
169 /* Someone defined this in XFree once (as 'RivaRectangle') but never used it:
170 * a handle should also be defined in the engine's init code, which was never done AFAIK.
171 * The command could be very interesting for us, as it could potentially speed-up our
172 * rectangle_fills :-) */
173 //fixme: test this 2D command!
174 typedef struct {
175 uint32 reserved00[0x0004];
176 uint16 FifoFree; /* little endian (FIFO internal register) */
177 uint16 Nop; /* little endian (FIFO internal register) */
178 uint32 reserved01[0x000b];
179 uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
180 uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
181 uint32 reserved02[0x00af];
182 uint32 Color; /* b0-31 is color */
183 uint32 reserved03[0x003e];
184 struct {
185 uint32 TopLeft; /* b0-15 is left, b16-31 is top */
186 uint32 HeightWidth; /* b0-15 is width, b16-31 is height */
187 } Rectangle[0x10]; /* command can handle upto 16 rectangles */
188 } cmd_nv_render_solid_rectangle;/* nv1_render_solid_rectangle is identical */
189
190 //fixme: (setup in progress for DMA) complete or remove (this cmd is not used currently)
191 typedef struct {
192 } cmd_nv1_image_from_cpu; /* 'pixmap': used in XFree 4.2.0, but not beyond.
193 * (Used for the 2D 'ImageWriteScanline' and
194 * 'ScanlineImageWriteRect' functions.)
195 * Is this command actually usefull? */
196
197 typedef struct {
198 uint32 reserved00[0x0004];
199 uint16 FifoFree; /* little endian (FIFO internal register) */
200 uint16 Nop; /* little endian (FIFO internal register) */
201 uint32 reserved01[0x000b];
202 uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
203 uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
204 uint32 reserved02[0x00ae];
205 uint32 Format; /* buffer colorspace */
206 uint32 Pitch; /* b0-15 is source pitch, b16-31 is dest pitch */
207 uint32 OffsetSource; /* b0-31 is source bufferadress offset */
208 uint32 OffsetDest; /* b0-31 is dest bufferadress offset */
209 } cmd_nv4_surface; /* nv10_context_surfaces_2d is identical as far as used */
210
211 /************************
212 * 3D specific commands *
213 ************************/
214
215 typedef struct {
216 uint32 reserved00[0x0004];
217 uint16 FifoFree; /* little endian (FIFO internal register) */
218 uint16 Nop; /* little endian (FIFO internal register) */
219 uint32 reserved01[0x000b];
220 uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
221 uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
222 uint32 reserved02[0x00ae];
223 uint32 Colorkey; /* texture colorkey */
224 uint32 Offset; /* texture offset */
225 uint32 Format; /* texture colorspace, size, and a lot more */
226 uint32 Filter; /* texture filtering modes (used for scaling) */
227 uint32 Blend; /* triangle blend: shade, perspective, specular.. */
228 uint32 Control; /* triangle control: Z-enable, culling, dither.. */
229 uint32 FogColor; /* fog colorvalue */
230 uint32 reserved03[0x0039];
231 struct {
232 float ScreenX; /* X */
233 float ScreenY; /* Y */
234 float ScreenZ; /* depth */
235 float RWH; /* eyeM */
236 uint32 Color; /* b24-31 Alpha, b16-23 Red, b8-15 Green, b0-7 Blue */
237 uint32 Specular; /* b24-31 Fog, b16-23 Red, b8-15 Green, b0-7 Blue */
238 float TU; /* texture S */
239 float TV; /* texture T */
240 } TLVertex[0x10]; /* command can handle upto 16 textured, lit(?) vertexes */
241 uint32 TLVDrawPrim[0x40]; /* b20-31 is I5, b16-19 is I4, b12-15 is I3,
242 * b8-11 is I2, 4-7 is I1, b0-3 is I0:
243 * Ix is a TLVertex[Ix].
244 * So: define your (single) texture, define your
245 * vertexes, and then program TLVDrawPrim with the
246 * order to draw them.
247 * You can draw primitives consisting of sets of upto
248 * 6 out of 16 defined vertexes this way; and you can
249 * draw 64 sets maximum. */
250 } cmd_nv4_dx5_texture_triangle; /* nv10_dx5_texture_triangle is identical */
251
252 typedef struct {
253 uint32 reserved00[0x0004];
254 uint16 FifoFree; /* little endian (FIFO internal register) */
255 uint16 Nop; /* little endian (FIFO internal register) */
256 uint32 reserved01[0x000b];
257 uint32 DMAPut; /* b2-28 is DMA Put offset (FIFO internal register) */
258 uint32 DMAGet; /* b2-28 is DMA Get offset (FIFO internal register) */
259 uint32 reserved02[0x00b0]; /* fixme? there's more here that's not used apparantly */
260 uint32 Pitch; /* b16-31 is Z-buffer, b0-15 is colorbuffer pitch */
261 uint32 SetOffsetColor; /* b0-31 is colorbuffer (renderbuffer) offset */
262 uint32 SetOffsetZeta; /* b0-31 is Z-buffer (zeta buffer) offset */
263 } cmd_nv4_context_surfaces_argb_zs; /* nv10_context_surfaces_argb_zs is identical */
264
265 //fixme: fill this out...
266 typedef struct {
267 } cmd_nv4_dx6_multi_texture_triangle;/* nv10_dx6_multi_texture_triangle is identical? */
268
269
270 /************ DMA command defines ***********/
271
272 /* FIFO channels */
273 #define NV_GENERAL_FIFO_CH0 0x0000
274 #define NV_GENERAL_FIFO_CH1 0x2000
275 #define NV_GENERAL_FIFO_CH2 0x4000
276 #define NV_GENERAL_FIFO_CH3 0x6000
277 #define NV_GENERAL_FIFO_CH4 0x8000
278 #define NV_GENERAL_FIFO_CH5 0xa000
279 #define NV_GENERAL_FIFO_CH6 0xc000
280 #define NV_GENERAL_FIFO_CH7 0xe000
281
282 /* sub-command offsets within FIFO channels */
283 #define NV_GENERAL_DMAPUT 0x0040
284 #define NV_GENERAL_DMAGET 0x0044
285 #define NV_ROP5_SOLID_SETROP5 0x0300
286 #define NV_IMAGE_BLACK_RECTANGLE_TOPLEFT 0x0300
287 #define NV_IMAGE_PATTERN_SETCOLORFORMAT 0x0300
288 #define NV_IMAGE_PATTERN_SETSHAPE 0x0308
289 #define NV_IMAGE_PATTERN_SETCOLOR0 0x0310
290 #define NV_IMAGE_BLIT_SOURCEORG 0x0300
291 //fixme note: non-DMA acc is still using NV3_GDI_RECTANGLE_TEXT...
292 //which is just as fast as NV4_GDI_RECTANGLE_TEXT, but has a hardware fault for DMA!
293 #define NV4_GDI_RECTANGLE_TEXT_SETCOLORFORMAT 0x0300
294 #define NV4_GDI_RECTANGLE_TEXT_COLOR1A 0x03fc
295 #define NV4_GDI_RECTANGLE_TEXT_UCR0_LEFTTOP 0x0400
296 #define NV4_SURFACE_FORMAT 0x0300
297 #define NV_SCALED_IMAGE_FROM_MEMORY_SETCOLORFORMAT 0x0300
298 #define NV_SCALED_IMAGE_FROM_MEMORY_SOURCEORG 0x0308
299 #define NV_SCALED_IMAGE_FROM_MEMORY_SOURCESIZE 0x0400
300
301
302 /************************
303 * 3D specific commands *
304 ************************/
305
306 #define NV4_DX5_TEXTURE_TRIANGLE_COLORKEY 0x0300
307 #define NV4_DX5_TEXTURE_TRIANGLE_TLVERTEX(i) 0x0400 + (i << 5)
308 #define NV4_DX5_TEXTURE_TRIANGLE_TLVDRAWPRIM(i) 0x0600 + (i << 2)
309 #define NV4_CONTEXT_SURFACES_ARGB_ZS_PITCH 0x0308
310
311 #endif
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