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[haiku.git] / headers / private / graphics / radeon_hd / r600_reg.h
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1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 * Alexander von Gluck <kallisti5@unixzen.com>
29 #ifndef __R600_REG_H__
30 #define __R600_REG_H__
33 /* Scratch Registers */
34 #define R600_SCRATCH_REG0 0x1724 // aka R600_BIOS_0_SCRATCH
35 #define R600_SCRATCH_REG1 0x1728 // aka R600_BIOS_1_SCRATCH
36 #define R600_SCRATCH_REG2 0x172c // aka R600_BIOS_2_SCRATCH
37 #define R600_SCRATCH_REG3 0x1730 // aka R600_BIOS_3_SCRATCH
38 #define R600_SCRATCH_REG4 0x1734 // aka R600_BIOS_4_SCRATCH
39 #define R600_SCRATCH_REG5 0x1738 // aka R600_BIOS_5_SCRATCH
40 #define R600_SCRATCH_REG6 0x173c // aka R600_BIOS_6_SCRATCH
41 #define R600_SCRATCH_REG7 0x1740 // aka R600_BIOS_7_SCRATCH
43 /* CRT controler register offset */
44 #define R600_CRTC0_REGISTER_OFFSET 0x0
45 #define R600_CRTC1_REGISTER_OFFSET 0x800
47 #define R600_PCIE_PORT_INDEX 0x0038
48 #define R600_PCIE_PORT_DATA 0x003c
50 /* Memory Controler */
51 #define R600_MC_VM_FB_LOCATION 0x2180
52 #define R600_MC_FB_BASE_MASK 0x0000FFFF
53 #define R600_MC_FB_BASE_SHIFT 0
54 #define R600_MC_FB_TOP_MASK 0xFFFF0000
55 #define R600_MC_FB_TOP_SHIFT 16
56 #define R600_MC_VM_AGP_TOP 0x2184
57 #define R600_MC_AGP_TOP_MASK 0x0003FFFF
58 #define R600_MC_AGP_TOP_SHIFT 0
59 #define R600_MC_VM_AGP_BOT 0x2188
60 #define R600_MC_AGP_BOT_MASK 0x0003FFFF
61 #define R600_MC_AGP_BOT_SHIFT 0
62 #define R600_MC_VM_AGP_BASE 0x218c
63 #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
64 #define R600_LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF
65 #define R600_LOGICAL_PAGE_NUMBER_SHIFT 0
66 #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
67 #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
69 #define R600_RAMCFG 0x2408
70 #define R600_CHANSIZE (1 << 7)
71 #define R600_CHANSIZE_OVERRIDE (1 << 10)
73 #define R600_GENERAL_PWRMGT 0x618
74 #define R600_OPEN_DRAIN_PADS (1 << 11)
76 #define R600_LOWER_GPIO_ENABLE 0x710
77 #define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718
78 #define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c
79 #define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720
80 #define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
82 #define R600_D1GRPH_SWAP_CONTROL 0x610C
83 #define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
84 #define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
85 #define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
86 #define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
88 /* Hot plug detection */
89 #define R600_HDP_HOST_PATH_CNTL 0x2C00
90 #define R600_HDP_NONSURFACE_BASE 0x2C04
91 #define R600_HDP_NONSURFACE_INFO 0x2C08
92 #define R600_HDP_NONSURFACE_SIZE 0x2C0C
93 #define R600_HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
94 #define R600_HDP_TILING_CONFIG 0x2F3C
95 #define R600_HDP_DEBUG1 0x2F34
97 #define R600_BUS_CNTL 0x5420
98 #define R600_BIOS_ROM_DIS (1 << 1)
99 #define R600_CONFIG_CNTL 0x5424
100 #define R600_CONFIG_MEMSIZE 0x5428
101 #define R600_CONFIG_F0_BASE 0x542C
102 #define R600_CONFIG_APER_SIZE 0x5430
104 #define R600_ROM_CNTL 0x1600
105 #define R600_SCK_OVERWRITE (1 << 1)
106 #define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
107 #define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
109 #define R600_CG_SPLL_FUNC_CNTL 0x600
110 #define R600_SPLL_BYPASS_EN (1 << 3)
111 #define R600_CG_SPLL_STATUS 0x60c
112 #define R600_SPLL_CHG_STATUS (1 << 1)
115 /* Audio, these regs were reverse enginered,
116 * so the chance is high that the naming is wrong
117 * R6xx+ ??? */
119 /* Audio clocks */
120 #define R600_AUDIO_PLL1_MUL 0x0514
121 #define R600_AUDIO_PLL1_DIV 0x0518
122 #define R600_AUDIO_PLL2_MUL 0x0524
123 #define R600_AUDIO_PLL2_DIV 0x0528
124 #define R600_AUDIO_CLK_SRCSEL 0x0534
126 /* Audio general */
127 #define R600_AUDIO_ENABLE 0x7300
128 #define R600_AUDIO_TIMING 0x7344
130 /* Audio params */
131 #define R600_AUDIO_VENDOR_ID 0x7380
132 #define R600_AUDIO_REVISION_ID 0x7384
133 #define R600_AUDIO_ROOT_NODE_COUNT 0x7388
134 #define R600_AUDIO_NID1_NODE_COUNT 0x738c
135 #define R600_AUDIO_NID1_TYPE 0x7390
136 #define R600_AUDIO_SUPPORTED_SIZE_RATE 0x7394
137 #define R600_AUDIO_SUPPORTED_CODEC 0x7398
138 #define R600_AUDIO_SUPPORTED_POWER_STATES 0x739c
139 #define R600_AUDIO_NID2_CAPS 0x73a0
140 #define R600_AUDIO_NID3_CAPS 0x73a4
141 #define R600_AUDIO_NID3_PIN_CAPS 0x73a8
143 /* Audio conn list */
144 #define R600_AUDIO_CONN_LIST_LEN 0x73ac
145 #define R600_AUDIO_CONN_LIST 0x73b0
147 /* Audio verbs */
148 #define R600_AUDIO_RATE_BPS_CHANNEL 0x73c0
149 #define R600_AUDIO_PLAYING 0x73c4
150 #define R600_AUDIO_IMPLEMENTATION_ID 0x73c8
151 #define R600_AUDIO_CONFIG_DEFAULT 0x73cc
152 #define R600_AUDIO_PIN_SENSE 0x73d0
153 #define R600_AUDIO_PIN_WIDGET_CNTL 0x73d4
154 #define R600_AUDIO_STATUS_BITS 0x73d8
156 /* HDMI base register addresses */
157 #define R600_HDMI_BLOCK1 0x7400
158 #define R600_HDMI_BLOCK2 0x7700
159 #define R600_HDMI_BLOCK3 0x7800
161 /* HDMI registers */
162 #define R600_HDMI_ENABLE 0x00
163 #define R600_HDMI_STATUS 0x04
164 #define R600_HDMI_INT_PENDING (1 << 29)
165 #define R600_HDMI_CNTL 0x08
166 #define R600_HDMI_INT_EN (1 << 28)
167 #define R600_HDMI_INT_ACK (1 << 29)
168 #define R600_HDMI_UNKNOWN_0 0x0C
169 #define R600_HDMI_AUDIOCNTL 0x10
170 #define R600_HDMI_VIDEOCNTL 0x14
171 #define R600_HDMI_VERSION 0x18
172 #define R600_HDMI_UNKNOWN_1 0x28
173 #define R600_HDMI_VIDEOINFOFRAME_0 0x54
174 #define R600_HDMI_VIDEOINFOFRAME_1 0x58
175 #define R600_HDMI_VIDEOINFOFRAME_2 0x5c
176 #define R600_HDMI_VIDEOINFOFRAME_3 0x60
177 #define R600_HDMI_32kHz_CTS 0xac
178 #define R600_HDMI_32kHz_N 0xb0
179 #define R600_HDMI_44_1kHz_CTS 0xb4
180 #define R600_HDMI_44_1kHz_N 0xb8
181 #define R600_HDMI_48kHz_CTS 0xbc
182 #define R600_HDMI_48kHz_N 0xc0
183 #define R600_HDMI_AUDIOINFOFRAME_0 0xcc
184 #define R600_HDMI_AUDIOINFOFRAME_1 0xd0
185 #define R600_HDMI_IEC60958_1 0xd4
186 #define R600_HDMI_IEC60958_2 0xd8
187 #define R600_HDMI_UNKNOWN_2 0xdc
188 #define R600_HDMI_AUDIO_DEBUG_0 0xe0
189 #define R600_HDMI_AUDIO_DEBUG_1 0xe4
190 #define R600_HDMI_AUDIO_DEBUG_2 0xe8
191 #define R600_HDMI_AUDIO_DEBUG_3 0xec
193 /* HDMI additional config base register addresses */
194 #define R600_HDMI_CONFIG1 0x7600
195 #define R600_HDMI_CONFIG2 0x7a00
197 /* Thermal information */
198 #define R600_CG_THERMAL_STATUS 0x7F4
199 #define R600_ASIC_T(x) ((x) << 0)
200 #define R600_ASIC_T_MASK 0x1FF
201 #define R600_ASIC_T_SHIFT 0
204 #endif /* __R600_REG_H__ */