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Make UEFI boot-platform build again
[haiku.git] / headers / private / graphics / vmware / svga_reg.h
blob7aa66200711f7283790112561857c965e0f575cc
1 /*
2 * Copyright 1998-2001, VMware, Inc.
3 * Distributed under the terms of the MIT License.
4 *
5 */
6
7 /*
8 * svga_reg.h --
9 *
10 * SVGA hardware definitions
11 */
12
13 #ifndef _SVGA_REG_H_
14 #define _SVGA_REG_H_
15
16 /*
17 * Memory and port addresses and fundamental constants
18 */
19
20 /*
21 * Note-- MAX_WIDTH and MAX_HEIGHT are largely ignored by the code. This
22 * isn't such a bad thing for forward compatibility. --Jeremy.
23 */
24 #define SVGA_MAX_WIDTH 2360
25 #define SVGA_MAX_HEIGHT 1770
26 #define SVGA_MAX_BITS_PER_PIXEL 32
27 #define SVGA_MAX_DEPTH 24
28
29 #define SVGA_FB_MAX_SIZE \
30 ((((SVGA_MAX_WIDTH * SVGA_MAX_HEIGHT * \
31 SVGA_MAX_BITS_PER_PIXEL / 8) >> PAGE_SHIFT) + 1) << PAGE_SHIFT)
32
33 #define SVGA_MAX_PSEUDOCOLOR_DEPTH 8
34 #define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
35 #define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS)
36
37 #define SVGA_MAGIC 0x900000UL
38 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
39
40 /* Version 2 let the address of the frame buffer be unsigned on Win32 */
41 #define SVGA_VERSION_2 2
42 #define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2)
43
44 /* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so
45 PALETTE_BASE has moved */
46 #define SVGA_VERSION_1 1
47 #define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1)
48
49 /* Version 0 is the initial version */
50 #define SVGA_VERSION_0 0
51 #define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0)
52
53 /* Invalid SVGA_ID_ */
54 #define SVGA_ID_INVALID 0xFFFFFFFF
55
56 /* More backwards compatibility, old location of color map: */
57 #define SVGA_OLD_PALETTE_BASE 17
58
59 /* Base and Offset gets us headed the right way for PCI Base Addr Registers */
60 #define SVGA_LEGACY_BASE_PORT 0x4560
61 #define SVGA_INDEX_PORT 0x0
62 #define SVGA_VALUE_PORT 0x1
63 #define SVGA_BIOS_PORT 0x2
64 #define SVGA_NUM_PORTS 0x3
65
66 /* This port is deprecated, but retained because of old drivers. */
67 #define SVGA_LEGACY_ACCEL_PORT 0x3
68
69 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
70 #define SVGA_CURSOR_ON_HIDE 0x0 /* Must be 0 to maintain backward compatibility */
71 #define SVGA_CURSOR_ON_SHOW 0x1 /* Must be 1 to maintain backward compatibility */
72 #define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 /* Remove the cursor from the framebuffer because we need to see what's under it */
73 #define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */
74
75 /*
76 * Registers
77 */
78
79 enum {
80 SVGA_REG_ID = 0,
81 SVGA_REG_ENABLE = 1,
82 SVGA_REG_WIDTH = 2,
83 SVGA_REG_HEIGHT = 3,
84 SVGA_REG_MAX_WIDTH = 4,
85 SVGA_REG_MAX_HEIGHT = 5,
86 SVGA_REG_DEPTH = 6,
87 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
88 SVGA_REG_PSEUDOCOLOR = 8,
89 SVGA_REG_RED_MASK = 9,
90 SVGA_REG_GREEN_MASK = 10,
91 SVGA_REG_BLUE_MASK = 11,
92 SVGA_REG_BYTES_PER_LINE = 12,
93 SVGA_REG_FB_START = 13,
94 SVGA_REG_FB_OFFSET = 14,
95 SVGA_REG_VRAM_SIZE = 15,
96 SVGA_REG_FB_SIZE = 16,
97
98 /* ID 0 implementation only had the above registers, then the palette */
99
100 SVGA_REG_CAPABILITIES = 17,
101 SVGA_REG_MEM_START = 18, /* Memory for command FIFO and bitmaps */
102 SVGA_REG_MEM_SIZE = 19,
103 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
104 SVGA_REG_SYNC = 21, /* Write to force synchronization */
105 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
106 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
107 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
108 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
109 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
110 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
111 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
112 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
113 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
114 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
115 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
116 SVGA_REG_TOP = 33, /* Must be 1 more than the last register */
117
118 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
119 /* Next 768 (== 256*3) registers exist for colormap */
120 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
121 /* Base of scratch registers */
122 /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
123 First 4 are reserved for VESA BIOS Extension; any remaining are for
124 the use of the current SVGA driver. */
125 };
126
127
128 /*
129 * Capabilities
130 */
131
132 #define SVGA_CAP_NONE 0x00000
133 #define SVGA_CAP_RECT_FILL 0x00001
134 #define SVGA_CAP_RECT_COPY 0x00002
135 #define SVGA_CAP_RECT_PAT_FILL 0x00004
136 #define SVGA_CAP_LEGACY_OFFSCREEN 0x00008
137 #define SVGA_CAP_RASTER_OP 0x00010
138 #define SVGA_CAP_CURSOR 0x00020
139 #define SVGA_CAP_CURSOR_BYPASS 0x00040
140 #define SVGA_CAP_CURSOR_BYPASS_2 0x00080
141 #define SVGA_CAP_8BIT_EMULATION 0x00100
142 #define SVGA_CAP_ALPHA_CURSOR 0x00200
143 #define SVGA_CAP_GLYPH 0x00400
144 #define SVGA_CAP_GLYPH_CLIPPING 0x00800
145 #define SVGA_CAP_OFFSCREEN_1 0x01000
146 #define SVGA_CAP_ALPHA_BLEND 0x02000
147 #define SVGA_CAP_3D 0x04000
148 #define SVGA_CAP_EXTENDED_FIFO 0x08000
149 #define SVGA_CAP_MULTIMON 0x10000
150 #define SVGA_CAP_PITCHLOCK 0x20000
151
152 /*
153 * Raster op codes (same encoding as X) used by FIFO drivers.
154 */
155
156 #define SVGA_ROP_CLEAR 0x00 /* 0 */
157 #define SVGA_ROP_AND 0x01 /* src AND dst */
158 #define SVGA_ROP_AND_REVERSE 0x02 /* src AND NOT dst */
159 #define SVGA_ROP_COPY 0x03 /* src */
160 #define SVGA_ROP_AND_INVERTED 0x04 /* NOT src AND dst */
161 #define SVGA_ROP_NOOP 0x05 /* dst */
162 #define SVGA_ROP_XOR 0x06 /* src XOR dst */
163 #define SVGA_ROP_OR 0x07 /* src OR dst */
164 #define SVGA_ROP_NOR 0x08 /* NOT src AND NOT dst */
165 #define SVGA_ROP_EQUIV 0x09 /* NOT src XOR dst */
166 #define SVGA_ROP_INVERT 0x0a /* NOT dst */
167 #define SVGA_ROP_OR_REVERSE 0x0b /* src OR NOT dst */
168 #define SVGA_ROP_COPY_INVERTED 0x0c /* NOT src */
169 #define SVGA_ROP_OR_INVERTED 0x0d /* NOT src OR dst */
170 #define SVGA_ROP_NAND 0x0e /* NOT src OR NOT dst */
171 #define SVGA_ROP_SET 0x0f /* 1 */
172 #define SVGA_ROP_UNSUPPORTED 0x10
173
174 #define SVGA_NUM_SUPPORTED_ROPS 16
175 #define SVGA_ROP_ALL (MASK(SVGA_NUM_SUPPORTED_ROPS))
176 #define SVGA_IS_VALID_ROP(rop) (rop < SVGA_NUM_SUPPORTED_ROPS)
177
178 /*
179 * Ops
180 * For each pixel, the four channels of the image are computed with:
181 *
182 * C = Ca * Fa + Cb * Fb
183 *
184 * where C, Ca, Cb are the values of the respective channels and Fa
185 * and Fb come from the following table:
186 *
187 * BlendOp Fa Fb
188 * ------------------------------------------
189 * Clear 0 0
190 * Src 1 0
191 * Dst 0 1
192 * Over 1 1-Aa
193 * OverReverse 1-Ab 1
194 * In Ab 0
195 * InReverse 0 Aa
196 * Out 1-Ab 0
197 * OutReverse 0 1-Aa
198 * Atop Ab 1-Aa
199 * AtopReverse 1-Ab Aa
200 * Xor 1-Ab 1-Aa
201 * Add 1 1
202 * Saturate min(1,(1-Ab)/Aa) 1
203 *
204 * Flags
205 * You can use the following flags to achieve additional affects:
206 *
207 * Flag Effect
208 * ------------------------------------------
209 * ConstantSourceAlpha Ca = Ca * Param0
210 * ConstantDestAlpha Cb = Cb * Param1
211 *
212 * Flag effects resolve before the op. For example
213 * BlendOp == Add && Flags == ConstantSourceAlpha |
214 * ConstantDestAlpha results in:
215 *
216 * C = (Ca * Param0) + (Cb * Param1)
217 */
218
219 #define SVGA_BLENDOP_CLEAR 0
220 #define SVGA_BLENDOP_SRC 1
221 #define SVGA_BLENDOP_DST 2
222 #define SVGA_BLENDOP_OVER 3
223 #define SVGA_BLENDOP_OVER_REVERSE 4
224 #define SVGA_BLENDOP_IN 5
225 #define SVGA_BLENDOP_IN_REVERSE 6
226 #define SVGA_BLENDOP_OUT 7
227 #define SVGA_BLENDOP_OUT_REVERSE 8
228 #define SVGA_BLENDOP_ATOP 9
229 #define SVGA_BLENDOP_ATOP_REVERSE 10
230 #define SVGA_BLENDOP_XOR 11
231 #define SVGA_BLENDOP_ADD 12
232 #define SVGA_BLENDOP_SATURATE 13
233
234 #define SVGA_NUM_BLENDOPS 14
235 #define SVGA_IS_VALID_BLENDOP(op) (op >= 0 && op < SVGA_NUM_BLENDOPS)
236
237 #define SVGA_BLENDFLAG_CONSTANT_SOURCE_ALPHA 0x01
238 #define SVGA_BLENDFLAG_CONSTANT_DEST_ALPHA 0x02
239 #define SVGA_NUM_BLENDFLAGS 2
240 #define SVGA_BLENDFLAG_ALL (MASK(SVGA_NUM_BLENDFLAGS))
241 #define SVGA_IS_VALID_BLENDFLAG(flag) ((flag & ~SVGA_BLENDFLAG_ALL) == 0)
242
243
244 /*
245 * FIFO offsets (viewed as an array of 32-bit words)
246 */
247
248 enum {
249 /*
250 * The original defined FIFO offsets
251 */
252
253 SVGA_FIFO_MIN = 0,
254 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
255 SVGA_FIFO_NEXT_CMD,
256 SVGA_FIFO_STOP,
257
258 /*
259 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
260 */
261
262 SVGA_FIFO_CAPABILITIES = 4,
263 SVGA_FIFO_FLAGS,
264 SVGA_FIFO_FENCE,
265 SVGA_FIFO_3D_HWVERSION, /* Check SVGA3dHardwareVersion in svga3d_reg.h */
266 SVGA_FIFO_PITCHLOCK,
267
268 /*
269 * Always keep this last. It's not an offset with semantic value, but
270 * rather a convenient way to produce the value of fifo[SVGA_FIFO_NUM_REGS]
271 */
272
273 SVGA_FIFO_NUM_REGS
274 };
275
276 /*
277 * FIFO Capabilities
278 *
279 * Fence -- Fence register and command are supported
280 * Accel Front -- Front buffer only commands are supported
281 * Pitch Lock -- Pitch lock register is supported
282 */
283
284 #define SVGA_FIFO_CAP_NONE 0
285 #define SVGA_FIFO_CAP_FENCE (1<<0)
286 #define SVGA_FIFO_CAP_ACCELFRONT (1<<1)
287 #define SVGA_FIFO_CAP_PITCHLOCK (1<<2)
288
289
290 /*
291 * FIFO Flags
292 *
293 * Accel Front -- Driver should use front buffer only commands
294 */
295
296 #define SVGA_FIFO_FLAG_NONE 0
297 #define SVGA_FIFO_FLAG_ACCELFRONT (1<<0)
298
299
300 /*
301 * Drawing object ID's, in the range 0 to SVGA_MAX_ID
302 */
303
304 #define SVGA_MAX_ID 499
305
306 /*
307 * Macros to compute variable length items (sizes in 32-bit words, except
308 * for SVGA_GLYPH_SCANLINE_SIZE, which is in bytes).
309 */
310
311 #define SVGA_BITMAP_SIZE(w,h) ((((w)+31) >> 5) * (h))
312 #define SVGA_BITMAP_SCANLINE_SIZE(w) (( (w)+31 ) >> 5)
313 #define SVGA_PIXMAP_SIZE(w,h,bpp) ((( ((w)*(bpp))+31 ) >> 5) * (h))
314 #define SVGA_PIXMAP_SCANLINE_SIZE(w,bpp) (( ((w)*(bpp))+31 ) >> 5)
315 #define SVGA_GLYPH_SIZE(w,h) ((((((w) + 7) >> 3) * (h)) + 3) >> 2)
316 #define SVGA_GLYPH_SCANLINE_SIZE(w) (((w) + 7) >> 3)
317
318 /*
319 * Increment from one scanline to the next of a bitmap or pixmap
320 */
321 #define SVGA_BITMAP_INCREMENT(w) ((( (w)+31 ) >> 5) * sizeof (uint32))
322 #define SVGA_PIXMAP_INCREMENT(w,bpp) ((( ((w)*(bpp))+31 ) >> 5) * sizeof (uint32))
323
324 /*
325 * Transparent color for DRAW_GLYPH_CLIPPED
326 */
327 #define SVGA_COLOR_TRANSPARENT (~0)
328
329 /*
330 * Commands in the command FIFO
331 */
332
333 #define SVGA_CMD_INVALID_CMD 0
334 /* FIFO layout:
335 <nothing> (well, undefined) */
336
337 #define SVGA_CMD_UPDATE 1
338 /* FIFO layout:
339 X, Y, Width, Height */
340
341 #define SVGA_CMD_RECT_FILL 2
342 /* FIFO layout:
343 Color, X, Y, Width, Height */
344
345 #define SVGA_CMD_RECT_COPY 3
346 /* FIFO layout:
347 Source X, Source Y, Dest X, Dest Y, Width, Height */
348
349 #define SVGA_CMD_DEFINE_BITMAP 4
350 /* FIFO layout:
351 Pixmap ID, Width, Height, <scanlines> */
352
353 #define SVGA_CMD_DEFINE_BITMAP_SCANLINE 5
354 /* FIFO layout:
355 Pixmap ID, Width, Height, Line #, scanline */
356
357 #define SVGA_CMD_DEFINE_PIXMAP 6
358 /* FIFO layout:
359 Pixmap ID, Width, Height, Depth, <scanlines> */
360
361 #define SVGA_CMD_DEFINE_PIXMAP_SCANLINE 7
362 /* FIFO layout:
363 Pixmap ID, Width, Height, Depth, Line #, scanline */
364
365 #define SVGA_CMD_RECT_BITMAP_FILL 8
366 /* FIFO layout:
367 Bitmap ID, X, Y, Width, Height, Foreground, Background */
368
369 #define SVGA_CMD_RECT_PIXMAP_FILL 9
370 /* FIFO layout:
371 Pixmap ID, X, Y, Width, Height */
372
373 #define SVGA_CMD_RECT_BITMAP_COPY 10
374 /* FIFO layout:
375 Bitmap ID, Source X, Source Y, Dest X, Dest Y,
376 Width, Height, Foreground, Background */
377
378 #define SVGA_CMD_RECT_PIXMAP_COPY 11
379 /* FIFO layout:
380 Pixmap ID, Source X, Source Y, Dest X, Dest Y, Width, Height */
381
382 #define SVGA_CMD_FREE_OBJECT 12
383 /* FIFO layout:
384 Object (pixmap, bitmap, ...) ID */
385
386 #define SVGA_CMD_RECT_ROP_FILL 13
387 /* FIFO layout:
388 Color, X, Y, Width, Height, ROP */
389
390 #define SVGA_CMD_RECT_ROP_COPY 14
391 /* FIFO layout:
392 Source X, Source Y, Dest X, Dest Y, Width, Height, ROP */
393
394 #define SVGA_CMD_RECT_ROP_BITMAP_FILL 15
395 /* FIFO layout:
396 ID, X, Y, Width, Height, Foreground, Background, ROP */
397
398 #define SVGA_CMD_RECT_ROP_PIXMAP_FILL 16
399 /* FIFO layout:
400 ID, X, Y, Width, Height, ROP */
401
402 #define SVGA_CMD_RECT_ROP_BITMAP_COPY 17
403 /* FIFO layout:
404 ID, Source X, Source Y,
405 Dest X, Dest Y, Width, Height, Foreground, Background, ROP */
406
407 #define SVGA_CMD_RECT_ROP_PIXMAP_COPY 18
408 /* FIFO layout:
409 ID, Source X, Source Y, Dest X, Dest Y, Width, Height, ROP */
410
411 #define SVGA_CMD_DEFINE_CURSOR 19
412 /* FIFO layout:
413 ID, Hotspot X, Hotspot Y, Width, Height,
414 Depth for AND mask, Depth for XOR mask,
415 <scanlines for AND mask>, <scanlines for XOR mask> */
416
417 #define SVGA_CMD_DISPLAY_CURSOR 20
418 /* FIFO layout:
419 ID, On/Off (1 or 0) */
420
421 #define SVGA_CMD_MOVE_CURSOR 21
422 /* FIFO layout:
423 X, Y */
424
425 #define SVGA_CMD_DEFINE_ALPHA_CURSOR 22
426 /* FIFO layout:
427 ID, Hotspot X, Hotspot Y, Width, Height,
428 <scanlines> */
429
430 #define SVGA_CMD_DRAW_GLYPH 23
431 /* FIFO layout:
432 X, Y, W, H, FGCOLOR, <stencil buffer> */
433
434 #define SVGA_CMD_DRAW_GLYPH_CLIPPED 24
435 /* FIFO layout:
436 X, Y, W, H, FGCOLOR, BGCOLOR, <cliprect>, <stencil buffer>
437 Transparent color expands are done by setting BGCOLOR to ~0 */
438
439 #define SVGA_CMD_UPDATE_VERBOSE 25
440 /* FIFO layout:
441 X, Y, Width, Height, Reason */
442
443 #define SVGA_CMD_SURFACE_FILL 26
444 /* FIFO layout:
445 color, dstSurfaceOffset, x, y, w, h, rop */
446
447 #define SVGA_CMD_SURFACE_COPY 27
448 /* FIFO layout:
449 srcSurfaceOffset, dstSurfaceOffset, srcX, srcY,
450 destX, destY, w, h, rop */
451
452 #define SVGA_CMD_SURFACE_ALPHA_BLEND 28
453 /* FIFO layout:
454 srcSurfaceOffset, dstSurfaceOffset, srcX, srcY,
455 destX, destY, w, h, op (SVGA_BLENDOP*), flags (SVGA_BLENDFLAGS*),
456 param1, param2 */
457
458 #define SVGA_CMD_FRONT_ROP_FILL 29
459 /* FIFO layout:
460 Color, X, Y, Width, Height, ROP */
461
462 #define SVGA_CMD_FENCE 30
463 /* FIFO layout:
464 Fence value */
465
466 #define SVGA_CMD_MAX 31
467
468 #define SVGA_CMD_MAX_ARGS 64
469
470 /*
471 * Location and size of SVGA frame buffer and the FIFO.
472 */
473 #define SVGA_VRAM_MAX_SIZE (16 * 1024 * 1024)
474
475 #define SVGA_VRAM_SIZE_WS (16 * 1024 * 1024) // 16 MB
476 #define SVGA_MEM_SIZE_WS (2 * 1024 * 1024) // 2 MB
477 #define SVGA_VRAM_SIZE_SERVER (4 * 1024 * 1024) // 4 MB
478 #define SVGA_MEM_SIZE_SERVER (256 * 1024) // 256 KB
479
480 #if /* defined(VMX86_WGS) || */ defined(VMX86_SERVER)
481 #define SVGA_VRAM_SIZE SVGA_VRAM_SIZE_SERVER
482 #define SVGA_MEM_SIZE SVGA_MEM_SIZE_SERVER
483 #else
484 #define SVGA_VRAM_SIZE SVGA_VRAM_SIZE_WS
485 #define SVGA_MEM_SIZE SVGA_MEM_SIZE_WS
486 #endif
487
488 /*
489 * SVGA_FB_START is the default starting address of the SVGA frame
490 * buffer in the guest's physical address space.
491 * SVGA_FB_START_BIGMEM is the starting address of the SVGA frame
492 * buffer for VMs that have a large amount of physical memory.
493 *
494 * The address of SVGA_FB_START is set to 2GB - (SVGA_FB_MAX_SIZE + SVGA_MEM_SIZE),
495 * thus the SVGA frame buffer sits at [SVGA_FB_START .. 2GB-1] in the
496 * physical address space. Our older SVGA drivers for NT treat the
497 * address of the frame buffer as a signed integer. For backwards
498 * compatibility, we keep the default location of the frame buffer
499 * at under 2GB in the address space. This restricts VMs to have "only"
500 * up to ~2031MB (i.e., up to SVGA_FB_START) of physical memory.
501 *
502 * For VMs that want more memory than the ~2031MB, we place the SVGA
503 * frame buffer at SVGA_FB_START_BIGMEM. This allows VMs to have up
504 * to 3584MB, at least as far as the SVGA frame buffer is concerned
505 * (note that there may be other issues that limit the VM memory
506 * size). PCI devices use high memory addresses, so we have to put
507 * SVGA_FB_START_BIGMEM low enough so that it doesn't overlap with any
508 * of these devices. Placing SVGA_FB_START_BIGMEM at 0xE0000000
509 * should leave plenty of room for the PCI devices.
510 *
511 * NOTE: All of that is only true for the 0710 chipset. As of the 0405
512 * chipset, the framebuffer start is determined solely based on the value
513 * the guest BIOS or OS programs into the PCI base address registers.
514 */
515 #define SVGA_FB_LEGACY_START 0x7EFC0000
516 #define SVGA_FB_LEGACY_START_BIGMEM 0xE0000000
517
518 #endif
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