src/add-ons/accelerants/intel_810/i810_regs.h

   1 /*
   2  * Copyright 2012 Haiku, Inc.  All rights reserved.
   3  * Distributed under the terms of the MIT license.
   4  *
   5  * Authors:
   6  *              Gerald Zajac
   7  */
   8
   9 /*!
  10         Haiku Intel-810 video driver was adapted from the X.org intel driver which
  11         has the following copyright.
  12
  13         Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
  14         All Rights Reserved.
  15  */
  16 #ifndef __I810_REGS_H__
  17 #define __I810_REGS_H__
  18
  19
  20 // CRT Controller Registers.
  21 #define START_ADDR_HI                   0x0C
  22 #define START_ADDR_LO                   0x0D
  23 #define VERT_SYNC_END                   0x11
  24 #define EXT_VERT_TOTAL                  0x30
  25 #define EXT_VERT_DISPLAY                0x31
  26 #define EXT_VERT_SYNC_START             0x32
  27 #define EXT_VERT_BLANK_START    0x33
  28 #define EXT_HORIZ_TOTAL                 0x35
  29 #define EXT_HORIZ_BLANK                 0x39
  30 #define EXT_START_ADDR                  0x40
  31 #define EXT_START_ADDR_ENABLE   0x80
  32 #define EXT_OFFSET                              0x41
  33 #define EXT_START_ADDR_HI               0x42
  34 #define INTERLACE_CNTL                  0x70
  35 #define INTERLACE_ENABLE                0x80
  36 #define INTERLACE_DISABLE               0x00
  37
  38 // CR80 - IO Control
  39 #define IO_CTNL                                 0x80
  40 #define EXTENDED_ATTR_CNTL              0x02
  41 #define EXTENDED_CRTC_CNTL              0x01
  42
  43 // GR10 - Address mapping
  44 #define ADDRESS_MAPPING                 0x10
  45 #define PAGE_TO_LOCAL_MEM_ENABLE 0x10
  46 #define GTT_MEM_MAP_ENABLE              0x08
  47 #define PACKED_MODE_ENABLE              0x04
  48 #define LINEAR_MODE_ENABLE              0x02
  49 #define PAGE_MAPPING_ENABLE             0x01
  50
  51 #define FENCE                   0x2000
  52
  53 #define INST_DONE               0x2090
  54
  55 // General error reporting regs.
  56 #define EIR                             0x20B0
  57 #define EMR                             0x20B4
  58 #define ESR                             0x20B8
  59
  60 // FIFO Watermark and Burst Length Control Register.
  61 #define FWATER_BLC                      0x20d8
  62 #define MM_BURST_LENGTH                 0x00700000
  63 #define MM_FIFO_WATERMARK               0x0001F000
  64 #define LM_BURST_LENGTH                 0x00000700
  65 #define LM_FIFO_WATERMARK               0x0000001F
  66
  67 #define MEM_MODE                        0x020DC
  68
  69 #define DRAM_ROW_CNTL_HI        0x3002
  70 #define DRAM_REFRESH_RATE               0x18
  71 #define DRAM_REFRESH_DISABLE    0x00
  72 #define DRAM_REFRESH_60HZ               0x08
  73
  74 #define VCLK2_VCO_M                     0x6008
  75 #define VCLK2_VCO_N                     0x600a
  76 #define VCLK2_VCO_DIV_SEL       0x6012
  77
  78 #define PIXPIPE_CONFIG          0x70008
  79 #define NO_BLANK_DELAY                  0x100000
  80 #define DISPLAY_8BPP_MODE               0x020000
  81 #define DISPLAY_15BPP_MODE              0x040000
  82 #define DISPLAY_16BPP_MODE              0x050000
  83 #define DAC_8_BIT                               0x008000
  84 #define HIRES_MODE                              0x000001
  85
  86 // Blitter control.
  87 #define BITBLT_CNTL                     0x7000c
  88 #define COLEXP_MODE                             0x30
  89 #define COLEXP_8BPP                             0x00
  90 #define COLEXP_16BPP                    0x10
  91
  92 // Color Palette Registers.
  93 #define DAC_MASK                0x3C6
  94 #define DAC_W_INDEX             0x3C8
  95 #define DAC_DATA                0x3C9
  96
  97
  98 #define MISC_OUT_R              0x3CC           // read
  99 #define MISC_OUT_W              0x3C2           // write
 100 #define SEQ_INDEX               0x3C4
 101 #define SEQ_DATA                0x3C5
 102 #define GRAPH_INDEX             0x3CE
 103 #define GRAPH_DATA              0x3CF
 104 #define CRTC_INDEX              0x3D4
 105 #define CRTC_DATA               0x3D5
 106
 107
 108 // Macros for memory mapped I/O.
 109 //==============================
 110
 111 #define INREG8(addr)            (*((vuint8*)(gInfo.regs + (addr))))
 112 #define INREG16(addr)           (*((vuint16*)(gInfo.regs + (addr))))
 113 #define INREG32(addr)           (*((vuint32*)(gInfo.regs + (addr))))
 114
 115 #define OUTREG8(addr, val)      (*((vuint8*)(gInfo.regs + (addr))) = (val))
 116 #define OUTREG16(addr, val)     (*((vuint16*)(gInfo.regs + (addr))) = (val))
 117 #define OUTREG32(addr, val)     (*((vuint32*)(gInfo.regs + (addr))) = (val))
 118
 119 // Write a value to an 32-bit reg using a mask.  The mask selects the
 120 // bits to be modified.
 121 #define OUTREGM(addr, value, mask)      \
 122         (OUTREG(addr, (INREG(addr) & ~mask) | (value & mask)))
 123
 124
 125 static inline uint8
 126 ReadCrtcReg(uint8 index)
 127 {
 128         OUTREG8(CRTC_INDEX, index);
 129         return INREG8(CRTC_DATA);
 130 }
 131
 132
 133 static inline void
 134 WriteCrtcReg(uint8 index, uint8 value)
 135 {
 136         OUTREG8(CRTC_INDEX, index);
 137         OUTREG8(CRTC_DATA, value);
 138 }
 139
 140
 141 static inline uint8
 142 ReadGraphReg(uint8 index)
 143 {
 144         OUTREG8(GRAPH_INDEX, index);
 145         return INREG8(GRAPH_DATA);
 146 }
 147
 148
 149 static inline void
 150 WriteGraphReg(uint8 index, uint8 value)
 151 {
 152         OUTREG8(GRAPH_INDEX, index);
 153         OUTREG8(GRAPH_DATA, value);
 154 }
 155
 156
 157 static inline uint8
 158 ReadSeqReg(uint8 index)
 159 {
 160         OUTREG8(SEQ_INDEX, index);
 161         return INREG8(SEQ_DATA);
 162 }
 163
 164
 165 static inline void
 166 WriteSeqReg(uint8 index, uint8 value)
 167 {
 168         OUTREG8(SEQ_INDEX, index);
 169         OUTREG8(SEQ_DATA, value);
 170 }
 171
 172
 173 #endif  // __I810_REGS_H__