src/add-ons/accelerants/via/engine/crtc2.c

   1 /* second CTRC functionality for GeForce cards */
   2 /* Author:
   3    Rudolf Cornelissen 11/2002-9/2004
   4 */
   5
   6 #define MODULE_BIT 0x00020000
   7
   8 #include "std.h"
   9
  10 /*Adjust passed parameters to a valid mode line*/
  11 status_t eng_crtc2_validate_timing(
  12         uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
  13         uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt
  14 )
  15 {
  16 /* horizontal */
  17         /* make all parameters multiples of 8 */
  18         *hd_e &= 0xfff8;
  19         *hs_s &= 0xfff8;
  20         *hs_e &= 0xfff8;
  21         *ht   &= 0xfff8;
  22
  23         /* confine to required number of bits, taking logic into account */
  24         if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3);
  25         if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3);
  26         if (*hs_e > ( 0x01ff      << 3)) *hs_e = ( 0x01ff      << 3);
  27         if (*ht   > ((0x01ff + 5) << 3)) *ht   = ((0x01ff + 5) << 3);
  28
  29         /* NOTE: keep horizontal timing at multiples of 8! */
  30         /* confine to a reasonable width */
  31         if (*hd_e < 640) *hd_e = 640;
  32         if (*hd_e > 2048) *hd_e = 2048;
  33
  34         /* if hor. total does not leave room for a sensible sync pulse, increase it! */
  35         if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80);
  36
  37         /* if hor. total does not adhere to max. blanking pulse width, decrease it! */
  38         if (*ht > (*hd_e + 0x3f8)) *ht = (*hd_e + 0x3f8);
  39
  40         /* make sure sync pulse is not during display */
  41         if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8);
  42         if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8);
  43
  44         /* correct sync pulse if it is too long:
  45          * there are only 5 bits available to save this in the card registers! */
  46         if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8);
  47
  48 /*vertical*/
  49         /* confine to required number of bits, taking logic into account */
  50         //fixme if needed: on GeForce cards there are 12 instead of 11 bits...
  51         if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2);
  52         if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1);
  53         if (*vs_e >  0x7ff     ) *vs_e =  0x7ff     ;
  54         if (*vt   > (0x7ff + 2)) *vt   = (0x7ff + 2);
  55
  56         /* confine to a reasonable height */
  57         if (*vd_e < 480) *vd_e = 480;
  58         if (*vd_e > 1536) *vd_e = 1536;
  59
  60         /*if vertical total does not leave room for a sync pulse, increase it!*/
  61         if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3);
  62
  63         /* if vert. total does not adhere to max. blanking pulse width, decrease it! */
  64         if (*vt > (*vd_e + 0xff)) *vt = (*vd_e + 0xff);
  65
  66         /* make sure sync pulse is not during display */
  67         if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1);
  68         if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1);
  69
  70         /* correct sync pulse if it is too long:
  71          * there are only 4 bits available to save this in the card registers! */
  72         if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f);
  73
  74         return B_OK;
  75 }
  76
  77 /*set a mode line - inputs are in pixels*/
  78 status_t eng_crtc2_set_timing(display_mode target)
  79 {
  80         uint8 temp;
  81
  82         uint32 htotal;          /*total horizontal total VCLKs*/
  83         uint32 hdisp_e;            /*end of horizontal display (begins at 0)*/
  84         uint32 hsync_s;            /*begin of horizontal sync pulse*/
  85         uint32 hsync_e;            /*end of horizontal sync pulse*/
  86         uint32 hblnk_s;            /*begin horizontal blanking*/
  87         uint32 hblnk_e;            /*end horizontal blanking*/
  88
  89         uint32 vtotal;          /*total vertical total scanlines*/
  90         uint32 vdisp_e;            /*end of vertical display*/
  91         uint32 vsync_s;            /*begin of vertical sync pulse*/
  92         uint32 vsync_e;            /*end of vertical sync pulse*/
  93         uint32 vblnk_s;            /*begin vertical blanking*/
  94         uint32 vblnk_e;            /*end vertical blanking*/
  95
  96         uint32 linecomp;        /*split screen and vdisp_e interrupt*/
  97
  98         LOG(4,("CRTC2: setting timing\n"));
  99
 100         /* setup tuned internal modeline for flatpanel if connected and active */
 101         /* notes:
 102          * - the CRTC modeline must end earlier than the panel modeline to keep correct
 103          *   sync going;
 104          * - if the CRTC modeline ends too soon, pixelnoise will occur in 8 (or so) pixel
 105          *   wide horizontal stripes. This can be observed earliest on fullscreen overlay,
 106          *   and if it gets worse, also normal desktop output will suffer. The stripes
 107          *   are mainly visible at the left of the screen, over the entire screen height. */
 108         if (si->ps.tmds2_active)
 109         {
 110                 LOG(2,("CRTC2: DFP active: tuning modeline\n"));
 111
 112                 /* horizontal timing */
 113                 target.timing.h_sync_start =
 114                         ((uint16)((si->ps.p2_timing.h_sync_start / ((float)si->ps.p2_timing.h_display)) *
 115                         target.timing.h_display)) & 0xfff8;
 116
 117                 target.timing.h_sync_end =
 118                         ((uint16)((si->ps.p2_timing.h_sync_end / ((float)si->ps.p2_timing.h_display)) *
 119                         target.timing.h_display)) & 0xfff8;
 120
 121                 target.timing.h_total =
 122                         (((uint16)((si->ps.p2_timing.h_total / ((float)si->ps.p2_timing.h_display)) *
 123                         target.timing.h_display)) & 0xfff8) - 8;
 124
 125                 /* in native mode the CRTC needs some extra time to keep synced correctly;
 126                  * OTOH the overlay unit distorts if we reserve too much time! */
 127                 if (target.timing.h_display == si->ps.p2_timing.h_display)
 128                 {
 129                         /* NV11 timing has different constraints than later cards */
 130                         if (si->ps.card_type == NV11)
 131                                 target.timing.h_total -= 56;
 132                         else
 133                                 /* confirmed NV34 with 1680x1050 panel */
 134                                 target.timing.h_total -= 32;
 135                 }
 136
 137                 if (target.timing.h_sync_start == target.timing.h_display)
 138                         target.timing.h_sync_start += 8;
 139                 if (target.timing.h_sync_end == target.timing.h_total)
 140                         target.timing.h_sync_end -= 8;
 141
 142                 /* vertical timing */
 143                 target.timing.v_sync_start =
 144                         ((uint16)((si->ps.p2_timing.v_sync_start / ((float)si->ps.p2_timing.v_display)) *
 145                         target.timing.v_display));
 146
 147                 target.timing.v_sync_end =
 148                         ((uint16)((si->ps.p2_timing.v_sync_end / ((float)si->ps.p2_timing.v_display)) *
 149                         target.timing.v_display));
 150
 151                 target.timing.v_total =
 152                         ((uint16)((si->ps.p2_timing.v_total / ((float)si->ps.p2_timing.v_display)) *
 153                         target.timing.v_display)) - 1;
 154
 155                 if (target.timing.v_sync_start == target.timing.v_display)
 156                         target.timing.v_sync_start += 1;
 157                 if (target.timing.v_sync_end == target.timing.v_total)
 158                         target.timing.v_sync_end -= 1;
 159
 160                 /* disable GPU scaling testmode so automatic scaling will be done */
 161                 DAC2W(FP_DEBUG1, 0);
 162         }
 163
 164         /* Modify parameters as required by standard VGA */
 165         htotal = ((target.timing.h_total >> 3) - 5);
 166         hdisp_e = ((target.timing.h_display >> 3) - 1);
 167         hblnk_s = hdisp_e;
 168         hblnk_e = (htotal + 4);//0;
 169         hsync_s = (target.timing.h_sync_start >> 3);
 170         hsync_e = (target.timing.h_sync_end >> 3);
 171
 172         vtotal = target.timing.v_total - 2;
 173         vdisp_e = target.timing.v_display - 1;
 174         vblnk_s = vdisp_e;
 175         vblnk_e = (vtotal + 1);
 176         vsync_s = target.timing.v_sync_start;//-1;
 177         vsync_e = target.timing.v_sync_end;//-1;
 178
 179         /* prevent memory adress counter from being reset (linecomp may not occur) */
 180         linecomp = target.timing.v_display;
 181
 182         /* enable access to secondary head */
 183         set_crtc_owner(1);
 184
 185         /* Note for laptop and DVI flatpanels:
 186          * CRTC timing has a seperate set of registers from flatpanel timing.
 187          * The flatpanel timing registers have scaling registers that are used to match
 188          * these two modelines. */
 189         {
 190                 LOG(4,("CRTC2: Setting full timing...\n"));
 191
 192                 /* log the mode that will be set */
 193                 LOG(2,("CRTC2:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e));
 194                 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e));
 195
 196                 /* actually program the card! */
 197                 /* unlock CRTC registers at index 0-7 */
 198                 CRTC2W(VSYNCE, (CRTC2R(VSYNCE) & 0x7f));
 199                 /* horizontal standard VGA regs */
 200                 CRTC2W(HTOTAL, (htotal & 0xff));
 201                 CRTC2W(HDISPE, (hdisp_e & 0xff));
 202                 CRTC2W(HBLANKS, (hblnk_s & 0xff));
 203                 /* also unlock vertical retrace registers in advance */
 204                 CRTC2W(HBLANKE, ((hblnk_e & 0x1f) | 0x80));
 205                 CRTC2W(HSYNCS, (hsync_s & 0xff));
 206                 CRTC2W(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2)));
 207
 208                 /* vertical standard VGA regs */
 209                 CRTC2W(VTOTAL, (vtotal & 0xff));
 210                 CRTC2W(OVERFLOW,
 211                 (
 212                         ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) |
 213                         ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) |
 214                         ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) |
 215                         ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4))
 216                 ));
 217                 CRTC2W(PRROWSCN, 0x00); /* not used */
 218                 CRTC2W(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6))));
 219                 CRTC2W(VSYNCS, (vsync_s & 0xff));
 220                 CRTC2W(VSYNCE, ((CRTC2R(VSYNCE) & 0xf0) | (vsync_e & 0x0f)));
 221                 CRTC2W(VDISPE, (vdisp_e & 0xff));
 222                 CRTC2W(VBLANKS, (vblnk_s & 0xff));
 223                 CRTC2W(VBLANKE, (vblnk_e & 0xff));
 224                 CRTC2W(LINECOMP, (linecomp & 0xff));
 225
 226                 /* horizontal extended regs */
 227                 //fixme: we reset bit4. is this correct??
 228                 CRTC2W(HEB, (CRTC2R(HEB) & 0xe0) |
 229                         (
 230                         ((htotal & 0x100) >> (8 - 0)) |
 231                         ((hdisp_e & 0x100) >> (8 - 1)) |
 232                         ((hblnk_s & 0x100) >> (8 - 2)) |
 233                         ((hsync_s & 0x100) >> (8 - 3))
 234                         ));
 235
 236                 /* (mostly) vertical extended regs */
 237                 CRTC2W(LSR,
 238                         (
 239                         ((vtotal & 0x400) >> (10 - 0)) |
 240                         ((vdisp_e & 0x400) >> (10 - 1)) |
 241                         ((vsync_s & 0x400) >> (10 - 2)) |
 242                         ((vblnk_s & 0x400) >> (10 - 3)) |
 243                         ((hblnk_e & 0x040) >> (6 - 4))
 244                         //fixme: we still miss one linecomp bit!?! is this it??
 245                         //| ((linecomp & 0x400) >> 3)
 246                         ));
 247
 248                 /* more vertical extended regs */
 249                 CRTC2W(EXTRA,
 250                         (
 251                         ((vtotal & 0x800) >> (11 - 0)) |
 252                         ((vdisp_e & 0x800) >> (11 - 2)) |
 253                         ((vsync_s & 0x800) >> (11 - 4)) |
 254                         ((vblnk_s & 0x800) >> (11 - 6))
 255                         //fixme: do we miss another linecomp bit!?!
 256                         ));
 257
 258                 /* setup 'large screen' mode */
 259                 if (target.timing.h_display >= 1280)
 260                         CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xfb));
 261                 else
 262                         CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x04));
 263
 264                 /* setup HSYNC & VSYNC polarity */
 265                 LOG(2,("CRTC2: sync polarity: "));
 266                 temp = ENG_REG8(RG8_MISCR);
 267                 if (target.timing.flags & B_POSITIVE_HSYNC)
 268                 {
 269                         LOG(2,("H:pos "));
 270                         temp &= ~0x40;
 271                 }
 272                 else
 273                 {
 274                         LOG(2,("H:neg "));
 275                         temp |= 0x40;
 276                 }
 277                 if (target.timing.flags & B_POSITIVE_VSYNC)
 278                 {
 279                         LOG(2,("V:pos "));
 280                         temp &= ~0x80;
 281                 }
 282                 else
 283                 {
 284                         LOG(2,("V:neg "));
 285                         temp |= 0x80;
 286                 }
 287                 ENG_REG8(RG8_MISCW) = temp;
 288
 289                 LOG(2,(", MISC reg readback: $%02x\n", ENG_REG8(RG8_MISCR)));
 290         }
 291
 292         /* always disable interlaced operation */
 293         /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */
 294         CRTC2W(INTERLACE, 0xff);
 295
 296         /* disable CRTC slaved mode unless a panel is in use */
 297         // fixme: this kills TVout when it was in use...
 298         if (!si->ps.tmds2_active) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x7f));
 299
 300         /* setup flatpanel if connected and active */
 301         if (si->ps.tmds2_active)
 302         {
 303                 uint32 iscale_x, iscale_y;
 304
 305                 /* calculate inverse scaling factors used by hardware in 20.12 format */
 306                 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p2_timing.h_display);
 307                 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p2_timing.v_display);
 308
 309                 /* unblock flatpanel timing programming (or something like that..) */
 310                 CRTC2W(FP_HTIMING, 0);
 311                 CRTC2W(FP_VTIMING, 0);
 312                 LOG(2,("CRTC2: FP_HTIMING reg readback: $%02x\n", CRTC2R(FP_HTIMING)));
 313                 LOG(2,("CRTC2: FP_VTIMING reg readback: $%02x\n", CRTC2R(FP_VTIMING)));
 314
 315                 /* enable full width visibility on flatpanel */
 316                 DAC2W(FP_HVALID_S, 0);
 317                 DAC2W(FP_HVALID_E, (si->ps.p2_timing.h_display - 1));
 318                 /* enable full height visibility on flatpanel */
 319                 DAC2W(FP_VVALID_S, 0);
 320                 DAC2W(FP_VVALID_E, (si->ps.p2_timing.v_display - 1));
 321
 322                 /* nVidia cards support upscaling except on ??? */
 323                 /* NV11 cards can upscale after all! */
 324                 if (0)//si->ps.card_type == NV11)
 325                 {
 326                         /* disable last fetched line limiting */
 327                         DAC2W(FP_DEBUG2, 0x00000000);
 328                         /* inform panel to scale if needed */
 329                         if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12)))
 330                         {
 331                                 LOG(2,("CRTC2: DFP needs to do scaling\n"));
 332                                 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) | 0x00000100));
 333                         }
 334                         else
 335                         {
 336                                 LOG(2,("CRTC2: no scaling for DFP needed\n"));
 337                                 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff));
 338                         }
 339                 }
 340                 else
 341                 {
 342                         float dm_aspect;
 343
 344                         LOG(2,("CRTC2: GPU scales for DFP if needed\n"));
 345
 346                         /* calculate display mode aspect */
 347                         dm_aspect = (target.timing.h_display / ((float)target.timing.v_display));
 348
 349                         /* limit last fetched line if vertical scaling is done */
 350                         if (iscale_y != (1 << 12))
 351                                 DAC2W(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16)));
 352                         else
 353                                 DAC2W(FP_DEBUG2, 0x00000000);
 354
 355                         /* inform panel not to scale */
 356                         DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff));
 357
 358                         /* GPU scaling is automatically setup by hardware, so only modify this
 359                          * scalingfactor for non 4:3 (1.33) aspect panels;
 360                          * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */
 361
 362                         /* correct for widescreen panels relative to mode...
 363                          * (so if panel is more widescreen than mode being set) */
 364                         /* BTW: known widescreen panels:
 365                          * 1280 x  800 (1.60),
 366                          * 1440 x  900 (1.60),
 367                          * 1680 x 1050 (1.60),
 368                          * 1920 x 1200 (1.60). */
 369                         /* known 4:3 aspect non-standard resolution panels:
 370                          * 1400 x 1050 (1.33). */
 371                         /* NOTE:
 372                          * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */
 373                         if ((iscale_x != (1 << 12)) && (si->ps.panel2_aspect > (dm_aspect + 0.10)))
 374                         {
 375                                 uint16 diff;
 376
 377                                 LOG(2,("CRTC2: (relative) widescreen panel: tuning horizontal scaling\n"));
 378
 379                                 /* X-scaling should be the same as Y-scaling */
 380                                 iscale_x = iscale_y;
 381                                 /* enable testmode (b12) and program new X-scaling factor */
 382                                 DAC2W(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12)));
 383                                 /* center/cut-off left and right side of screen */
 384                                 diff = ((si->ps.p2_timing.h_display -
 385                                                 (target.timing.h_display * ((1 << 12) / ((float)iscale_x))))
 386                                                 / 2);
 387                                 DAC2W(FP_HVALID_S, diff);
 388                                 DAC2W(FP_HVALID_E, ((si->ps.p2_timing.h_display - diff) - 1));
 389                         }
 390                         /* correct for portrait panels... */
 391                         /* NOTE:
 392                          * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */
 393                         if ((iscale_y != (1 << 12)) && (si->ps.panel2_aspect < (dm_aspect - 0.10)))
 394                         {
 395                                 LOG(2,("CRTC2: (relative) portrait panel: should tune vertical scaling\n"));
 396                                 /* fixme: implement if this kind of portrait panels exist on nVidia... */
 397                         }
 398                 }
 399
 400                 /* do some logging.. */
 401                 LOG(2,("CRTC2: FP_HVALID_S reg readback: $%08x\n", DAC2R(FP_HVALID_S)));
 402                 LOG(2,("CRTC2: FP_HVALID_E reg readback: $%08x\n", DAC2R(FP_HVALID_E)));
 403                 LOG(2,("CRTC2: FP_VVALID_S reg readback: $%08x\n", DAC2R(FP_VVALID_S)));
 404                 LOG(2,("CRTC2: FP_VVALID_E reg readback: $%08x\n", DAC2R(FP_VVALID_E)));
 405                 LOG(2,("CRTC2: FP_DEBUG0 reg readback: $%08x\n", DAC2R(FP_DEBUG0)));
 406                 LOG(2,("CRTC2: FP_DEBUG1 reg readback: $%08x\n", DAC2R(FP_DEBUG1)));
 407                 LOG(2,("CRTC2: FP_DEBUG2 reg readback: $%08x\n", DAC2R(FP_DEBUG2)));
 408                 LOG(2,("CRTC2: FP_DEBUG3 reg readback: $%08x\n", DAC2R(FP_DEBUG3)));
 409                 LOG(2,("CRTC2: FP_TG_CTRL reg readback: $%08x\n", DAC2R(FP_TG_CTRL)));
 410         }
 411
 412         return B_OK;
 413 }
 414
 415 status_t eng_crtc2_depth(int mode)
 416 {
 417         uint8 viddelay = 0;
 418         uint32 genctrl = 0;
 419
 420         /* set VCLK scaling */
 421         switch(mode)
 422         {
 423         case BPP8:
 424                 viddelay = 0x01;
 425                 /* genctrl b4 & b5 reset: 'direct mode' */
 426                 genctrl = 0x00101100;
 427                 break;
 428         case BPP15:
 429                 viddelay = 0x02;
 430                 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
 431                 genctrl = 0x00100130;
 432                 break;
 433         case BPP16:
 434                 viddelay = 0x02;
 435                 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
 436                 genctrl = 0x00101130;
 437                 break;
 438         case BPP24:
 439                 viddelay = 0x03;
 440                 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
 441                 genctrl = 0x00100130;
 442                 break;
 443         case BPP32:
 444                 viddelay = 0x03;
 445                 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */
 446                 genctrl = 0x00101130;
 447                 break;
 448         }
 449         /* enable access to secondary head */
 450         set_crtc_owner(1);
 451
 452         CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xfc) | viddelay));
 453         DAC2W(GENCTRL, genctrl);
 454
 455         return B_OK;
 456 }
 457
 458 status_t eng_crtc2_dpms(bool display, bool h, bool v)
 459 {
 460         uint8 temp;
 461
 462         LOG(4,("CRTC2: setting DPMS: "));
 463
 464         /* enable access to secondary head */
 465         set_crtc_owner(1);
 466
 467         /* start synchronous reset: required before turning screen off! */
 468         SEQW(RESET, 0x01);
 469
 470         /* turn screen off */
 471         temp = SEQR(CLKMODE);
 472         if (display)
 473         {
 474                 SEQW(CLKMODE, (temp & ~0x20));
 475
 476                 /* end synchronous reset if display should be enabled */
 477                 SEQW(RESET, 0x03);
 478
 479                 //'safe mode' test! feedback needed with this 'setting'!
 480                 if (0)//si->ps.tmds2_active)
 481                 {
 482                         /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink)
 483                          * internal transmitters... */
 484                         /* note:
 485                          * the powerbits in this register are hardwired to the DVI connectors,
 486                          * instead of to the DACs! (confirmed NV34) */
 487                         //fixme...
 488                         DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) & 0xcfffffff));
 489                         /* ... and powerup external TMDS transmitter if it exists */
 490                         /* (confirmed OK on NV28 and NV34) */
 491                         CRTC2W(0x59, (CRTC2R(0x59) | 0x01));
 492                 }
 493
 494                 LOG(4,("display on, "));
 495         }
 496         else
 497         {
 498                 SEQW(CLKMODE, (temp | 0x20));
 499
 500                 //'safe mode' test! feedback needed with this 'setting'!
 501                 if (0)//si->ps.tmds2_active)
 502                 {
 503                         /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink)
 504                          * internal transmitters... */
 505                         /* note:
 506                          * the powerbits in this register are hardwired to the DVI connectors,
 507                          * instead of to the DACs! (confirmed NV34) */
 508                         //fixme...
 509                         DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) | 0x30000000));
 510                         /* ... and powerdown external TMDS transmitter if it exists */
 511                         /* (confirmed OK on NV28 and NV34) */
 512                         CRTC2W(0x59, (CRTC2R(0x59) & 0xfe));
 513                 }
 514
 515                 LOG(4,("display off, "));
 516         }
 517
 518         if (h)
 519         {
 520                 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0x7f));
 521                 LOG(4,("hsync enabled, "));
 522         }
 523         else
 524         {
 525                 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x80));
 526                 LOG(4,("hsync disabled, "));
 527         }
 528         if (v)
 529         {
 530                 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf));
 531                 LOG(4,("vsync enabled\n"));
 532         }
 533         else
 534         {
 535                 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x40));
 536                 LOG(4,("vsync disabled\n"));
 537         }
 538
 539         return B_OK;
 540 }
 541
 542 status_t eng_crtc2_dpms_fetch(bool *display, bool *h, bool *v)
 543 {
 544         /* enable access to secondary head */
 545         set_crtc_owner(1);
 546
 547         *display = !(SEQR(CLKMODE) & 0x20);
 548         *h = !(CRTC2R(REPAINT1) & 0x80);
 549         *v = !(CRTC2R(REPAINT1) & 0x40);
 550
 551         LOG(4,("CTRC2: fetched DPMS state: "));
 552         if (*display) LOG(4,("display on, "));
 553         else LOG(4,("display off, "));
 554         if (*h) LOG(4,("hsync enabled, "));
 555         else LOG(4,("hsync disabled, "));
 556         if (*v) LOG(4,("vsync enabled\n"));
 557         else LOG(4,("vsync disabled\n"));
 558
 559         return B_OK;
 560 }
 561
 562 status_t eng_crtc2_set_display_pitch()
 563 {
 564         uint32 offset;
 565
 566         LOG(4,("CRTC2: setting card pitch (offset between lines)\n"));
 567
 568         /* figure out offset value hardware needs */
 569         offset = si->fbc.bytes_per_row / 8;
 570
 571         LOG(2,("CRTC2: offset register set to: $%04x\n", offset));
 572
 573         /* enable access to secondary head */
 574         set_crtc_owner(1);
 575
 576         /* program the card */
 577         CRTC2W(PITCHL, (offset & 0x00ff));
 578         CRTC2W(REPAINT0, ((CRTC2R(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3)));
 579
 580         return B_OK;
 581 }
 582
 583 status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp)
 584 {
 585         uint32 timeout = 0;
 586
 587         LOG(4,("CRTC2: setting card RAM to be displayed bpp %d\n", bpp));
 588
 589         LOG(2,("CRTC2: startadd: $%08x\n", startadd));
 590         LOG(2,("CRTC2: frameRAM: $%08x\n", si->framebuffer));
 591         LOG(2,("CRTC2: framebuffer: $%08x\n", si->fbc.frame_buffer));
 592
 593         /* we might have no retraces during setmode! */
 594         /* wait 25mS max. for retrace to occur (refresh > 40Hz) */
 595         while (((ENG_REG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) &&
 596                         (timeout < (25000/10)))
 597         {
 598                 /* don't snooze much longer or retrace might get missed! */
 599                 snooze(10);
 600                 timeout++;
 601         }
 602
 603         /* enable access to secondary head */
 604         set_crtc_owner(1);
 605
 606         /* upto 4Gb RAM adressing: must be used on NV10 and later! */
 607         /* NOTE:
 608          * While this register also exists on pre-NV10 cards, it will
 609          * wrap-around at 16Mb boundaries!! */
 610
 611         /* 30bit adress in 32bit words */
 612         ENG_REG32(RG32_NV10FB2STADD32) = (startadd & 0xfffffffc);
 613
 614         /* set byte adress: (b0 - 1) */
 615         ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1));
 616
 617         return B_OK;
 618 }
 619
 620 status_t eng_crtc2_cursor_init()
 621 {
 622         int i;
 623         uint32 * fb;
 624         /* cursor bitmap will be stored at the start of the framebuffer */
 625         const uint32 curadd = 0;
 626
 627         /* enable access to secondary head */
 628         set_crtc_owner(1);
 629
 630         /* set cursor bitmap adress ... */
 631         if (si->ps.laptop)
 632         {
 633                 /* must be used this way on pre-NV10 and on all 'Go' cards! */
 634
 635                 /* cursorbitmap must start on 2Kbyte boundary: */
 636                 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */
 637                 CRTC2W(CURCTL0, ((curadd & 0x0001f800) >> 9));
 638                 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */
 639                 CRTC2W(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80));
 640                 /* set adress bit24-31 */
 641                 CRTC2W(CURCTL2, ((curadd & 0xff000000) >> 24));
 642         }
 643         else
 644         {
 645                 /* upto 4Gb RAM adressing:
 646                  * can be used on NV10 and later (except for 'Go' cards)! */
 647                 /* NOTE:
 648                  * This register does not exist on pre-NV10 and 'Go' cards. */
 649
 650                 /* cursorbitmap must still start on 2Kbyte boundary: */
 651                 ENG_REG32(RG32_NV10CUR2ADD32) = (curadd & 0xfffff800);
 652         }
 653
 654         /* set cursor colour: not needed because of direct nature of cursor bitmap. */
 655
 656         /*clear cursor*/
 657         fb = (uint32 *) si->framebuffer + curadd;
 658         for (i=0;i<(2048/4);i++)
 659         {
 660                 fb[i]=0;
 661         }
 662
 663         /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */
 664         ENG_REG32(RG32_2CURCONF) = 0x02000100;
 665
 666         /* activate hardware cursor */
 667         eng_crtc2_cursor_show();
 668
 669         return B_OK;
 670 }
 671
 672 status_t eng_crtc2_cursor_show()
 673 {
 674         LOG(4,("CRTC2: enabling cursor\n"));
 675
 676         /* enable access to secondary head */
 677         set_crtc_owner(1);
 678
 679         /* b0 = 1 enables cursor */
 680         CRTC2W(CURCTL0, (CRTC2R(CURCTL0) | 0x01));
 681
 682         return B_OK;
 683 }
 684
 685 status_t eng_crtc2_cursor_hide()
 686 {
 687         LOG(4,("CRTC2: disabling cursor\n"));
 688
 689         /* enable access to secondary head */
 690         set_crtc_owner(1);
 691
 692         /* b0 = 0 disables cursor */
 693         CRTC2W(CURCTL0, (CRTC2R(CURCTL0) & 0xfe));
 694
 695         return B_OK;
 696 }
 697
 698 /*set up cursor shape*/
 699 status_t eng_crtc2_cursor_define(uint8* andMask,uint8* xorMask)
 700 {
 701         int x, y;
 702         uint8 b;
 703         uint16 *cursor;
 704         uint16 pixel;
 705
 706         /* get a pointer to the cursor */
 707         cursor = (uint16*) si->framebuffer;
 708
 709         /* draw the cursor */
 710         /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */
 711         for (y = 0; y < 16; y++)
 712         {
 713                 b = 0x80;
 714                 for (x = 0; x < 8; x++)
 715                 {
 716                         /* preset transparant */
 717                         pixel = 0x0000;
 718                         /* set white if requested */
 719                         if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff;
 720                         /* set black if requested */
 721                         if ((!(*andMask & b)) &&   (*xorMask & b))  pixel = 0x8000;
 722                         /* set invert if requested */
 723                         if (  (*andMask & b)  &&   (*xorMask & b))  pixel = 0x7fff;
 724                         /* place the pixel in the bitmap */
 725                         cursor[x + (y * 32)] = pixel;
 726                         b >>= 1;
 727                 }
 728                 xorMask++;
 729                 andMask++;
 730                 b = 0x80;
 731                 for (; x < 16; x++)
 732                 {
 733                         /* preset transparant */
 734                         pixel = 0x0000;
 735                         /* set white if requested */
 736                         if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff;
 737                         /* set black if requested */
 738                         if ((!(*andMask & b)) &&   (*xorMask & b))  pixel = 0x8000;
 739                         /* set invert if requested */
 740                         if (  (*andMask & b)  &&   (*xorMask & b))  pixel = 0x7fff;
 741                         /* place the pixel in the bitmap */
 742                         cursor[x + (y * 32)] = pixel;
 743                         b >>= 1;
 744                 }
 745                 xorMask++;
 746                 andMask++;
 747         }
 748
 749         return B_OK;
 750 }
 751
 752 /* position the cursor */
 753 status_t eng_crtc2_cursor_position(uint16 x, uint16 y)
 754 {
 755         uint16 yhigh;
 756
 757         /* make sure we are beyond the first line of the cursorbitmap being drawn during
 758          * updating the position to prevent distortions: no double buffering feature */
 759         /* Note:
 760          * we need to return as quick as possible or some apps will exhibit lagging.. */
 761
 762         /* read the old cursor Y position */
 763         yhigh = ((DAC2R(CURPOS) & 0x0fff0000) >> 16);
 764         /* make sure we will wait until we are below both the old and new Y position:
 765          * visible cursorbitmap drawing needs to be done at least... */
 766         if (y > yhigh) yhigh = y;
 767
 768         if (yhigh < (si->dm.timing.v_display - 16))
 769         {
 770                 /* we have vertical lines below old and new cursorposition to spare. So we
 771                  * update the cursor postion 'mid-screen', but below that area. */
 772                 while (((uint16)(ENG_REG32(RG32_RASTER2) & 0x000007ff)) < (yhigh + 16))
 773                 {
 774                         snooze(10);
 775                 }
 776         }
 777         else
 778         {
 779                 /* no room to spare, just wait for retrace (is relatively slow) */
 780                 while ((ENG_REG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display)
 781                 {
 782                         /* don't snooze much longer or retrace might get missed! */
 783                         snooze(10);
 784                 }
 785         }
 786
 787         /* update cursorposition */
 788         DAC2W(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16)));
 789
 790         return B_OK;
 791 }