src/add-ons/kernel/drivers/audio/hda/driver.h

   1 /*
   2  * Copyright 2007-2012, Haiku, Inc. All Rights Reserved.
   3  * Distributed under the terms of the MIT License.
   4  *
   5  * Authors:
   6  *              Ithamar Adema, ithamar AT unet DOT nl
   7  *              Axel Dörfler, axeld@pinc-software.de
   8  */
   9 #ifndef _HDA_H_
  10 #define _HDA_H_
  11
  12 #include <KernelExport.h>
  13 #include <Drivers.h>
  14 #include <PCI.h>
  15 #include <PCI_x86.h>
  16
  17 #include <string.h>
  18 #include <stdlib.h>
  19
  20 #ifndef HAIKU_TARGET_PLATFORM_HAIKU
  21 #       define DEVFS_PATH_FORMAT        "audio/multi/hda/%lu"
  22 #       include <multi_audio.h>
  23 #else
  24 #       define DEVFS_PATH_FORMAT        "audio/hmulti/hda/%lu"
  25 #       include <hmulti_audio.h>
  26 #endif
  27
  28 #include "hda_controller_defs.h"
  29 #include "hda_codec_defs.h"
  30
  31 #define MAX_CARDS                               4
  32
  33 /* values for the class_sub field for class_base = 0x04 (multimedia device) */
  34 #ifndef __HAIKU__
  35 #       define PCI_hd_audio                     3
  36 #endif
  37
  38 #define HDA_MAX_AUDIO_GROUPS    15
  39 #define HDA_MAX_CODECS                  15
  40 #define HDA_MAX_STREAMS                 16
  41 #define MAX_CODEC_RESPONSES             16
  42 #define MAX_CODEC_UNSOL_RESPONSES 16
  43 #define MAX_INPUTS                              32
  44 #define MAX_IO_WIDGETS                  8
  45 #define MAX_ASSOCIATIONS                16
  46 #define MAX_ASSOCIATION_PINS    16
  47
  48 #define STREAM_MAX_BUFFERS      10
  49 #define STREAM_MIN_BUFFERS      2
  50
  51
  52 enum {
  53         STREAM_PLAYBACK,
  54         STREAM_RECORD
  55 };
  56
  57 struct hda_codec;
  58 struct hda_stream;
  59 struct hda_multi;
  60
  61 /*!     This structure describes a single HDA compliant
  62         controller. It contains a list of available streams
  63         for use by the codecs contained, and the messaging queue
  64         (verb/response) buffers for communication.
  65 */
  66 struct hda_controller {
  67         struct pci_info pci_info;
  68         int32                   opened;
  69         const char*             devfs_path;
  70
  71         area_id                 regs_area;
  72         vuint8*                 regs;
  73         uint32                  irq;
  74         bool                    msi;
  75         bool                    dma_snooping;
  76
  77         uint16                  codec_status;
  78         uint32                  num_input_streams;
  79         uint32                  num_output_streams;
  80         uint32                  num_bidir_streams;
  81
  82         uint32                  corb_length;
  83         uint32                  rirb_length;
  84         uint32                  rirb_read_pos;
  85         uint32                  corb_write_pos;
  86         area_id                 corb_rirb_pos_area;
  87         corb_t*                 corb;
  88         rirb_t*                 rirb;
  89         uint32*                 stream_positions;
  90
  91         hda_codec*              codecs[HDA_MAX_CODECS + 1];
  92         hda_codec*              active_codec;
  93         uint32                  num_codecs;
  94
  95         hda_stream*             streams[HDA_MAX_STREAMS];
  96         sem_id                  buffer_ready_sem;
  97
  98         uint8 Read8(uint32 reg)
  99         {
 100                 return *(regs + reg);
 101         }
 102
 103         uint16 Read16(uint32 reg)
 104         {
 105                 return *(vuint16*)(regs + reg);
 106         }
 107
 108         uint32 Read32(uint32 reg)
 109         {
 110                 return *(vuint32*)(regs + reg);
 111         }
 112
 113         void Write8(uint32 reg, uint8 value)
 114         {
 115                 *(regs + reg) = value;
 116         }
 117
 118         void Write16(uint32 reg, uint16 value)
 119         {
 120                 *(vuint16*)(regs + reg) = value;
 121         }
 122
 123         void Write32(uint32 reg, uint32 value)
 124         {
 125                 *(vuint32*)(regs + reg) = value;
 126         }
 127
 128         void ReadModifyWrite8(uint32 reg, uint8 mask, uint8 value)
 129         {
 130                 uint8 temp = Read8(reg);
 131                 temp &= ~mask;
 132                 temp |= value;
 133                 Write8(reg, temp);
 134         }
 135
 136         void ReadModifyWrite16(uint32 reg, uint16 mask, uint16 value)
 137         {
 138                 uint16 temp = Read16(reg);
 139                 temp &= ~mask;
 140                 temp |= value;
 141                 Write16(reg, temp);
 142         }
 143
 144         void ReadModifyWrite32(uint32 reg, uint32 mask, uint32 value)
 145         {
 146                 uint32 temp = Read32(reg);
 147                 temp &= ~mask;
 148                 temp |= value;
 149                 Write32(reg, temp);
 150         }
 151 };
 152
 153 /*!     This structure describes a single stream of audio data,
 154         which is can have multiple channels (for stereo or better).
 155 */
 156 struct hda_stream {
 157         uint32          id;                                     /* HDA controller stream # */
 158         uint32          offset;                         /* HDA I/O/B descriptor offset */
 159         bool            running;
 160         spinlock        lock;                           /* Write lock */
 161         uint32          type;
 162
 163         hda_controller* controller;
 164
 165         uint32          pin_widget;                     /* PIN Widget ID */
 166         uint32          io_widgets[MAX_IO_WIDGETS];     /* Input/Output Converter Widget ID */
 167         uint32          num_io_widgets;
 168
 169         uint32          sample_rate;
 170         uint32          sample_format;
 171
 172         uint32          num_buffers;
 173         uint32          num_channels;
 174         uint32          buffer_length;  /* size of buffer in samples */
 175         uint32          buffer_size;    /* actual (aligned) size of buffer in bytes */
 176         uint32          sample_size;
 177         uint8*          buffers[STREAM_MAX_BUFFERS];
 178                                         /* Virtual addresses for buffer */
 179         phys_addr_t     physical_buffers[STREAM_MAX_BUFFERS];
 180                                         /* Physical addresses for buffer */
 181
 182         volatile bigtime_t      real_time;
 183         volatile uint64         frames_count;
 184         uint32                          last_link_frame_position;
 185         volatile int32          buffer_cycle;
 186
 187         uint32          rate, bps;                      /* Samplerate & bits per sample */
 188
 189         area_id         buffer_area;
 190         area_id         buffer_descriptors_area;
 191         phys_addr_t     physical_buffer_descriptors;    /* BDL physical address */
 192
 193         int32           incorrect_position_count;
 194         bool            use_dma_position;
 195
 196         uint8 Read8(uint32 reg)
 197         {
 198                 return controller->Read8(HDAC_STREAM_BASE + offset + reg);
 199         }
 200
 201         uint16 Read16(uint32 reg)
 202         {
 203                 return controller->Read16(HDAC_STREAM_BASE + offset + reg);
 204         }
 205
 206         uint32 Read32(uint32 reg)
 207         {
 208                 return controller->Read32(HDAC_STREAM_BASE + offset + reg);
 209         }
 210
 211         void Write8(uint32 reg, uint8 value)
 212         {
 213                 *(controller->regs + HDAC_STREAM_BASE + offset + reg) = value;
 214         }
 215
 216         void Write16(uint32 reg, uint16 value)
 217         {
 218                 *(vuint16*)(controller->regs + HDAC_STREAM_BASE + offset + reg) = value;
 219         }
 220
 221         void Write32(uint32 reg, uint32 value)
 222         {
 223                 *(vuint32*)(controller->regs + HDAC_STREAM_BASE + offset + reg) = value;
 224         }
 225 };
 226
 227 struct hda_widget {
 228         uint32                  node_id;
 229
 230         uint32                  num_inputs;
 231         int32                   active_input;
 232         uint32                  inputs[MAX_INPUTS];
 233         uint32                  flags;
 234
 235         hda_widget_type type;
 236         uint32                  pm;
 237
 238         struct {
 239                 uint32          audio;
 240                 uint32          output_amplifier;
 241                 uint32          input_amplifier;
 242         } capabilities;
 243
 244         union {
 245                 struct {
 246                         uint32  formats;
 247                         uint32  rates;
 248                 } io;
 249                 struct {
 250                 } mixer;
 251                 struct {
 252                         uint32  capabilities;
 253                         uint32  config;
 254                 } pin;
 255         } d;
 256 };
 257
 258 struct hda_association {
 259         uint32  index;
 260         bool    enabled;
 261         uint32  pin_count;
 262         uint32  pins[MAX_ASSOCIATION_PINS];
 263 };
 264
 265 #define WIDGET_FLAG_OUTPUT_PATH 0x01
 266 #define WIDGET_FLAG_INPUT_PATH  0x02
 267 #define WIDGET_FLAG_WIDGET_PATH 0x04
 268
 269 /*!     This structure describes a single Audio Function Group. An AFG
 270         is a group of audio widgets which can be used to configure multiple
 271         streams of audio either from the HDA Link to an output device (= playback)
 272         or from an input device to the HDA link (= recording).
 273 */
 274 struct hda_audio_group {
 275         hda_codec*              codec;
 276         hda_widget              widget;
 277
 278         /* Multi Audio API data */
 279         hda_stream*             playback_stream;
 280         hda_stream*             record_stream;
 281
 282         uint32                  widget_start;
 283         uint32                  widget_count;
 284
 285         uint32                  association_count;
 286         uint32                  gpio;
 287
 288         hda_widget*             widgets;
 289         hda_association         associations[MAX_ASSOCIATIONS];
 290
 291         hda_multi*              multi;
 292 };
 293
 294 /*!     This structure describes a single codec module in the
 295         HDA compliant device. This is a discrete component, which
 296         can contain both Audio Function Groups, Modem Function Groups,
 297         and other customized (vendor specific) Function Groups.
 298
 299         NOTE: ATM, only Audio Function Groups are supported.
 300 */
 301 struct hda_codec {
 302         uint16          vendor_id;
 303         uint16          product_id;
 304         uint8           major;
 305         uint8           minor;
 306         uint8           revision;
 307         uint8           stepping;
 308         uint8           addr;
 309
 310         uint32          quirks;
 311
 312         sem_id          response_sem;
 313         uint32          responses[MAX_CODEC_RESPONSES];
 314         uint32          response_count;
 315
 316         sem_id          unsol_response_sem;
 317         thread_id       unsol_response_thread;
 318         uint32          unsol_responses[MAX_CODEC_UNSOL_RESPONSES];
 319         uint32          unsol_response_read, unsol_response_write;
 320
 321         hda_audio_group* audio_groups[HDA_MAX_AUDIO_GROUPS];
 322         uint32          num_audio_groups;
 323
 324         struct hda_controller* controller;
 325 };
 326
 327
 328 #define MULTI_CONTROL_FIRSTID   1024
 329 #define MULTI_CONTROL_MASTERID  0
 330 #define MULTI_MAX_CONTROLS 128
 331 #define MULTI_MAX_CHANNELS 128
 332
 333 struct hda_multi_mixer_control {
 334         hda_multi       *multi;
 335         int32   nid;
 336         int32 type;
 337         bool input;
 338         uint32 mute;
 339         uint32 gain;
 340         uint32 capabilities;
 341         int32 index;
 342         multi_mix_control       mix_control;
 343 };
 344
 345
 346 struct hda_multi {
 347         hda_audio_group *group;
 348         hda_multi_mixer_control controls[MULTI_MAX_CONTROLS];
 349         uint32 control_count;
 350
 351         multi_channel_info chans[MULTI_MAX_CHANNELS];
 352         uint32 output_channel_count;
 353         uint32 input_channel_count;
 354         uint32 output_bus_channel_count;
 355         uint32 input_bus_channel_count;
 356         uint32 aux_bus_channel_count;
 357 };
 358
 359
 360 /* driver.c */
 361 extern device_hooks gDriverHooks;
 362 extern pci_module_info* gPci;
 363 extern pci_x86_module_info* gPCIx86Module;
 364 extern hda_controller gCards[MAX_CARDS];
 365 extern uint32 gNumCards;
 366
 367 /* hda_codec.c */
 368 const char* get_widget_location(uint32 location);
 369 hda_widget* hda_audio_group_get_widget(hda_audio_group* audioGroup, uint32 nodeID);
 370
 371 status_t hda_audio_group_get_widgets(hda_audio_group* audioGroup,
 372         hda_stream* stream);
 373 hda_codec* hda_codec_new(hda_controller* controller, uint32 cad);
 374 void hda_codec_delete(hda_codec* codec);
 375
 376 /* hda_multi_audio.c */
 377 status_t multi_audio_control(void* cookie, uint32 op, void* arg, size_t length);
 378
 379 /* hda_controller.c: Basic controller support */
 380 status_t hda_hw_init(hda_controller* controller);
 381 void hda_hw_stop(hda_controller* controller);
 382 void hda_hw_uninit(hda_controller* controller);
 383 status_t hda_send_verbs(hda_codec* codec, corb_t* verbs, uint32* responses,
 384         uint32 count);
 385 status_t hda_verb_write(hda_codec* codec, uint32 nid, uint32 vid, uint16 payload);
 386 status_t hda_verb_read(hda_codec* codec, uint32 nid, uint32 vid, uint32 *response);
 387
 388 /* hda_controller.c: Stream support */
 389 hda_stream* hda_stream_new(hda_audio_group* audioGroup, int type);
 390 void hda_stream_delete(hda_stream* stream);
 391 status_t hda_stream_setup_buffers(hda_audio_group* audioGroup,
 392         hda_stream* stream, const char* desc);
 393 status_t hda_stream_start(hda_controller* controller, hda_stream* stream);
 394 status_t hda_stream_stop(hda_controller* controller, hda_stream* stream);
 395
 396 #endif  /* _HDA_H_ */