src/add-ons/kernel/drivers/dvb/cx23882/cx23882_regs.h

   1 /*
   2  * Copyright (c) 2004-2007 Marcus Overhagen <marcus@overhagen.de>
   3  *
   4  * Permission is hereby granted, free of charge, to any person
   5  * obtaining a copy of this software and associated documentation
   6  * files (the "Software"), to deal in the Software without restriction,
   7  * including without limitation the rights to use, copy, modify,
   8  * merge, publish, distribute, sublicense, and/or sell copies of
   9  * the Software, and to permit persons to whom the Software is
  10  * furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be
  13  * included in all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  17  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  18  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  19  * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  20  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #ifndef __CX23882_REGS_H
  26 #define __CX23882_REGS_H
  27
  28 #define PCI_PCICMD_IOS                  0x01
  29 #define PCI_PCICMD_MSE                  0x02
  30 #define PCI_PCICMD_BME                  0x04
  31
  32 #define PCI_VENDOR_SIS                  0x1039
  33 #define PCI_VENDOR_VIA                  0x1106
  34
  35 #define REG_PDMA_STHRSH                 0x200000
  36 #define REG_PDMA_DTHRSH                 0x200010
  37
  38 #define PDMA_ISBTHRSH_1                 0x0100
  39 #define PDMA_ISBTHRSH_2                 0x0200
  40 #define PDMA_ISBTHRSH_3                 0x0300
  41 #define PDMA_ISBTHRSH_4                 0x0400
  42 #define PDMA_ISBTHRSH_5                 0x0500
  43 #define PDMA_ISBTHRSH_6                 0x0600
  44 #define PDMA_ISBTHRSH_7                 0x0700
  45
  46 #define PDMA_PCITHRSH_1                 0x0001
  47 #define PDMA_PCITHRSH_2                 0x0002
  48 #define PDMA_PCITHRSH_3                 0x0003
  49 #define PDMA_PCITHRSH_4                 0x0004
  50 #define PDMA_PCITHRSH_5                 0x0005
  51 #define PDMA_PCITHRSH_6                 0x0006
  52 #define PDMA_PCITHRSH_7                 0x0007
  53
  54 #define REG_DEV_CNTRL2                  0x200034
  55
  56 #define DEV_CNTRL2_RUN_RISC             0x20
  57
  58 #define REG_PCI_INT_MSK                 0x200040
  59 #define REG_PCI_INT_STAT                0x200044
  60 #define REG_PCI_INT_MSTAT               0x200048
  61
  62 #define PCI_INT_STAT_VID_INT    0x01
  63 #define PCI_INT_STAT_AUD_INT    0x02
  64 #define PCI_INT_STAT_TS_INT             0x04
  65 #define PCI_INT_STAT_VIP_INT    0x08
  66 #define PCI_INT_STAT_HST_INT    0x10
  67
  68 #define REG_VID_INT_MSK                 0x200050
  69 #define REG_VID_INT_STAT                0x200054
  70 #define REG_VID_INT_MSTAT               0x200058
  71
  72 #define REG_AUD_INT_MSK                 0x200060
  73 #define REG_AUD_INT_STAT                0x200064
  74 #define REG_AUD_INT_MSTAT               0x200068
  75
  76 #define REG_TS_INT_MSK                  0x200070
  77 #define REG_TS_INT_STAT                 0x200074
  78 #define REG_TS_INT_MSTAT                0x200078
  79
  80 #define TS_INT_STAT_TS_RISC1    0x000001
  81 #define TS_INT_STAT_TS_RISC2    0x000010
  82 #define TS_INT_STAT_OPC_ERR             0x010000
  83
  84 #define REG_VIP_INT_MSK                 0x200080
  85 #define REG_VIP_INT_STAT                0x200084
  86 #define REG_VIP_INT_MSTAT               0x200088
  87
  88 #define REG_HST_INT_MSK                 0x200090
  89 #define REG_HST_INT_STAT                0x200094
  90 #define REG_HST_INT_MSTAT               0x200098
  91
  92 #define REG_F2_DEV_CNTRL1               0x2f0240
  93 #define F2_DEV_CNTRL1_EN_VSFX   0x8
  94
  95 #define REG_DMA28_PTR1                  0x30009c
  96 #define REG_DMA28_PTR2                  0x3000dc
  97 #define REG_DMA28_CNT1                  0x30011c
  98 #define REG_DMA28_CNT2                  0x30015c
  99
 100 #define REG_TS_GP_CNT_CNTRL             0x33c030
 101 #define REG_TS_DMA_CNTRL                0x33c040
 102
 103 #define TS_DMA_CNTRL_TS_FIFO_EN 0x01
 104 #define TS_DMA_CNTRL_TS_RISC_EN 0x10
 105
 106 #define REG_TS_LNGTH                    0x33c048
 107 #define REG_HW_SOP_CONTROL              0x33c04c
 108 #define REG_TS_GEN_CONTROL              0x33c050
 109
 110 #define TS_GEN_CONTROL_IPB_SMODE 0x08
 111
 112 #define REG_TS_BD_PKT_STATUS    0x33c054
 113 #define REG_TS_SOP_STATUS               0x33c058
 114
 115 #define REG_VIP_STREAM_EN               0x34c040
 116
 117 // these 3 are not in my spec, taken form Linux
 118 #define REG_DMA_RISC_INT_MSK    0x35C060
 119 #define REG_DMA_RISC_INT_STAT   0x35C064
 120 #define REG_DMA_RISC_INT_MSTAT  0x35C068
 121
 122 #define REG_I2C_CONTROL                 0x368000
 123 #define I2C_SDA                                 0x01
 124 #define I2C_SCL                                 0x02
 125 #define I2C_HW_MODE                             0x80
 126
 127 #define REG_HST_STREAM_EN               0x38c040
 128
 129
 130 // RISC instructions
 131 #define RISC_RESYNC                             0x80008000
 132 #define RISC_WRITE                              0x10000000
 133 #define RISC_SKIP                               0x20000000
 134 #define RISC_JUMP                               0x70000000
 135 #define RISC_WRITECR                    0xd0000000
 136
 137 #define RISC_IMM                                0x00000001
 138 #define RISC_SOL                                0x08000000
 139 #define RISC_EOL                                0x04000000
 140 #define RISC_IRQ2                               0x02000000
 141 #define RISC_IRQ1                               0x01000000
 142 #define RISC_SRP                                0x00000001
 143
 144 #endif