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BPicture: Fix archive constructor.
[haiku.git] / src / add-ons / kernel / drivers / graphics / nvidia / driver.c
blob9420b76c438814aa211b8db34418605e3baae868
1 /*
2 Copyright 1999, Be Incorporated. All Rights Reserved.
3 This file may be used under the terms of the Be Sample Code License.
4
5 Other authors:
6 Mark Watson;
7 Rudolf Cornelissen 3/2002-6/2010.
8 */
9
10
11 #include "AGP.h"
12 #include "DriverInterface.h"
13 #include "nv_macros.h"
14
15 #include <graphic_driver.h>
16 #include <KernelExport.h>
17 #include <ISA.h>
18 #include <PCI.h>
19 #include <OS.h>
20 #include <directories.h>
21 #include <driver_settings.h>
22
23 #include <stdlib.h>
24 #include <stdio.h>
25 #include <string.h>
26
27 #define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s))
28 #define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v))
29
30 #define MAX_DEVICES 8
31
32 #ifndef __HAIKU__
33 # undef B_USER_CLONEABLE_AREA
34 # define B_USER_CLONEABLE_AREA 0
35 #endif
36
37 /* Tell the kernel what revision of the driver API we support */
38 int32 api_version = B_CUR_DRIVER_API_VERSION;
39
40 /* these structures are private to the kernel driver */
41 typedef struct device_info device_info;
42
43 typedef struct {
44 timer te; /* timer entry for add_timer() */
45 device_info *di; /* pointer to the owning device */
46 bigtime_t when_target; /* when we're supposed to wake up */
47 } timer_info;
48
49 struct device_info {
50 uint32 is_open; /* a count of how many times the devices has been opened */
51 area_id shared_area; /* the area shared between the driver and all of the accelerants */
52 shared_info *si; /* a pointer to the shared area, for convenience */
53 vuint32 *regs; /* kernel's pointer to memory mapped registers */
54 pci_info pcii; /* a convenience copy of the pci info for this device */
55 char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */
56 };
57
58 typedef struct {
59 uint32 count; /* number of devices actually found */
60 benaphore kernel; /* for serializing opens/closes */
61 char *device_names[MAX_DEVICES+1]; /* device name pointer storage */
62 device_info di[MAX_DEVICES]; /* device specific stuff */
63 } DeviceData;
64
65 /* prototypes for our private functions */
66 static status_t open_hook(const char* name, uint32 flags, void** cookie);
67 static status_t close_hook(void* dev);
68 static status_t free_hook(void* dev);
69 static status_t read_hook(void* dev, off_t pos, void* buf, size_t* len);
70 static status_t write_hook(void* dev, off_t pos, const void* buf, size_t* len);
71 static status_t control_hook(void* dev, uint32 msg, void *buf, size_t len);
72 static status_t map_device(device_info *di);
73 static void unmap_device(device_info *di);
74 static void probe_devices(void);
75 static int32 nv_interrupt(void *data);
76
77 static DeviceData *pd;
78 static isa_module_info *isa_bus = NULL;
79 static pci_module_info *pci_bus = NULL;
80 static agp_gart_module_info *agp_bus = NULL;
81 static device_hooks graphics_device_hooks = {
82 open_hook,
83 close_hook,
84 free_hook,
85 control_hook,
86 read_hook,
87 write_hook,
88 NULL,
89 NULL,
90 NULL,
91 NULL
92 };
93
94 #define VENDOR_ID_NVIDIA 0x10de /* Nvidia */
95 #define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */
96 #define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */
97 #define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */
98
99 static uint16 nvidia_device_list[] = {
100 0x0020, /* Nvidia TNT1 */
101 0x0028, /* Nvidia TNT2 (pro) */
102 0x0029, /* Nvidia TNT2 Ultra */
103 0x002a, /* Nvidia TNT2 */
104 0x002b, /* Nvidia TNT2 */
105 0x002c, /* Nvidia Vanta (Lt) */
106 0x002d, /* Nvidia TNT2-M64 (Pro) */
107 0x002e, /* Nvidia NV06 Vanta */
108 0x002f, /* Nvidia NV06 Vanta */
109 0x0040, /* Nvidia Geforce FX 6800 Ultra */
110 0x0041, /* Nvidia Geforce FX 6800 */
111 0x0042, /* Nvidia Geforce FX 6800LE */
112 0x0043, /* Nvidia Geforce 6800 XE */
113 0x0045, /* Nvidia Geforce FX 6800 GT */
114 0x0046, /* Nvidia Geforce FX 6800 GT */
115 0x0047, /* Nvidia Geforce 6800 GS */
116 0x0048, /* Nvidia Geforce FX 6800 XT */
117 0x0049, /* Nvidia unknown FX */
118 0x004d, /* Nvidia Quadro FX 4400 */
119 0x004e, /* Nvidia Quadro FX 4000 */
120 0x0091, /* Nvidia Geforce 7800 GTX PCIe */
121 0x0092, /* Nvidia Geforce 7800 GT PCIe */
122 0x0098, /* Nvidia Geforce 7800 Go PCIe */
123 0x0099, /* Nvidia Geforce 7800 GTX Go PCIe */
124 0x009d, /* Nvidia Quadro FX 4500 */
125 0x00a0, /* Nvidia Aladdin TNT2 */
126 0x00c0, /* Nvidia Geforce 6800 GS */
127 0x00c1, /* Nvidia Geforce FX 6800 */
128 0x00c2, /* Nvidia Geforce FX 6800LE */
129 0x00c3, /* Nvidia Geforce FX 6800 XT */
130 0x00c8, /* Nvidia Geforce FX 6800 Go */
131 0x00c9, /* Nvidia Geforce FX 6800 Ultra Go */
132 0x00cc, /* Nvidia Quadro FX 1400 Go */
133 0x00cd, /* Nvidia Quadro FX 3450/4000 SDI */
134 0x00ce, /* Nvidia Quadro FX 1400 */
135 0x00f0, /* Nvidia Geforce FX 6800 (Ultra) AGP(?) */
136 0x00f1, /* Nvidia Geforce FX 6600 GT AGP */
137 0x00f2, /* Nvidia Geforce FX 6600 AGP */
138 0x00f3, /* Nvidia Geforce 6200 */
139 0x00f4, /* Nvidia Geforce 6600 LE */
140 0x00f5, /* Nvidia Geforce FX 7800 GS AGP */
141 0x00f6, /* Nvidia Geforce 6800 GS */
142 0x00f8, /* Nvidia Quadro FX 3400/4400 PCIe */
143 0x00f9, /* Nvidia Geforce PCX 6800 PCIe */
144 0x00fa, /* Nvidia Geforce PCX 5750 PCIe */
145 0x00fb, /* Nvidia Geforce PCX 5900 PCIe */
146 0x00fc, /* Nvidia Geforce PCX 5300 PCIe */
147 0x00fd, /* Nvidia Quadro PCX PCIe */
148 0x00fe, /* Nvidia Quadro FX 1300 PCIe(?) */
149 0x00ff, /* Nvidia Geforce PCX 4300 PCIe */
150 0x0100, /* Nvidia Geforce256 SDR */
151 0x0101, /* Nvidia Geforce256 DDR */
152 0x0102, /* Nvidia Geforce256 Ultra */
153 0x0103, /* Nvidia Quadro */
154 0x0110, /* Nvidia Geforce2 MX/MX400 */
155 0x0111, /* Nvidia Geforce2 MX100/MX200 DDR */
156 0x0112, /* Nvidia Geforce2 Go */
157 0x0113, /* Nvidia Quadro2 MXR/EX/Go */
158 0x0140, /* Nvidia Geforce FX 6600 GT */
159 0x0141, /* Nvidia Geforce FX 6600 */
160 0x0142, /* Nvidia Geforce FX 6600LE */
161 0x0143, /* Nvidia Geforce 6600 VE */
162 0x0144, /* Nvidia Geforce FX 6600 Go */
163 0x0145, /* Nvidia Geforce FX 6610 XL */
164 0x0146, /* Nvidia Geforce FX 6600 TE Go / 6200 TE Go */
165 0x0147, /* Nvidia Geforce FX 6700 XL */
166 0x0148, /* Nvidia Geforce FX 6600 Go */
167 0x0149, /* Nvidia Geforce FX 6600 GT Go */
168 0x014b, /* Nvidia unknown FX */
169 0x014c, /* Nvidia Quadro FX 540 MXM */
170 0x014d, /* Nvidia unknown FX */
171 0x014e, /* Nvidia Quadro FX 540 */
172 0x014f, /* Nvidia Geforce 6200 PCIe (128Mb) */
173 0x0150, /* Nvidia Geforce2 GTS/Pro */
174 0x0151, /* Nvidia Geforce2 Ti DDR */
175 0x0152, /* Nvidia Geforce2 Ultra */
176 0x0153, /* Nvidia Quadro2 Pro */
177 0x0160, /* Nvidia Geforce 6500 Go */
178 0x0161, /* Nvidia Geforce 6200 TurboCache */
179 0x0162, /* Nvidia Geforce 6200SE TurboCache */
180 0x0163, /* Nvidia Geforce 6200LE */
181 0x0164, /* Nvidia Geforce FX 6200 Go */
182 0x0165, /* Nvidia Quadro FX NVS 285 */
183 0x0166, /* Nvidia Geforce 6400 Go */
184 0x0167, /* Nvidia Geforce 6200 Go */
185 0x0168, /* Nvidia Geforce 6400 Go */
186 0x0169, /* Nvidia Geforce 6250 Go */
187 0x016a, /* Nvidia Geforce 7100 GS */
188 0x016b, /* Nvidia unknown FX Go */
189 0x016c, /* Nvidia unknown FX Go */
190 0x016d, /* Nvidia unknown FX Go */
191 0x016e, /* Nvidia unknown FX */
192 0x0170, /* Nvidia Geforce4 MX 460 */
193 0x0171, /* Nvidia Geforce4 MX 440 */
194 0x0172, /* Nvidia Geforce4 MX 420 */
195 0x0173, /* Nvidia Geforce4 MX 440SE */
196 0x0174, /* Nvidia Geforce4 440 Go */
197 0x0175, /* Nvidia Geforce4 420 Go */
198 0x0176, /* Nvidia Geforce4 420 Go 32M */
199 0x0177, /* Nvidia Geforce4 460 Go */
200 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */
201 0x0179, /* Nvidia Geforce4 440 Go 64M (PPC: Geforce4 MX) */
202 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */
203 0x017c, /* Nvidia Quadro4 500 GoGL */
204 0x017d, /* Nvidia Geforce4 410 Go 16M */
205 0x0181, /* Nvidia Geforce4 MX 440 AGP8X */
206 0x0182, /* Nvidia Geforce4 MX 440SE AGP8X */
207 0x0183, /* Nvidia Geforce4 MX 420 AGP8X */
208 0x0185, /* Nvidia Geforce4 MX 4000 AGP8X */
209 0x0186, /* Nvidia Geforce4 448 Go */
210 0x0187, /* Nvidia Geforce4 488 Go */
211 0x0188, /* Nvidia Quadro4 580 XGL */
212 0x0189, /* Nvidia Geforce4 MX AGP8X (PPC) */
213 0x018a, /* Nvidia Quadro4 280 NVS AGP8X */
214 0x018b, /* Nvidia Quadro4 380 XGL */
215 0x018c, /* Nvidia Quadro4 NVS 50 PCI */
216 0x018d, /* Nvidia Geforce4 448 Go */
217 0x01a0, /* Nvidia Geforce2 Integrated GPU */
218 0x01d1, /* Nvidia Geforce 7300 LE */
219 0x01d3, /* Nvidia Geforce 7300 SE */
220 0x01d7, /* Nvidia Quadro NVS 110M/Geforce 7300 Go */
221 0x01d8, /* Nvidia Geforce 7400 GO */
222 0x01dd, /* Nvidia Geforce 7500 LE */
223 0x01df, /* Nvidia Geforce 7300 GS */
224 0x01f0, /* Nvidia Geforce4 MX Integrated GPU */
225 0x0200, /* Nvidia Geforce3 */
226 0x0201, /* Nvidia Geforce3 Ti 200 */
227 0x0202, /* Nvidia Geforce3 Ti 500 */
228 0x0203, /* Nvidia Quadro DCC */
229 0x0211, /* Nvidia Geforce FX 6800 */
230 0x0212, /* Nvidia Geforce FX 6800LE */
231 0x0215, /* Nvidia Geforce FX 6800 GT */
232 0x0218, /* Nvidia Geforce 6800 XT */
233 0x0220, /* Nvidia unknown FX */
234 0x0221, /* Nvidia Geforce 6200 AGP (256Mb - 128bit) */
235 0x0222, /* Nvidia unknown FX */
236 0x0228, /* Nvidia unknown FX Go */
237 0x0240, /* Nvidia Geforce 6150 (NFORCE4 Integr.GPU) */
238 0x0241, /* Nvidia Geforce 6150 LE (NFORCE4 Integr.GPU) */
239 0x0242, /* Nvidia Geforce 6100 (NFORCE4 Integr.GPU) */
240 0x0244, /* Nvidia Geforce Go 6150 (NFORCE4 Integr.GPU) */
241 0x0245, /* Nvidia Quadro NVS 210S / Geforce 6150LE */
242 0x0247, /* Nvidia Geforce 6100 Go (NFORCE4 Integr.GPU) */
243 0x0250, /* Nvidia Geforce4 Ti 4600 */
244 0x0251, /* Nvidia Geforce4 Ti 4400 */
245 0x0252, /* Nvidia Geforce4 Ti 4600 */
246 0x0253, /* Nvidia Geforce4 Ti 4200 */
247 0x0258, /* Nvidia Quadro4 900 XGL */
248 0x0259, /* Nvidia Quadro4 750 XGL */
249 0x025b, /* Nvidia Quadro4 700 XGL */
250 0x0280, /* Nvidia Geforce4 Ti 4800 AGP8X */
251 0x0281, /* Nvidia Geforce4 Ti 4200 AGP8X */
252 0x0282, /* Nvidia Geforce4 Ti 4800SE */
253 0x0286, /* Nvidia Geforce4 4200 Go */
254 0x0288, /* Nvidia Quadro4 980 XGL */
255 0x0289, /* Nvidia Quadro4 780 XGL */
256 0x028c, /* Nvidia Quadro4 700 GoGL */
257 0x0290, /* Nvidia Geforce 7900 GTX */
258 0x0291, /* Nvidia Geforce 7900 GT */
259 0x0292, /* Nvidia Geforce 7900 GS */
260 0x0293, /* Nvidia Geforce 7900 GX2 */
261 0x0294, /* Nvidia Geforce 7950 GX2 */
262 0x0295, /* Nvidia Geforce 7950 GT */
263 0x0298, /* Nvidia Geforce Go 7900 GS */
264 0x0299, /* Nvidia Geforce Go 7900 GTX */
265 0x029c, /* Nvidia Quadro FX 5500 */
266 0x029f, /* Nvidia Quadro FX 4500 X2 */
267 0x02a0, /* Nvidia Geforce3 Integrated GPU */
268 0x02e0, /* Nvidia Geforce 7600 GT */
269 0x02e1, /* Nvidia Geforce 7600 GS */
270 0x02e2, /* Nvidia Geforce 7300 GT */
271 0x0301, /* Nvidia Geforce FX 5800 Ultra */
272 0x0302, /* Nvidia Geforce FX 5800 */
273 0x0308, /* Nvidia Quadro FX 2000 */
274 0x0309, /* Nvidia Quadro FX 1000 */
275 0x0311, /* Nvidia Geforce FX 5600 Ultra */
276 0x0312, /* Nvidia Geforce FX 5600 */
277 0x0313, /* Nvidia unknown FX */
278 0x0314, /* Nvidia Geforce FX 5600XT */
279 0x0316, /* Nvidia unknown FX Go */
280 0x0317, /* Nvidia unknown FX Go */
281 0x031a, /* Nvidia Geforce FX 5600 Go */
282 0x031b, /* Nvidia Geforce FX 5650 Go */
283 0x031c, /* Nvidia Quadro FX 700 Go */
284 0x031d, /* Nvidia unknown FX Go */
285 0x031e, /* Nvidia unknown FX Go */
286 0x031f, /* Nvidia unknown FX Go */
287 0x0320, /* Nvidia Geforce FX 5200 */
288 0x0321, /* Nvidia Geforce FX 5200 Ultra */
289 0x0322, /* Nvidia Geforce FX 5200 */
290 0x0323, /* Nvidia Geforce FX 5200LE */
291 0x0324, /* Nvidia Geforce FX 5200 Go */
292 0x0325, /* Nvidia Geforce FX 5250 Go */
293 0x0326, /* Nvidia Geforce FX 5500 */
294 0x0327, /* Nvidia Geforce FX 5100 */
295 0x0328, /* Nvidia Geforce FX 5200 Go 32M/64M */
296 0x0329, /* Nvidia Geforce FX 5200 (PPC) */
297 0x032a, /* Nvidia Quadro NVS 280 PCI */
298 0x032b, /* Nvidia Quadro FX 500/600 PCI */
299 0x032c, /* Nvidia Geforce FX 5300 Go */
300 0x032d, /* Nvidia Geforce FX 5100 Go */
301 0x032e, /* Nvidia unknown FX Go */
302 0x032f, /* Nvidia unknown FX Go */
303 0x0330, /* Nvidia Geforce FX 5900 Ultra */
304 0x0331, /* Nvidia Geforce FX 5900 */
305 0x0332, /* Nvidia Geforce FX 5900 XT */
306 0x0333, /* Nvidia Geforce FX 5950 Ultra */
307 0x0334, /* Nvidia Geforce FX 5900 ZT */
308 0x0338, /* Nvidia Quadro FX 3000 */
309 0x033f, /* Nvidia Quadro FX 700 */
310 0x0341, /* Nvidia Geforce FX 5700 Ultra */
311 0x0342, /* Nvidia Geforce FX 5700 */
312 0x0343, /* Nvidia Geforce FX 5700LE */
313 0x0344, /* Nvidia Geforce FX 5700VE */
314 0x0345, /* Nvidia unknown FX */
315 0x0347, /* Nvidia Geforce FX 5700 Go */
316 0x0348, /* Nvidia Geforce FX 5700 Go */
317 0x0349, /* Nvidia unknown FX Go */
318 0x034b, /* Nvidia unknown FX Go */
319 0x034c, /* Nvidia Quadro FX 1000 Go */
320 0x034e, /* Nvidia Quadro FX 1100 */
321 0x034f, /* Nvidia unknown FX */
322 0x0391, /* Nvidia Geforce 7600 GT */
323 0x0392, /* Nvidia Geforce 7600 GS */
324 0x0393, /* Nvidia Geforce 7300 GT */
325 0x0394, /* Nvidia Geforce 7600 LE */
326 0x0398, /* Nvidia Geforce 7600 GO */
327 0x03d0, /* Nvidia Geforce 6100 nForce 430 */
328 0x03d1, /* Nvidia Geforce 6100 nForce 405 */
329 0x03d2, /* Nvidia Geforce 6100 nForce 400 */
330 0x03d5, /* Nvidia Geforce 6100 nForce 420 */
331 0x03d6, /* Nvidia Geforce 7025 / nForce 630a */
332 0x07e1, /* Nvidia Geforce 7100 / nForce 630i */
333 0
334 };
335
336 static uint16 elsa_device_list[] = {
337 0x0c60, /* Elsa Gladiac Geforce2 MX */
338 0
339 };
340
341 static uint16 nvstbsgs_device_list[] = {
342 0x0020, /* Nvidia STB/SGS-Thompson TNT1 */
343 0x0028, /* Nvidia STB/SGS-Thompson TNT2 (pro) */
344 0x0029, /* Nvidia STB/SGS-Thompson TNT2 Ultra */
345 0x002a, /* Nvidia STB/SGS-Thompson TNT2 */
346 0x002b, /* Nvidia STB/SGS-Thompson TNT2 */
347 0x002c, /* Nvidia STB/SGS-Thompson Vanta (Lt) */
348 0x002d, /* Nvidia STB/SGS-Thompson TNT2-M64 (Pro) */
349 0x002e, /* Nvidia STB/SGS-Thompson NV06 Vanta */
350 0x002f, /* Nvidia STB/SGS-Thompson NV06 Vanta */
351 0x00a0, /* Nvidia STB/SGS-Thompson Aladdin TNT2 */
352 0
353 };
354
355 static uint16 varisys_device_list[] = {
356 0x3503, /* Varisys Geforce4 MX440 */
357 0x3505, /* Varisys Geforce4 Ti 4200 */
358 0
359 };
360
361 static struct {
362 uint16 vendor;
363 uint16 *devices;
364 } SupportedDevices[] = {
365 {VENDOR_ID_NVIDIA, nvidia_device_list},
366 {VENDOR_ID_ELSA, elsa_device_list},
367 {VENDOR_ID_NVSTBSGS, nvstbsgs_device_list},
368 {VENDOR_ID_VARISYS, varisys_device_list},
369 {0x0000, NULL}
370 };
371
372 static nv_settings sSettings = { // see comments in nvidia.settings
373 /* for driver */
374 DRIVER_PREFIX ".accelerant",
375 "none", // primary
376 false, // dumprom
377 /* for accelerant */
378 0x00000000, // logmask
379 0, // memory
380 0, // tv_output
381 true, // usebios
382 true, // hardcursor
383 false, // switchhead
384 false, // force_pci
385 false, // unhide_fw
386 false, // pgm_panel
387 true, // dma_acc
388 false, // vga_on_tv
389 false, // force_sync
390 false, // force_ws
391 false, // block_acc
392 0, // gpu_clk
393 0, // ram_clk
394 };
395
396
397 static void
398 dumprom(void *rom, uint32 size, pci_info pcii)
399 {
400 int fd;
401 uint32 cnt;
402 char fname[64];
403
404 /* determine the romfile name: we need split-up per card in the system */
405 sprintf (fname, kUserDirectory "//" DRIVER_PREFIX "." DEVICE_FORMAT ".rom",
406 pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function);
407
408 fd = open (fname, O_WRONLY | O_CREAT, 0666);
409 if (fd < 0) return;
410
411 /* apparantly max. 32kb may be written at once;
412 * the ROM size is a multiple of that anyway. */
413 for (cnt = 0; (cnt < size); cnt += 32768)
414 write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768);
415 close (fd);
416 }
417
418
419 /*! return 1 if vblank interrupt has occured */
420 static int
421 caused_vbi_crtc1(vuint32 * regs)
422 {
423 return (NV_REG32(NV32_CRTC_INTS) & 0x00000001);
424 }
425
426
427 /*! clear the vblank interrupt */
428 static void
429 clear_vbi_crtc1(vuint32 * regs)
430 {
431 NV_REG32(NV32_CRTC_INTS) = 0x00000001;
432 }
433
434
435 static void
436 enable_vbi_crtc1(vuint32 * regs)
437 {
438 /* clear the vblank interrupt */
439 NV_REG32(NV32_CRTC_INTS) = 0x00000001;
440 /* enable nVidia interrupt source vblank */
441 NV_REG32(NV32_CRTC_INTE) |= 0x00000001;
442 /* enable nVidia interrupt system hardware (b0-1) */
443 NV_REG32(NV32_MAIN_INTE) = 0x00000001;
444 }
445
446
447 static void
448 disable_vbi_crtc1(vuint32 * regs)
449 {
450 /* disable nVidia interrupt source vblank */
451 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe;
452 /* clear the vblank interrupt */
453 NV_REG32(NV32_CRTC_INTS) = 0x00000001;
454 }
455
456
457 /*! return 1 if vblank interrupt has occured */
458 static int
459 caused_vbi_crtc2(vuint32 * regs)
460 {
461 return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001);
462 }
463
464
465 /*! clear the vblank interrupt */
466 static void
467 clear_vbi_crtc2(vuint32 * regs)
468 {
469 NV_REG32(NV32_CRTC2_INTS) = 0x00000001;
470 }
471
472
473 static void
474 enable_vbi_crtc2(vuint32 * regs)
475 {
476 /* clear the vblank interrupt */
477 NV_REG32(NV32_CRTC2_INTS) = 0x00000001;
478 /* enable nVidia interrupt source vblank */
479 NV_REG32(NV32_CRTC2_INTE) |= 0x00000001;
480 /* enable nVidia interrupt system hardware (b0-1) */
481 NV_REG32(NV32_MAIN_INTE) = 0x00000001;
482 }
483
484
485 static void
486 disable_vbi_crtc2(vuint32 * regs)
487 {
488 /* disable nVidia interrupt source vblank */
489 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe;
490 /* clear the vblank interrupt */
491 NV_REG32(NV32_CRTC2_INTS) = 0x00000001;
492 }
493
494
495 //fixme:
496 //dangerous code, on singlehead cards better not try accessing secondary head
497 //registers (card might react in unpredictable ways, though there's only a small
498 //chance we actually run into this).
499 //fix requires (some) card recognition code to be moved from accelerant to
500 //kerneldriver...
501 static void
502 disable_vbi_all(vuint32 * regs)
503 {
504 /* disable nVidia interrupt source vblank */
505 NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe;
506 /* clear the vblank interrupt */
507 NV_REG32(NV32_CRTC_INTS) = 0x00000001;
508
509 /* disable nVidia interrupt source vblank */
510 NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe;
511 /* clear the vblank interrupt */
512 NV_REG32(NV32_CRTC2_INTS) = 0x00000001;
513
514 /* disable nVidia interrupt system hardware (b0-1) */
515 NV_REG32(NV32_MAIN_INTE) = 0x00000000;
516 }
517
518
519 static status_t
520 map_device(device_info *di)
521 {
522 char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/
523 shared_info *si = di->si;
524 uint32 tmpUlong, tmpROMshadow;
525 pci_info *pcii = &(di->pcii);
526 system_info sysinfo;
527
528 /* variables for making copy of ROM */
529 uint8* rom_temp;
530 area_id rom_area = -1;
531
532 /* Nvidia cards have registers in [0] and framebuffer in [1] */
533 int registers = 0;
534 int frame_buffer = 1;
535
536 /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */
537 tmpUlong = get_pci(PCI_command, 2);
538 /* enable PCI access */
539 tmpUlong |= PCI_command_memory;
540 /* enable busmastering */
541 tmpUlong |= PCI_command_master;
542 /* disable ISA I/O access */
543 tmpUlong &= ~PCI_command_io;
544 set_pci(PCI_command, 2, tmpUlong);
545
546 /*work out which version of BeOS is running*/
547 get_system_info(&sysinfo);
548 if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/
549 {
550 si->use_clone_bugfix = 1;
551 }
552 else
553 {
554 si->use_clone_bugfix = 0;
555 }
556
557 /* work out a name for the register mapping */
558 sprintf(buffer, DEVICE_FORMAT " regs",
559 di->pcii.vendor_id, di->pcii.device_id,
560 di->pcii.bus, di->pcii.device, di->pcii.function);
561
562 /* get a virtual memory address for the registers*/
563 si->regs_area = map_physical_memory(
564 buffer,
565 /* WARNING: Nvidia needs to map regs as viewed from PCI space! */
566 di->pcii.u.h0.base_registers_pci[registers],
567 di->pcii.u.h0.base_register_sizes[registers],
568 B_ANY_KERNEL_ADDRESS,
569 B_USER_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0),
570 (void **)&(di->regs));
571 si->clone_bugfix_regs = (uint32 *) di->regs;
572
573 /* if mapping registers to vmem failed then pass on error */
574 if (si->regs_area < 0) return si->regs_area;
575
576 /* work out a name for the ROM mapping*/
577 sprintf(buffer, DEVICE_FORMAT " rom",
578 di->pcii.vendor_id, di->pcii.device_id,
579 di->pcii.bus, di->pcii.device, di->pcii.function);
580
581 /* preserve ROM shadowing setting, we need to restore the current state later on. */
582 /* warning:
583 * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise.
584 * NV18, NV28 and NV34 keep working.
585 * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes,
586 * however the actual ROM content (so the used part) is intact (confirmed). */
587 tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4);
588 /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */
589 set_pci(NVCFG_ROMSHADOW, 4, 0);
590
591 /* get ROM memory mapped base adress - this is defined in the PCI standard */
592 tmpUlong = get_pci(PCI_rom_base, 4);
593 //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not
594 //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA
595 //legacy space will get us into trouble if we aren't the primary graphics card!!
596 //(as legacy space always has the primary card's ROM 'mapped'!)
597 if (tmpUlong) {
598 /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */
599 tmpUlong |= 0x00000001;
600 set_pci(PCI_rom_base, 4, tmpUlong);
601
602 rom_area = map_physical_memory(
603 buffer,
604 di->pcii.u.h0.rom_base_pci,
605 di->pcii.u.h0.rom_size,
606 B_ANY_KERNEL_ADDRESS,
607 B_READ_AREA,
608 (void **)&(rom_temp)
609 );
610
611 /* check if we got the BIOS and signature (might fail on laptops..) */
612 if (rom_area >= 0) {
613 if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) {
614 /* apparantly no ROM is mapped here */
615 delete_area(rom_area);
616 rom_area = -1;
617 /* force using ISA legacy map as fall-back */
618 tmpUlong = 0x00000000;
619 }
620 } else {
621 /* mapping failed: force using ISA legacy map as fall-back */
622 tmpUlong = 0x00000000;
623 }
624 }
625
626 if (!tmpUlong) {
627 /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */
628 rom_area = map_physical_memory(buffer, 0x000c0000,
629 65536, B_ANY_KERNEL_ADDRESS, B_READ_AREA, (void **)&(rom_temp));
630 }
631
632 /* if mapping ROM to vmem failed then clean up and pass on error */
633 if (rom_area < 0) {
634 delete_area(si->regs_area);
635 si->regs_area = -1;
636 return rom_area;
637 }
638
639 /* dump ROM to file if selected in nvidia.settings
640 * (ROM always fits in 64Kb: checked TNT1 - FX5950) */
641 if (sSettings.dumprom)
642 dumprom(rom_temp, 65536, di->pcii);
643
644 /* make a copy of ROM for future reference */
645 memcpy(si->rom_mirror, rom_temp, 65536);
646
647 /* disable ROM decoding - this is defined in the PCI standard, and delete the area */
648 tmpUlong = get_pci(PCI_rom_base, 4);
649 tmpUlong &= 0xfffffffe;
650 set_pci(PCI_rom_base, 4, tmpUlong);
651 delete_area(rom_area);
652
653 /* restore original ROM shadowing setting to prevent trouble starting (some) cards */
654 set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow);
655
656 /* work out a name for the framebuffer mapping*/
657 sprintf(buffer, DEVICE_FORMAT " framebuffer",
658 di->pcii.vendor_id, di->pcii.device_id,
659 di->pcii.bus, di->pcii.device, di->pcii.function);
660
661 /* map the framebuffer into vmem, using Write Combining*/
662 si->fb_area = map_physical_memory(buffer,
663 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */
664 di->pcii.u.h0.base_registers_pci[frame_buffer],
665 di->pcii.u.h0.base_register_sizes[frame_buffer],
666 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
667 B_READ_AREA | B_WRITE_AREA,
668 &(si->framebuffer));
669
670 /*if failed with write combining try again without*/
671 if (si->fb_area < 0) {
672 si->fb_area = map_physical_memory(buffer,
673 /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */
674 di->pcii.u.h0.base_registers_pci[frame_buffer],
675 di->pcii.u.h0.base_register_sizes[frame_buffer],
676 B_ANY_KERNEL_BLOCK_ADDRESS,
677 B_READ_AREA | B_WRITE_AREA,
678 &(si->framebuffer));
679 }
680
681 /* if there was an error, delete our other areas and pass on error*/
682 if (si->fb_area < 0) {
683 delete_area(si->regs_area);
684 si->regs_area = -1;
685 return si->fb_area;
686 }
687
688 //fixme: retest for card coldstart and PCI/virt_mem mapping!!
689 /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */
690 si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer];
691
692 /* note the amount of memory mapped by the kerneldriver so we can make sure we
693 * don't attempt to adress more later on */
694 si->ps.memory_size = di->pcii.u.h0.base_register_sizes[frame_buffer];
695
696 // remember settings for use here and in accelerant
697 si->settings = sSettings;
698
699 /* in any case, return the result */
700 return si->fb_area;
701 }
702
703
704 static void
705 unmap_device(device_info *di)
706 {
707 shared_info *si = di->si;
708 uint32 tmpUlong;
709 pci_info *pcii = &(di->pcii);
710
711 /* disable memory mapped IO */
712 tmpUlong = get_pci(PCI_command, 4);
713 tmpUlong &= 0xfffffffc;
714 set_pci(PCI_command, 4, tmpUlong);
715 /* delete the areas */
716 if (si->regs_area >= 0)
717 delete_area(si->regs_area);
718 if (si->fb_area >= 0)
719 delete_area(si->fb_area);
720 si->regs_area = si->fb_area = -1;
721 si->framebuffer = NULL;
722 di->regs = NULL;
723 }
724
725
726 static void
727 probe_devices(void)
728 {
729 uint32 pci_index = 0;
730 uint32 count = 0;
731 device_info *di = pd->di;
732 char tmp_name[B_OS_NAME_LENGTH];
733
734 /* while there are more pci devices */
735 while (count < MAX_DEVICES
736 && (*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_OK) {
737 int vendor = 0;
738
739 /* if we match a supported vendor */
740 while (SupportedDevices[vendor].vendor) {
741 if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) {
742 uint16 *devices = SupportedDevices[vendor].devices;
743 /* while there are more supported devices */
744 while (*devices) {
745 /* if we match a supported device */
746 if (*devices == di->pcii.device_id ) {
747 /* publish the device name */
748 sprintf(tmp_name, DEVICE_FORMAT,
749 di->pcii.vendor_id, di->pcii.device_id,
750 di->pcii.bus, di->pcii.device, di->pcii.function);
751 /* tweak the exported name to show first in the alphabetically ordered /dev/
752 * hierarchy folder, so the system will use it as primary adaptor if requested
753 * via nvidia.settings. */
754 if (strcmp(tmp_name, sSettings.primary) == 0)
755 sprintf(tmp_name, "-%s", sSettings.primary);
756 /* add /dev/ hierarchy path */
757 sprintf(di->name, "graphics/%s", tmp_name);
758 /* remember the name */
759 pd->device_names[count] = di->name;
760 /* mark the driver as available for R/W open */
761 di->is_open = 0;
762 /* mark areas as not yet created */
763 di->shared_area = -1;
764 /* mark pointer to shared data as invalid */
765 di->si = NULL;
766 /* inc pointer to device info */
767 di++;
768 /* inc count */
769 count++;
770 /* break out of these while loops */
771 goto next_device;
772 }
773 /* next supported device */
774 devices++;
775 }
776 }
777 vendor++;
778 }
779 next_device:
780 /* next pci_info struct, please */
781 pci_index++;
782 }
783 /* propagate count */
784 pd->count = count;
785 /* terminate list of device names with a null pointer */
786 pd->device_names[pd->count] = NULL;
787 }
788
789
790 static uint32
791 thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si)
792 {
793 uint32 handled = B_HANDLED_INTERRUPT;
794 /* release the vblank semaphore */
795 if (si->vblank >= 0) {
796 int32 blocked;
797 if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) {
798 release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE);
799 handled = B_INVOKE_SCHEDULER;
800 }
801 }
802 return handled;
803 }
804
805
806 static int32
807 nv_interrupt(void *data)
808 {
809 int32 handled = B_UNHANDLED_INTERRUPT;
810 device_info *di = (device_info *)data;
811 shared_info *si = di->si;
812 int32 *flags = &(si->flags);
813 vuint32 *regs;
814
815 /* is someone already handling an interrupt for this device? */
816 if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0;
817
818 /* get regs */
819 regs = di->regs;
820
821 /* was it a VBI? */
822 /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */
823 if (si->ps.secondary_head) {
824 //fixme:
825 //rewrite once we use one driver instance 'per head' (instead of 'per card')
826 if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) {
827 /* clear the interrupt(s) */
828 clear_vbi_crtc1(regs);
829 clear_vbi_crtc2(regs);
830 /* release the semaphore */
831 handled = thread_interrupt_work(flags, regs, si);
832 }
833 } else {
834 if (caused_vbi_crtc1(regs)) {
835 /* clear the interrupt */
836 clear_vbi_crtc1(regs);
837 /* release the semaphore */
838 handled = thread_interrupt_work(flags, regs, si);
839 }
840 }
841
842 /* note that we're not in the handler any more */
843 atomic_and(flags, ~SKD_HANDLER_INSTALLED);
844
845 exit0:
846 return handled;
847 }
848
849
850 // #pragma mark - device hooks
851
852
853 static status_t
854 open_hook(const char* name, uint32 flags, void** cookie)
855 {
856 int32 index = 0;
857 device_info *di;
858 shared_info *si;
859 thread_id thid;
860 thread_info thinfo;
861 status_t result = B_OK;
862 char shared_name[B_OS_NAME_LENGTH];
863 physical_entry map[1];
864 size_t net_buf_size;
865 void *unaligned_dma_buffer;
866 uint32 mem_size;
867
868 /* find the device name in the list of devices */
869 /* we're never passed a name we didn't publish */
870 while (pd->device_names[index]
871 && (strcmp(name, pd->device_names[index]) != 0))
872 index++;
873
874 /* for convienience */
875 di = &(pd->di[index]);
876
877 /* make sure no one else has write access to the common data */
878 AQUIRE_BEN(pd->kernel);
879
880 /* if it's already open for writing */
881 if (di->is_open) {
882 /* mark it open another time */
883 goto mark_as_open;
884 }
885 /* create the shared_info area */
886 sprintf(shared_name, DEVICE_FORMAT " shared",
887 di->pcii.vendor_id, di->pcii.device_id,
888 di->pcii.bus, di->pcii.device, di->pcii.function);
889 /* create this area with NO user-space read or write permissions, to prevent accidental damage */
890 di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS,
891 ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK,
892 B_USER_CLONEABLE_AREA);
893 if (di->shared_area < 0) {
894 /* return the error */
895 result = di->shared_area;
896 goto done;
897 }
898
899 /* save a few dereferences */
900 si = di->si;
901
902 /* create the DMA command buffer area */
903 //fixme? for R4.5 a workaround for cloning would be needed!
904 /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */
905 net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1);
906 /* create the area that will hold the DMA command buffer */
907 si->unaligned_dma_area =
908 create_area("NV DMA cmd buffer",
909 (void **)&unaligned_dma_buffer,
910 B_ANY_KERNEL_ADDRESS,
911 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */
912 B_32_BIT_CONTIGUOUS, /* GPU always needs access */
913 B_USER_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA);
914 // TODO: Physical aligning can be done without waste using the
915 // private create_area_etc().
916 /* on error, abort */
917 if (si->unaligned_dma_area < 0)
918 {
919 /* free the already created shared_info area, and return the error */
920 result = si->unaligned_dma_area;
921 goto free_shared;
922 }
923 /* we (also) need the physical adress our DMA buffer is at, as this needs to be
924 * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC
925 * even on older CPU's. */
926 get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1);
927 si->dma_buffer_pci = (void*)
928 ((map[0].address + net_buf_size - 1) & ~(net_buf_size - 1));
929
930 /* map the net DMA command buffer into vmem, using Write Combining */
931 si->dma_area = map_physical_memory(
932 "NV aligned DMA cmd buffer", (addr_t)si->dma_buffer_pci, net_buf_size,
933 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC,
934 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer));
935 /* if failed with write combining try again without */
936 if (si->dma_area < 0) {
937 si->dma_area = map_physical_memory("NV aligned DMA cmd buffer",
938 (addr_t)si->dma_buffer_pci, net_buf_size,
939 B_ANY_KERNEL_BLOCK_ADDRESS,
940 B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer));
941 }
942 /* if there was an error, delete our other areas and pass on error*/
943 if (si->dma_area < 0)
944 {
945 /* free the already created areas, and return the error */
946 result = si->dma_area;
947 goto free_shared_and_uadma;
948 }
949
950 /* save the vendor and device IDs */
951 si->vendor_id = di->pcii.vendor_id;
952 si->device_id = di->pcii.device_id;
953 si->revision = di->pcii.revision;
954 si->bus = di->pcii.bus;
955 si->device = di->pcii.device;
956 si->function = di->pcii.function;
957
958 /* ensure that the accelerant's INIT_ACCELERANT function can be executed */
959 si->accelerant_in_use = false;
960 /* preset singlehead card to prevent early INT routine calls (once installed) to
961 * wrongly identify the INT request coming from us! */
962 si->ps.secondary_head = false;
963
964 /* map the device */
965 result = map_device(di);
966 if (result < 0) goto free_shared_and_alldma;
967
968 /* we will be returning OK status for sure now */
969 result = B_OK;
970
971 /* note the amount of system RAM the system BIOS assigned to the card if applicable:
972 * unified memory architecture (UMA) */
973 switch ((((uint32)(si->device_id)) << 16) | si->vendor_id)
974 {
975 case 0x01a010de: /* Nvidia Geforce2 Integrated GPU */
976 /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */
977 mem_size = 1024 * 1024 *
978 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1);
979 /* don't attempt to adress memory not mapped by the kerneldriver */
980 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size;
981 /* last 64kB RAM is used for the BIOS (or something else?) */
982 si->ps.memory_size -= (64 * 1024);
983 break;
984 case 0x01f010de: /* Nvidia Geforce4 MX Integrated GPU */
985 /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */
986 mem_size = 1024 * 1024 *
987 (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1);
988 /* don't attempt to adress memory not mapped by the kerneldriver */
989 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size;
990 /* last 64kB RAM is used for the BIOS (or something else?) */
991 si->ps.memory_size -= (64 * 1024);
992 break;
993 default:
994 /* all other cards have own RAM: the amount of which is determined in the
995 * accelerant. */
996 break;
997 }
998
999 /* disable and clear any pending interrupts */
1000 //fixme:
1001 //distinquish between crtc1/crtc2 once all heads get seperate driver instances!
1002 disable_vbi_all(di->regs);
1003
1004 /* preset we can't use INT related functions */
1005 si->ps.int_assigned = false;
1006
1007 /* create a semaphore for vertical blank management */
1008 si->vblank = create_sem(0, di->name);
1009 if (si->vblank < 0) goto mark_as_open;
1010
1011 /* change the owner of the semaphores to the opener's team */
1012 /* this is required because apps can't aquire kernel semaphores */
1013 thid = find_thread(NULL);
1014 get_thread_info(thid, &thinfo);
1015 set_sem_owner(si->vblank, thinfo.team);
1016
1017 /* If there is a valid interrupt line assigned then set up interrupts */
1018 if ((di->pcii.u.h0.interrupt_pin == 0x00) ||
1019 (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */
1020 (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */
1021 {
1022 /* delete the semaphore as it won't be used */
1023 delete_sem(si->vblank);
1024 si->vblank = -1;
1025 }
1026 else
1027 {
1028 /* otherwise install our interrupt handler */
1029 result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0);
1030 /* bail if we couldn't install the handler */
1031 if (result != B_OK)
1032 {
1033 /* delete the semaphore as it won't be used */
1034 delete_sem(si->vblank);
1035 si->vblank = -1;
1036 }
1037 else
1038 {
1039 /* inform accelerant(s) we can use INT related functions */
1040 si->ps.int_assigned = true;
1041 }
1042 }
1043
1044 mark_as_open:
1045 /* mark the device open */
1046 di->is_open++;
1047
1048 /* send the cookie to the opener */
1049 *cookie = di;
1050
1051 goto done;
1052
1053
1054 free_shared_and_alldma:
1055 /* clean up our aligned DMA area */
1056 delete_area(si->dma_area);
1057 si->dma_area = -1;
1058 si->dma_buffer = NULL;
1059
1060 free_shared_and_uadma:
1061 /* clean up our unaligned DMA area */
1062 delete_area(si->unaligned_dma_area);
1063 si->unaligned_dma_area = -1;
1064 si->dma_buffer_pci = NULL;
1065
1066 free_shared:
1067 /* clean up our shared area */
1068 delete_area(di->shared_area);
1069 di->shared_area = -1;
1070 di->si = NULL;
1071
1072 done:
1073 /* end of critical section */
1074 RELEASE_BEN(pd->kernel);
1075
1076 /* all done, return the status */
1077 return result;
1078 }
1079
1080
1081 static status_t
1082 read_hook(void* dev, off_t pos, void* buf, size_t* len)
1083 {
1084 *len = 0;
1085 return B_NOT_ALLOWED;
1086 }
1087
1088
1089 static status_t
1090 write_hook(void* dev, off_t pos, const void* buf, size_t* len)
1091 {
1092 *len = 0;
1093 return B_NOT_ALLOWED;
1094 }
1095
1096
1097 static status_t
1098 close_hook(void* dev)
1099 {
1100 /* we don't do anything on close: there might be dup'd fd */
1101 return B_NO_ERROR;
1102 }
1103
1104
1105 static status_t
1106 free_hook(void* dev)
1107 {
1108 device_info *di = (device_info *)dev;
1109 shared_info *si = di->si;
1110 vuint32 *regs = di->regs;
1111
1112 /* lock the driver */
1113 AQUIRE_BEN(pd->kernel);
1114
1115 /* if opened multiple times, decrement the open count and exit */
1116 if (di->is_open > 1)
1117 goto unlock_and_exit;
1118
1119 /* disable and clear any pending interrupts */
1120 //fixme:
1121 //distinquish between crtc1/crtc2 once all heads get seperate driver instances!
1122 disable_vbi_all(regs);
1123
1124 if (si->ps.int_assigned) {
1125 /* remove interrupt handler */
1126 remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di);
1127
1128 /* delete the semaphores, ignoring any errors ('cause the owning
1129 team may have died on us) */
1130 delete_sem(si->vblank);
1131 si->vblank = -1;
1132 }
1133
1134 /* free regs and framebuffer areas */
1135 unmap_device(di);
1136
1137 /* clean up our aligned DMA area */
1138 delete_area(si->dma_area);
1139 si->dma_area = -1;
1140 si->dma_buffer = NULL;
1141
1142 /* clean up our unaligned DMA area */
1143 delete_area(si->unaligned_dma_area);
1144 si->unaligned_dma_area = -1;
1145 si->dma_buffer_pci = NULL;
1146
1147 /* clean up our shared area */
1148 delete_area(di->shared_area);
1149 di->shared_area = -1;
1150 di->si = NULL;
1151
1152 unlock_and_exit:
1153 /* mark the device available */
1154 di->is_open--;
1155 /* unlock the driver */
1156 RELEASE_BEN(pd->kernel);
1157 /* all done */
1158 return B_OK;
1159 }
1160
1161
1162 static status_t
1163 control_hook(void* dev, uint32 msg, void *buf, size_t len)
1164 {
1165 device_info *di = (device_info *)dev;
1166 status_t result = B_DEV_INVALID_IOCTL;
1167 uint32 tmpUlong;
1168
1169 switch (msg) {
1170 /* the only PUBLIC ioctl */
1171 case B_GET_ACCELERANT_SIGNATURE:
1172 {
1173 strcpy((char* )buf, sSettings.accelerant);
1174 result = B_OK;
1175 break;
1176 }
1177
1178 /* PRIVATE ioctl from here on */
1179 case NV_GET_PRIVATE_DATA:
1180 {
1181 nv_get_private_data *gpd = (nv_get_private_data *)buf;
1182 if (gpd->magic == NV_PRIVATE_DATA_MAGIC) {
1183 gpd->shared_info_area = di->shared_area;
1184 result = B_OK;
1185 }
1186 break;
1187 }
1188
1189 case NV_GET_PCI:
1190 {
1191 nv_get_set_pci *gsp = (nv_get_set_pci *)buf;
1192 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) {
1193 pci_info *pcii = &(di->pcii);
1194 gsp->value = get_pci(gsp->offset, gsp->size);
1195 result = B_OK;
1196 }
1197 break;
1198 }
1199
1200 case NV_SET_PCI:
1201 {
1202 nv_get_set_pci *gsp = (nv_get_set_pci *)buf;
1203 if (gsp->magic == NV_PRIVATE_DATA_MAGIC) {
1204 pci_info *pcii = &(di->pcii);
1205 set_pci(gsp->offset, gsp->size, gsp->value);
1206 result = B_OK;
1207 }
1208 break;
1209 }
1210
1211 case NV_DEVICE_NAME:
1212 {
1213 nv_device_name *dn = (nv_device_name *)buf;
1214 if (dn->magic == NV_PRIVATE_DATA_MAGIC) {
1215 strcpy(dn->name, di->name);
1216 result = B_OK;
1217 }
1218 break;
1219 }
1220
1221 case NV_RUN_INTERRUPTS:
1222 {
1223 nv_set_vblank_int *vi = (nv_set_vblank_int *)buf;
1224 if (vi->magic == NV_PRIVATE_DATA_MAGIC) {
1225 vuint32 *regs = di->regs;
1226 if (!(vi->crtc)) {
1227 if (vi->do_it) {
1228 enable_vbi_crtc1(regs);
1229 } else {
1230 disable_vbi_crtc1(regs);
1231 }
1232 } else {
1233 if (vi->do_it) {
1234 enable_vbi_crtc2(regs);
1235 } else {
1236 disable_vbi_crtc2(regs);
1237 }
1238 }
1239 result = B_OK;
1240 }
1241 break;
1242 }
1243
1244 case NV_GET_NTH_AGP_INFO:
1245 {
1246 nv_nth_agp_info *nai = (nv_nth_agp_info *)buf;
1247 if (nai->magic == NV_PRIVATE_DATA_MAGIC) {
1248 nai->exist = false;
1249 nai->agp_bus = false;
1250 if (agp_bus) {
1251 nai->agp_bus = true;
1252 if ((*agp_bus->get_nth_agp_info)(nai->index, &(nai->agpi)) == B_NO_ERROR) {
1253 nai->exist = true;
1254 }
1255 }
1256 result = B_OK;
1257 }
1258 break;
1259 }
1260
1261 case NV_ENABLE_AGP:
1262 {
1263 nv_cmd_agp *nca = (nv_cmd_agp *)buf;
1264 if (nca->magic == NV_PRIVATE_DATA_MAGIC) {
1265 if (agp_bus) {
1266 nca->agp_bus = true;
1267 nca->cmd = agp_bus->set_agp_mode(nca->cmd);
1268 } else {
1269 nca->agp_bus = false;
1270 nca->cmd = 0;
1271 }
1272 result = B_OK;
1273 }
1274 break;
1275 }
1276
1277 case NV_ISA_OUT:
1278 {
1279 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf;
1280 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) {
1281 pci_info *pcii = &(di->pcii);
1282
1283 /* lock the driver:
1284 * no other graphics card may have ISA I/O enabled when we enter */
1285 AQUIRE_BEN(pd->kernel);
1286
1287 /* enable ISA I/O access */
1288 tmpUlong = get_pci(PCI_command, 2);
1289 tmpUlong |= PCI_command_io;
1290 set_pci(PCI_command, 2, tmpUlong);
1291
1292 if (io_isa->size == 1)
1293 isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data);
1294 else
1295 isa_bus->write_io_16(io_isa->adress, io_isa->data);
1296 result = B_OK;
1297
1298 /* disable ISA I/O access */
1299 tmpUlong = get_pci(PCI_command, 2);
1300 tmpUlong &= ~PCI_command_io;
1301 set_pci(PCI_command, 2, tmpUlong);
1302
1303 /* end of critical section */
1304 RELEASE_BEN(pd->kernel);
1305 }
1306 break;
1307 }
1308
1309 case NV_ISA_IN:
1310 {
1311 nv_in_out_isa *io_isa = (nv_in_out_isa *)buf;
1312 if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) {
1313 pci_info *pcii = &(di->pcii);
1314
1315 /* lock the driver:
1316 * no other graphics card may have ISA I/O enabled when we enter */
1317 AQUIRE_BEN(pd->kernel);
1318
1319 /* enable ISA I/O access */
1320 tmpUlong = get_pci(PCI_command, 2);
1321 tmpUlong |= PCI_command_io;
1322 set_pci(PCI_command, 2, tmpUlong);
1323
1324 if (io_isa->size == 1)
1325 io_isa->data = isa_bus->read_io_8(io_isa->adress);
1326 else
1327 io_isa->data = isa_bus->read_io_16(io_isa->adress);
1328 result = B_OK;
1329
1330 /* disable ISA I/O access */
1331 tmpUlong = get_pci(PCI_command, 2);
1332 tmpUlong &= ~PCI_command_io;
1333 set_pci(PCI_command, 2, tmpUlong);
1334
1335 /* end of critical section */
1336 RELEASE_BEN(pd->kernel);
1337 }
1338 break;
1339 }
1340 }
1341
1342 return result;
1343 }
1344
1345
1346 // #pragma mark - driver API
1347
1348
1349 status_t
1350 init_hardware(void)
1351 {
1352 long index = 0;
1353 pci_info pcii;
1354 bool found = false;
1355
1356 /* choke if we can't find the PCI bus */
1357 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK)
1358 return B_ERROR;
1359
1360 /* choke if we can't find the ISA bus */
1361 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK)
1362 {
1363 put_module(B_PCI_MODULE_NAME);
1364 return B_ERROR;
1365 }
1366
1367 /* while there are more pci devices */
1368 while ((*pci_bus->get_nth_pci_info)(index, &pcii) == B_NO_ERROR) {
1369 int vendor = 0;
1370
1371 /* if we match a supported vendor */
1372 while (SupportedDevices[vendor].vendor) {
1373 if (SupportedDevices[vendor].vendor == pcii.vendor_id) {
1374 uint16 *devices = SupportedDevices[vendor].devices;
1375 /* while there are more supported devices */
1376 while (*devices) {
1377 /* if we match a supported device */
1378 if (*devices == pcii.device_id ) {
1379
1380 found = true;
1381 goto done;
1382 }
1383 /* next supported device */
1384 devices++;
1385 }
1386 }
1387 vendor++;
1388 }
1389 /* next pci_info struct, please */
1390 index++;
1391 }
1392
1393 done:
1394 /* put away the module manager */
1395 put_module(B_PCI_MODULE_NAME);
1396 return found ? B_OK : B_ERROR;
1397 }
1398
1399
1400 status_t
1401 init_driver(void)
1402 {
1403 void *settings;
1404
1405 // get driver/accelerant settings
1406 settings = load_driver_settings(DRIVER_PREFIX ".settings");
1407 if (settings != NULL) {
1408 const char *item;
1409 char *end;
1410 uint32 value;
1411
1412 // for driver
1413 item = get_driver_parameter(settings, "accelerant", "", "");
1414 if (item[0] && strlen(item) < sizeof(sSettings.accelerant) - 1)
1415 strcpy (sSettings.accelerant, item);
1416
1417 item = get_driver_parameter(settings, "primary", "", "");
1418 if (item[0] && strlen(item) < sizeof(sSettings.primary) - 1)
1419 strcpy(sSettings.primary, item);
1420
1421 sSettings.dumprom = get_driver_boolean_parameter(settings,
1422 "dumprom", false, false);
1423
1424 // for accelerant
1425 item = get_driver_parameter(settings, "logmask",
1426 "0x00000000", "0x00000000");
1427 value = strtoul(item, &end, 0);
1428 if (*end == '\0')
1429 sSettings.logmask = value;
1430
1431 item = get_driver_parameter(settings, "memory", "0", "0");
1432 value = strtoul(item, &end, 0);
1433 if (*end == '\0')
1434 sSettings.memory = value;
1435
1436 item = get_driver_parameter(settings, "tv_output", "0", "0");
1437 value = strtoul(item, &end, 0);
1438 if (*end == '\0')
1439 sSettings.tv_output = value;
1440
1441 sSettings.hardcursor = get_driver_boolean_parameter(settings,
1442 "hardcursor", true, true);
1443 sSettings.usebios = get_driver_boolean_parameter(settings,
1444 "usebios", true, true);
1445 sSettings.switchhead = get_driver_boolean_parameter(settings,
1446 "switchhead", false, false);
1447 sSettings.force_pci = get_driver_boolean_parameter(settings,
1448 "force_pci", false, false);
1449 sSettings.unhide_fw = get_driver_boolean_parameter(settings,
1450 "unhide_fw", false, false);
1451 sSettings.pgm_panel = get_driver_boolean_parameter(settings,
1452 "pgm_panel", false, false);
1453 sSettings.dma_acc = get_driver_boolean_parameter(settings,
1454 "dma_acc", true, true);
1455 sSettings.vga_on_tv = get_driver_boolean_parameter(settings,
1456 "vga_on_tv", false, false);
1457 sSettings.force_sync = get_driver_boolean_parameter(settings,
1458 "force_sync", false, false);
1459 sSettings.force_ws = get_driver_boolean_parameter(settings,
1460 "force_ws", false, false);
1461 sSettings.block_acc = get_driver_boolean_parameter(settings,
1462 "block_acc", false, false);
1463
1464 item = get_driver_parameter(settings, "gpu_clk", "0", "0");
1465 value = strtoul(item, &end, 0);
1466 if (*end == '\0')
1467 sSettings.gpu_clk = value;
1468
1469 item = get_driver_parameter(settings, "ram_clk", "0", "0");
1470 value = strtoul(item, &end, 0);
1471 if (*end == '\0')
1472 sSettings.ram_clk = value;
1473
1474 unload_driver_settings(settings);
1475 }
1476
1477 /* get a handle for the pci bus */
1478 if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK)
1479 return B_ERROR;
1480
1481 /* get a handle for the isa bus */
1482 if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) {
1483 put_module(B_PCI_MODULE_NAME);
1484 return B_ERROR;
1485 }
1486
1487 /* get a handle for the agp bus if it exists */
1488 get_module(B_AGP_GART_MODULE_NAME, (module_info **)&agp_bus);
1489
1490 /* driver private data */
1491 pd = (DeviceData *)calloc(1, sizeof(DeviceData));
1492 if (!pd) {
1493 put_module(B_PCI_MODULE_NAME);
1494 return B_ERROR;
1495 }
1496 /* initialize the benaphore */
1497 INIT_BEN(pd->kernel);
1498 /* find all of our supported devices */
1499 probe_devices();
1500 return B_OK;
1501 }
1502
1503
1504 const char **
1505 publish_devices(void)
1506 {
1507 /* return the list of supported devices */
1508 return (const char **)pd->device_names;
1509 }
1510
1511
1512 device_hooks *
1513 find_device(const char *name)
1514 {
1515 int index = 0;
1516 while (pd->device_names[index]) {
1517 if (strcmp(name, pd->device_names[index]) == 0)
1518 return &graphics_device_hooks;
1519 index++;
1520 }
1521 return NULL;
1522
1523 }
1524
1525
1526 void
1527 uninit_driver(void)
1528 {
1529 /* free the driver data */
1530 DELETE_BEN(pd->kernel);
1531 free(pd);
1532 pd = NULL;
1533
1534 /* put the pci module away */
1535 put_module(B_PCI_MODULE_NAME);
1536 put_module(B_ISA_MODULE_NAME);
1537
1538 /* put the agp module away if it's there */
1539 if (agp_bus)
1540 put_module(B_AGP_GART_MODULE_NAME);
1541 }
1542
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