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BPicture: Fix archive constructor.
[haiku.git] / src / add-ons / kernel / drivers / network / bcm440x / b44.h
blobd144fa92f216b5ac279415ca286f5634cb0478c7
1
2 /******************************************************************************/
3 /* */
4 /* Broadcom BCM4400 Linux Network Driver, Copyright (c) 2002 Broadcom */
5 /* Corporation. */
6 /* All rights reserved. */
7 /* */
8 /* This program is free software; you can redistribute it and/or modify */
9 /* it under the terms of the GNU General Public License as published by */
10 /* the Free Software Foundation, located in the file LICENSE. */
11 /* */
12 /* History: */
13 /* */
14 /******************************************************************************/
15
16 #ifndef B44_H
17 #define B44_H
18
19 #include "b44lm.h"
20
21
22
23 /******************************************************************************/
24 /* Constants. */
25 /******************************************************************************/
26
27 /* Maxim number of packet descriptors used for sending packets. */
28 #define MAX_TX_PACKET_DESC_COUNT 512
29 #define DEFAULT_TX_PACKET_DESC_COUNT 64
30
31 #define MAX_RX_PACKET_DESC_COUNT 512
32 #define DEFAULT_RX_PACKET_DESC_COUNT 64
33
34 #define BIT_0 0x01
35 #define BIT_1 0x02
36 #define BIT_2 0x04
37 #define BIT_3 0x08
38 #define BIT_4 0x10
39 #define BIT_5 0x20
40 #define BIT_6 0x40
41 #define BIT_7 0x80
42 #define BIT_8 0x100
43 #define BIT_9 0x200
44 #define BIT_10 0x400
45 #define BIT_11 0x800
46 #define BIT_12 0x1000
47 #define BIT_13 0x2000
48 #define BIT_14 0x4000
49 #define BIT_15 0x8000
50 #define BIT_16 0x10000
51 #define BIT_17 0x20000
52 #define BIT_18 0x40000
53 #define BIT_19 0x80000
54 #define BIT_20 0x100000
55 #define BIT_21 0x200000
56 #define BIT_22 0x400000
57 #define BIT_23 0x800000
58 #define BIT_24 0x1000000
59 #define BIT_25 0x2000000
60 #define BIT_26 0x4000000
61 #define BIT_27 0x8000000
62 #define BIT_28 0x10000000
63 #define BIT_29 0x20000000
64 #define BIT_30 0x40000000
65 #define BIT_31 0x80000000
66
67 #define ROUNDUP(x, y) ((((LM_UINT32)(x)+((y)-1))/(y))*(y))
68
69 /******************************************************************************/
70 /* MII registers. */
71 /******************************************************************************/
72
73 /* Control register. */
74 #define PHY_CTRL_REG 0x00
75
76 #define PHY_CTRL_SPEED_MASK (BIT_6 | BIT_13)
77 #define PHY_CTRL_SPEED_SELECT_10MBPS BIT_NONE
78 #define PHY_CTRL_SPEED_SELECT_100MBPS BIT_13
79 #define PHY_CTRL_SPEED_SELECT_1000MBPS BIT_6
80 #define PHY_CTRL_COLLISION_TEST_ENABLE BIT_7
81 #define PHY_CTRL_FULL_DUPLEX_MODE BIT_8
82 #define PHY_CTRL_RESTART_AUTO_NEG BIT_9
83 #define PHY_CTRL_ISOLATE_PHY BIT_10
84 #define PHY_CTRL_LOWER_POWER_MODE BIT_11
85 #define PHY_CTRL_AUTO_NEG_ENABLE BIT_12
86 #define PHY_CTRL_LOOPBACK_MODE BIT_14
87 #define PHY_CTRL_PHY_RESET BIT_15
88
89
90 /* Status register. */
91 #define PHY_STATUS_REG 0x01
92
93 #define PHY_STATUS_LINK_PASS BIT_2
94 #define PHY_STATUS_AUTO_NEG_COMPLETE BIT_5
95
96
97 /* Phy Id registers. */
98 #define PHY_ID1_REG 0x02
99 #define PHY_ID1_OUI_MASK 0xffff
100
101 #define PHY_ID2_REG 0x03
102 #define PHY_ID2_REV_MASK 0x000f
103 #define PHY_ID2_MODEL_MASK 0x03f0
104 #define PHY_ID2_OUI_MASK 0xfc00
105
106
107 /* Auto-negotiation advertisement register. */
108 #define PHY_AN_AD_REG 0x04
109
110 #define PHY_AN_AD_ASYM_PAUSE BIT_11
111 #define PHY_AN_AD_PAUSE_CAPABLE BIT_10
112 #define PHY_AN_AD_10BASET_HALF BIT_5
113 #define PHY_AN_AD_10BASET_FULL BIT_6
114 #define PHY_AN_AD_100BASETX_HALF BIT_7
115 #define PHY_AN_AD_100BASETX_FULL BIT_8
116 #define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD 0x01
117
118 #define PHY_AN_AD_ALL_SPEEDS (PHY_AN_AD_10BASET_HALF | \
119 PHY_AN_AD_10BASET_FULL | PHY_AN_AD_100BASETX_HALF | \
120 PHY_AN_AD_100BASETX_FULL)
121
122 /* Auto-negotiation Link Partner Ability register. */
123 #define PHY_LINK_PARTNER_ABILITY_REG 0x05
124
125 #define PHY_LINK_PARTNER_ASYM_PAUSE BIT_11
126 #define PHY_LINK_PARTNER_PAUSE_CAPABLE BIT_10
127
128
129 #define STAT_REMFAULT (1 << 4) /* remote fault */
130 #define STAT_LINK (1 << 2) /* link status */
131 #define STAT_JAB (1 << 1) /* jabber detected */
132 #define AUX_FORCED (1 << 2) /* forced 10/100 */
133 #define AUX_SPEED (1 << 1) /* speed 0=10mbps 1=100mbps */
134 #define AUX_DUPLEX (1 << 0) /* duplex 0=half 1=full */
135
136
137 /******************************************************************************/
138 /* Register definitions. */
139 /******************************************************************************/
140
141 typedef volatile LM_UINT8 T3_8BIT_REGISTER, *PT3_8BIT_REGISTER;
142 typedef volatile LM_UINT16 T3_16BIT_REGISTER, *PT3_16BIT_REGISTER;
143 typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER;
144
145 /*
146 * Each DMA processor consists of a transmit channel and a receive channel.
147 */
148 typedef volatile struct {
149 /* transmit channel */
150 LM_UINT32 xmtcontrol; /* enable, et al */
151 LM_UINT32 xmtaddr; /* descriptor ring base address (4K aligned) */
152 LM_UINT32 xmtptr; /* last descriptor posted to chip */
153 LM_UINT32 xmtstatus; /* current active descriptor, et al */
154
155 /* receive channel */
156 LM_UINT32 rcvcontrol; /* enable, et al */
157 LM_UINT32 rcvaddr; /* descriptor ring base address (4K aligned) */
158 LM_UINT32 rcvptr; /* last descriptor posted to chip */
159 LM_UINT32 rcvstatus; /* current active descriptor, et al */
160
161 /* diag access */
162 LM_UINT32 fifoaddr; /* diag address */
163 LM_UINT32 fifodatalow; /* low 32bits of data */
164 LM_UINT32 fifodatahigh; /* high 32bits of data */
165 LM_UINT32 pad; /* reserved */
166 } dmaregs_t;
167
168 /* transmit channel control */
169 #define XC_XE ((LM_UINT32)1 << 0) /* transmit enable */
170 #define XC_SE ((LM_UINT32)1 << 1) /* transmit suspend request */
171 #define XC_LE ((LM_UINT32)1 << 2) /* loopback enable */
172 #define XC_FPRI ((LM_UINT32)1 << 3) /* fair priority */
173 #define XC_FL ((LM_UINT32)1 << 4) /* flush request */
174
175 /* transmit descriptor table pointer */
176 #define XP_LD_MASK 0xfff /* last valid descriptor */
177
178 /* transmit channel status */
179 #define XS_CD_MASK 0x0fff /* current descriptor pointer */
180 #define XS_XS_MASK 0xf000 /* transmit state */
181 #define XS_XS_SHIFT 12
182 #define XS_XS_DISABLED 0x0000 /* disabled */
183 #define XS_XS_ACTIVE 0x1000 /* active */
184 #define XS_XS_IDLE 0x2000 /* idle wait */
185 #define XS_XS_STOPPED 0x3000 /* stopped */
186 #define XS_XS_SUSP 0x4000 /* suspend pending */
187 #define XS_XE_MASK 0xf0000 /* transmit errors */
188 #define XS_XE_SHIFT 16
189 #define XS_XE_NOERR 0x00000 /* no error */
190 #define XS_XE_DPE 0x10000 /* descriptor protocol error */
191 #define XS_XE_DFU 0x20000 /* data fifo underrun */
192 #define XS_XE_BEBR 0x30000 /* bus error on buffer read */
193 #define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
194 #define XS_FL ((LM_UINT32)1 << 20) /* flushed */
195
196 /* receive channel control */
197 #define RC_RE ((LM_UINT32)1 << 0) /* receive enable */
198 #define RC_RO_MASK 0xfe /* receive frame offset */
199 #define RC_RO_SHIFT 1
200
201 /* receive descriptor table pointer */
202 #define RP_LD_MASK 0xfff /* last valid descriptor */
203
204 /* receive channel status */
205 #define RS_CD_MASK 0x0fff /* current descriptor pointer */
206 #define RS_RS_MASK 0xf000 /* receive state */
207 #define RS_RS_SHIFT 12
208 #define RS_RS_DISABLED 0x0000 /* disabled */
209 #define RS_RS_ACTIVE 0x1000 /* active */
210 #define RS_RS_IDLE 0x2000 /* idle wait */
211 #define RS_RS_STOPPED 0x3000 /* reserved */
212 #define RS_RE_MASK 0xf0000 /* receive errors */
213 #define RS_RE_SHIFT 16
214 #define RS_RE_NOERR 0x00000 /* no error */
215 #define RS_RE_DPE 0x10000 /* descriptor protocol error */
216 #define RS_RE_DFO 0x20000 /* data fifo overflow */
217 #define RS_RE_BEBW 0x30000 /* bus error on buffer write */
218 #define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
219
220 /* fifoaddr */
221 #define FA_OFF_MASK 0xffff /* offset */
222 #define FA_SEL_MASK 0xf0000 /* select */
223 #define FA_SEL_SHIFT 16
224 #define FA_SEL_XDD 0x00000 /* transmit dma data */
225 #define FA_SEL_XDP 0x10000 /* transmit dma pointers */
226 #define FA_SEL_RDD 0x40000 /* receive dma data */
227 #define FA_SEL_RDP 0x50000 /* receive dma pointers */
228 #define FA_SEL_XFD 0x80000 /* transmit fifo data */
229 #define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
230 #define FA_SEL_RFD 0xc0000 /* receive fifo data */
231 #define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
232
233 /*
234 * DMA Descriptor
235 * Descriptors are only read by the hardware, never written back.
236 */
237 typedef volatile struct {
238 LM_UINT32 ctrl; /* misc control bits & bufcount */
239 LM_UINT32 addr; /* data buffer address */
240 } dmadd_t;
241
242 /*
243 * Each descriptor ring must be 4096byte aligned
244 * and fit within a single 4096byte page.
245 */
246 #define DMAMAXRINGSZ 4096
247 #define DMARINGALIGN 4096
248
249 /* control flags */
250 #define CTRL_BC_MASK 0x1fff /* buffer byte count */
251 #define CTRL_EOT ((LM_UINT32)1 << 28) /* end of descriptor table */
252 #define CTRL_IOC ((LM_UINT32)1 << 29) /* interrupt on completion */
253 #define CTRL_EOF ((LM_UINT32)1 << 30) /* end of frame */
254 #define CTRL_SOF ((LM_UINT32)1 << 31) /* start of frame */
255
256 /* control flags in the range [27:20] are core-specific and not defined here */
257 #define CTRL_CORE_MASK 0x0ff00000
258
259
260 #define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
261 #define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
262 #define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
263 #define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
264
265 /* power management event wakeup pattern constants */
266 #define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
267 #define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
268 #define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
269 #define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
270 #define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
271
272 /* PCI config space "back door" access registers */
273 #define BCMENET_BACK_DOOR_ADDR 0xa0
274 #define BCMENET_BACK_DOOR_DATA 0xa4
275
276 #define BCMENET_PMC 0x42
277 #define BCMENET_PMCSR 0x44
278 #define ENABLE_PCICONFIG_PME 0x8100
279
280 /* cpp contortions to concatenate w/arg prescan */
281 #ifndef PAD
282 #define _PADLINE(line) pad ## line
283 #define _XSTR(line) _PADLINE(line)
284 #define PAD _XSTR(__LINE__)
285 #endif /* PAD */
286
287 /*
288 * EMAC MIB Registers
289 */
290 typedef volatile struct {
291 LM_UINT32 tx_good_octets;
292 LM_UINT32 tx_good_pkts;
293 LM_UINT32 tx_octets;
294 LM_UINT32 tx_pkts;
295 LM_UINT32 tx_broadcast_pkts;
296 LM_UINT32 tx_multicast_pkts;
297 LM_UINT32 tx_len_64;
298 LM_UINT32 tx_len_65_to_127;
299 LM_UINT32 tx_len_128_to_255;
300 LM_UINT32 tx_len_256_to_511;
301 LM_UINT32 tx_len_512_to_1023;
302 LM_UINT32 tx_len_1024_to_max;
303 LM_UINT32 tx_jabber_pkts;
304 LM_UINT32 tx_oversize_pkts;
305 LM_UINT32 tx_fragment_pkts;
306 LM_UINT32 tx_underruns;
307 LM_UINT32 tx_total_cols;
308 LM_UINT32 tx_single_cols;
309 LM_UINT32 tx_multiple_cols;
310 LM_UINT32 tx_excessive_cols;
311 LM_UINT32 tx_late_cols;
312 LM_UINT32 tx_defered;
313 LM_UINT32 tx_carrier_lost;
314 LM_UINT32 tx_pause_pkts;
315 LM_UINT32 PAD[8];
316
317 LM_UINT32 rx_good_octets;
318 LM_UINT32 rx_good_pkts;
319 LM_UINT32 rx_octets;
320 LM_UINT32 rx_pkts;
321 LM_UINT32 rx_broadcast_pkts;
322 LM_UINT32 rx_multicast_pkts;
323 LM_UINT32 rx_len_64;
324 LM_UINT32 rx_len_65_to_127;
325 LM_UINT32 rx_len_128_to_255;
326 LM_UINT32 rx_len_256_to_511;
327 LM_UINT32 rx_len_512_to_1023;
328 LM_UINT32 rx_len_1024_to_max;
329 LM_UINT32 rx_jabber_pkts;
330 LM_UINT32 rx_oversize_pkts;
331 LM_UINT32 rx_fragment_pkts;
332 LM_UINT32 rx_missed_pkts;
333 LM_UINT32 rx_crc_align_errs;
334 LM_UINT32 rx_undersize;
335 LM_UINT32 rx_crc_errs;
336 LM_UINT32 rx_align_errs;
337 LM_UINT32 rx_symbol_errs;
338 LM_UINT32 rx_pause_pkts;
339 LM_UINT32 rx_nonpause_pkts;
340 } bcmenetmib_t;
341
342 #define SB_ENUM_BASE 0x18000000
343 #define SB_CORE_SIZE 0x1000
344 #define SBCONFIGOFF 0xf00 /* core register space offset in bytes */
345 #define SBCONFIGSIZE 256 /* size in bytes */
346
347 /*
348 * Sonics Configuration Space Registers.
349 */
350 typedef volatile struct _sbconfig {
351 LM_UINT32 PAD[2];
352 LM_UINT32 sbipsflag; /* initiator port ocp slave flag */
353 LM_UINT32 PAD[3];
354 LM_UINT32 sbtpsflag; /* target port ocp slave flag */
355 LM_UINT32 PAD[17];
356 LM_UINT32 sbadmatch3; /* address match3 */
357 LM_UINT32 PAD;
358 LM_UINT32 sbadmatch2; /* address match2 */
359 LM_UINT32 PAD;
360 LM_UINT32 sbadmatch1; /* address match1 */
361 LM_UINT32 PAD[7];
362 LM_UINT32 sbimstate; /* initiator agent state */
363 LM_UINT32 sbintvec; /* interrupt mask */
364 LM_UINT32 sbtmstatelow; /* target state */
365 LM_UINT32 sbtmstatehigh; /* target state */
366 LM_UINT32 sbbwa0; /* bandwidth allocation table0 */
367 LM_UINT32 PAD;
368 LM_UINT32 sbimconfiglow; /* initiator configuration */
369 LM_UINT32 sbimconfighigh; /* initiator configuration */
370 LM_UINT32 sbadmatch0; /* address match0 */
371 LM_UINT32 PAD;
372 LM_UINT32 sbtmconfiglow; /* target configuration */
373 LM_UINT32 sbtmconfighigh; /* target configuration */
374 LM_UINT32 sbbconfig; /* broadcast configuration */
375 LM_UINT32 PAD;
376 LM_UINT32 sbbstate; /* broadcast state */
377 LM_UINT32 PAD[3];
378 LM_UINT32 sbactcnfg; /* activate configuration */
379 LM_UINT32 PAD[3];
380 LM_UINT32 sbflagst; /* current sbflags */
381 LM_UINT32 PAD[3];
382 LM_UINT32 sbidlow; /* identification */
383 LM_UINT32 sbidhigh; /* identification */
384 } sbconfig_t;
385
386 /* XXX 4710-specific and should be deleted since they can be read from sbtpsflag */
387 /* interrupt sbFlags */
388 #define SBFLAG_PCI 0
389 #define SBFLAG_ENET0 1
390 #define SBFLAG_ILINE20 2
391 #define SBFLAG_CODEC 3
392 #define SBFLAG_USB 4
393 #define SBFLAG_EXTIF 5
394 #define SBFLAG_ENET1 6
395
396 /* sbipsflag */
397 #define SBIPSFLAG 0x08 /* offset */
398 #define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
399 #define SBIPS_INT1_SHIFT 0
400 #define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
401 #define SBIPS_INT2_SHIFT 8
402 #define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
403 #define SBIPS_INT3_SHIFT 16
404 #define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
405 #define SBIPS_INT4_SHIFT 24
406
407 /* sbtpsflag */
408 #define SBTPSFLAG 0x18 /* offset */
409 #define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
410 #define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
411
412 /* sbadmatch */
413 #define SBADMATCH3 0x60 /* offset */
414 #define SBADMATCH2 0x68 /* offset */
415 #define SBADMATCH1 0x70 /* offset */
416
417 /* sbimstate */
418 #define SBIMSTATE 0x90 /* offset */
419 #define SBIM_PC 0xf /* pipecount */
420 #define SBIM_AP_MASK 0x30 /* arbitration policy */
421 #define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
422 #define SBIM_AP_TS 0x10 /* use timesliaces only */
423 #define SBIM_AP_TK 0x20 /* use token only */
424 #define SBIM_AP_RSV 0x30 /* reserved */
425 #define SBIM_IBE 0x20000 /* inbanderror */
426 #define SBIM_TO 0x40000 /* timeout */
427
428 /* sbintvec */
429 #define SBINTVEC 0x94 /* offset */
430 #define SBIV_PCI 0x1 /* enable interrupts for pci */
431 #define SBIV_ENET0 0x2 /* enable interrupts for enet 0 */
432 #define SBIV_ILINE20 0x4 /* enable interrupts for iline20 */
433 #define SBIV_CODEC 0x8 /* enable interrupts for v90 codec */
434 #define SBIV_USB 0x10 /* enable interrupts for usb */
435 #define SBIV_EXTIF 0x20 /* enable interrupts for external i/f */
436 #define SBIV_ENET1 0x40 /* enable interrupts for enet 1 */
437
438 /* sbtmstatelow */
439 #define SBTMSTATELOW 0x98 /* offset */
440 #define SBTML_RESET 0x1 /* reset */
441 #define SBTML_REJ 0x2 /* reject */
442 #define SBTML_CLK 0x10000 /* clock enable */
443 #define SBTML_FGC 0x20000 /* force gated clocks on */
444 #define SBTML_PE 0x40000000 /* pme enable */
445 #define SBTML_BE 0x80000000 /* bist enable */
446
447 /* sbtmstatehigh */
448 #define SBTMSTATEHIGH 0x9C /* offset */
449 #define SBTMH_SERR 0x1 /* serror */
450 #define SBTMH_INT 0x2 /* interrupt */
451 #define SBTMH_BUSY 0x4 /* busy */
452 #define SBTMH_GCR 0x20000000 /* gated clock request */
453 #define SBTMH_BISTF 0x40000000 /* bist failed */
454 #define SBTMH_BISTD 0x80000000 /* bist done */
455
456 /* sbbwa0 */
457 #define SBBWA0 0xA0 /* offset */
458 #define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
459 #define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
460 #define SBBWA_TAB1_SHIFT 16
461
462 /* sbimconfiglow */
463 #define SBIMCONFIGLOW 0xA8 /* offset */
464 #define SBIMCL_STO_MASK 0x3 /* service timeout */
465 #define SBIMCL_RTO_MASK 0x30 /* request timeout */
466 #define SBIMCL_RTO_SHIFT 4
467 #define SBIMCL_CID_MASK 0xff0000 /* connection id */
468 #define SBIMCL_CID_SHIFT 16
469
470 /* sbimconfighigh */
471 #define SBIMCONFIGHIGH 0xAC /* offset */
472 #define SBIMCH_IEM_MASK 0xc /* inband error mode */
473 #define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
474 #define SBIMCH_TEM_SHIFT 4
475 #define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
476 #define SBIMCH_BEM_SHIFT 6
477
478 /* sbadmatch0 */
479 #define SBADMATCH0 0xB0 /* offset */
480 #define SBAM_TYPE_MASK 0x3 /* address type */
481 #define SBAM_AD64 0x4 /* reserved */
482 #define SBAM_ADINT0_MASK 0xf8 /* type0 size */
483 #define SBAM_ADINT0_SHIFT 3
484 #define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
485 #define SBAM_ADINT1_SHIFT 3
486 #define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
487 #define SBAM_ADINT2_SHIFT 3
488 #define SBAM_ADEN 0x400 /* enable */
489 #define SBAM_ADNEG 0x800 /* negative decode */
490 #define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
491 #define SBAM_BASE0_SHIFT 8
492 #define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
493 #define SBAM_BASE1_SHIFT 12
494 #define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
495 #define SBAM_BASE2_SHIFT 16
496
497 /* sbtmconfiglow */
498 #define SBTMCONFIGLOW 0xB8 /* offset */
499 #define SBTMCL_CD_MASK 0xff /* clock divide */
500 #define SBTMCL_CO_MASK 0xf800 /* clock offset */
501 #define SBTMCL_CO_SHIFT 11
502 #define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
503 #define SBTMCL_IF_SHIFT 18
504 #define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
505 #define SBTMCL_IM_SHIFT 24
506
507 /* sbtmconfighigh */
508 #define SBTMCONFIGHIGH 0xBC /* offset */
509 #define SBTMCH_BM_MASK 0x3 /* busy mode */
510 #define SBTMCH_RM_MASK 0x3 /* retry mode */
511 #define SBTMCH_RM_SHIFT 2
512 #define SBTMCH_SM_MASK 0x30 /* stop mode */
513 #define SBTMCH_SM_SHIFT 4
514 #define SBTMCH_EM_MASK 0x300 /* sb error mode */
515 #define SBTMCH_EM_SHIFT 8
516 #define SBTMCH_IM_MASK 0xc00 /* int mode */
517 #define SBTMCH_IM_SHIFT 10
518
519 /* sbbconfig */
520 #define SBBCONFIG 0xC0 /* offset */
521 #define SBBC_LAT_MASK 0x3 /* sb latency */
522 #define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
523 #define SBBC_MAX0_SHIFT 16
524 #define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
525 #define SBBC_MAX1_SHIFT 20
526
527 /* sbbstate */
528 #define SBBSTATE 0xC8 /* offset */
529 #define SBBS_SRD 0x1 /* st reg disable */
530 #define SBBS_HRD 0x2 /* hold reg disable */
531
532 /* sbactcnfg */
533 #define SBACTCNFG 0xD8 /* offset */
534
535 /* sbflagst */
536 #define SBFLAGST 0xE8 /* offset */
537
538 /* sbidlow */
539 #define SBIDLOW 0xF8 /* offset */
540 #define SBIDL_CS_MASK 0x3 /* config space */
541 #define SBIDL_AR_MASK 0x38 /* # address ranges supported */
542 #define SBIDL_AR_SHIFT 3
543 #define SBIDL_SYNCH 0x40 /* sync */
544 #define SBIDL_INIT 0x80 /* initiator */
545 #define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
546 #define SBIDL_MINLAT_SHIFT 8
547 #define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
548 #define SBIDL_MAXLAT_SHIFT 12
549 #define SBIDL_FIRST 0x10000 /* this initiator is first */
550 #define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
551 #define SBIDL_CW_SHIFT 18
552 #define SBIDL_TP_MASK 0xf00000 /* target ports */
553 #define SBIDL_TP_SHIFT 20
554 #define SBIDL_IP_MASK 0xf000000 /* initiator ports */
555 #define SBIDL_IP_SHIFT 24
556
557 /* sbidhigh */
558 #define SBIDHIGH 0xFC /* offset */
559 #define SBIDH_RC_MASK 0xf /* revision code*/
560 #define SBIDH_CC_MASK 0xfff0 /* core code */
561 #define SBIDH_CC_SHIFT 4
562 #define SBIDH_VC_MASK 0xffff0000 /* vendor code */
563 #define SBIDH_VC_SHIFT 16
564
565 /* core codes */
566 #define SB_ILINE20 0x801 /* iline20 core */
567 #define SB_SDRAM 0x803 /* sdram core */
568 #define SB_PCI 0x804 /* pci core */
569 #define SB_MIPS 0x805 /* mips core */
570 #define SB_ENET 0x806 /* enet mac core */
571 #define SB_CODEC 0x807 /* v90 codec core */
572 #define SB_USB 0x808 /* usb core */
573 #define SB_ILINE100 0x80a /* iline100 core */
574 #define SB_EXTIF 0x811 /* external interface core */
575
576 struct sbmap {
577 LM_UINT32 id;
578 LM_UINT32 coreunit;
579 LM_UINT32 sbaddr;
580 };
581
582 #define SBID_SDRAM 0
583 #define SBID_PCI_MEM 1
584 #define SBID_PCI_CFG 2
585 #define SBID_PCI_DMA 3
586 #define SBID_SDRAM_SWAPPED 4
587 #define SBID_ENUM 5
588 #define SBID_REG_SDRAM 6
589 #define SBID_REG_ILINE20 7
590 #define SBID_REG_EMAC 8
591 #define SBID_REG_CODEC 9
592 #define SBID_REG_USB 10
593 #define SBID_REG_PCI 11
594 #define SBID_REG_MIPS 12
595 #define SBID_REG_EXTIF 13
596 #define SBID_EXTIF 14
597 #define SBID_EJTAG 15
598 #define SBID_MAX 16
599
600 /*
601 * Host Interface Registers
602 */
603 typedef volatile struct _bcmenettregs {
604 /* Device and Power Control */
605 LM_UINT32 devcontrol;
606 LM_UINT32 PAD[2];
607 LM_UINT32 biststatus;
608 LM_UINT32 wakeuplength;
609 #define DISABLE_32_PATMATCH 0x80800000
610 #define DISABLE_3210_PATMATCH 0x80808080
611 LM_UINT32 PAD[3];
612
613 /* Interrupt Control */
614 LM_UINT32 intstatus;
615 LM_UINT32 intmask;
616 LM_UINT32 gptimer;
617 LM_UINT32 PAD[23];
618
619 /* Ethernet MAC Address Filtering Control */
620 LM_UINT32 enetaddrlo; /* added in B0 */
621 LM_UINT32 enetaddrhi; /* added in B0 */
622 LM_UINT32 enetftaddr;
623 LM_UINT32 enetftdata;
624 LM_UINT32 PAD[2];
625
626 /* Ethernet MAC Control */
627 LM_UINT32 emactxmaxburstlen;
628 LM_UINT32 emacrxmaxburstlen;
629 LM_UINT32 emaccontrol;
630 LM_UINT32 emacflowcontrol;
631
632 LM_UINT32 PAD[20];
633
634 /* DMA Lazy Interrupt Control */
635 LM_UINT32 intrecvlazy;
636 LM_UINT32 PAD[63];
637
638 /* DMA engine */
639 dmaregs_t dmaregs;
640 LM_UINT32 PAD[116];
641
642 /* EMAC Registers */
643 LM_UINT32 rxconfig;
644 LM_UINT32 rxmaxlength;
645 LM_UINT32 txmaxlength;
646 LM_UINT32 PAD;
647 LM_UINT32 mdiocontrol;
648 LM_UINT32 mdiodata;
649 LM_UINT32 emacintmask;
650 LM_UINT32 emacintstatus;
651 LM_UINT32 camdatalo;
652 LM_UINT32 camdatahi;
653 LM_UINT32 camcontrol;
654 LM_UINT32 enetcontrol;
655 LM_UINT32 txcontrol;
656 LM_UINT32 txwatermark;
657 LM_UINT32 mibcontrol;
658 LM_UINT32 PAD[49];
659
660 /* EMAC MIB counters */
661 bcmenetmib_t mib;
662
663 LM_UINT32 PAD[585];
664
665 /* Sonics SiliconBackplane config registers */
666 sbconfig_t sbconfig;
667 } bcmenetregs_t;
668
669 /* device control */
670 #define DC_MPM ((LM_UINT32)1 << 6) /* Magic Packet PME enable(B0)*/
671 #define DC_PM ((LM_UINT32)1 << 7) /* pattern filtering enable */
672 #define DC_IP ((LM_UINT32)1 << 10) /* internal ephy present (rev >= 1) */
673 #define DC_ER ((LM_UINT32)1 << 15) /* ephy reset */
674 #define DC_MP ((LM_UINT32)1 << 16) /* mii phy mode enable */
675 #define DC_CO ((LM_UINT32)1 << 17) /* mii phy mode: enable clocks */
676 #define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
677 #define DC_PA_SHIFT 18
678
679 /* wakeup length */
680 #define WL_P0_MASK 0x7f /* pattern 0 */
681 #define WL_D0 ((LM_UINT32)1 << 7)
682 #define WL_P1_MASK 0x7f00 /* pattern 1 */
683 #define WL_P1_SHIFT 8
684 #define WL_D1 ((LM_UINT32)1 << 15)
685 #define WL_P2_MASK 0x7f0000 /* pattern 2 */
686 #define WL_P2_SHIFT 16
687 #define WL_D2 ((LM_UINT32)1 << 23)
688 #define WL_P3_MASK 0x7f000000 /* pattern 3 */
689 #define WL_P3_SHIFT 24
690 #define WL_D3 ((LM_UINT32)1 << 31)
691
692 /* intstatus and intmask */
693 #define I_LS ((LM_UINT32)1 << 5) /* link change (new in B0) */
694 #define I_PME ((LM_UINT32)1 << 6) /* power management event */
695 #define I_TO ((LM_UINT32)1 << 7) /* general purpose timeout */
696 #define I_PC ((LM_UINT32)1 << 10) /* descriptor error */
697 #define I_PD ((LM_UINT32)1 << 11) /* data error */
698 #define I_DE ((LM_UINT32)1 << 12) /* descriptor protocol error */
699 #define I_RU ((LM_UINT32)1 << 13) /* receive descriptor underflow */
700 #define I_RO ((LM_UINT32)1 << 14) /* receive fifo overflow */
701 #define I_XU ((LM_UINT32)1 << 15) /* transmit fifo underflow */
702 #define I_RI ((LM_UINT32)1 << 16) /* receive interrupt */
703 #define I_XI ((LM_UINT32)1 << 24) /* transmit interrupt */
704 #define I_EM ((LM_UINT32)1 << 26) /* emac interrupt */
705 #define I_MW ((LM_UINT32)1 << 27) /* mii write */
706 #define I_MR ((LM_UINT32)1 << 28) /* mii read */
707
708 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
709 #define DEF_INTMASK (I_TO | I_XI | I_RI | I_ERRORS)
710
711 /* emaccontrol */
712 #define EMC_CG ((LM_UINT32)1 << 0) /* crc32 generation enable */
713 #define EMC_EP ((LM_UINT32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
714 #define EMC_ED ((LM_UINT32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
715 #define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
716 #define EMC_LC_SHIFT 5
717
718 /* emacflowcontrol */
719 #define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
720 #define EMF_PG ((LM_UINT32)1 << 15) /* enable pause frame generation */
721
722 /* interrupt receive lazy */
723 #define IRL_TO_MASK 0x00ffffff /* timeout */
724 #define IRL_FC_MASK 0xff000000 /* frame count */
725 #define IRL_FC_SHIFT 24 /* frame count */
726
727 /* emac receive config */
728 #define ERC_DB ((LM_UINT32)1 << 0) /* disable broadcast */
729 #define ERC_AM ((LM_UINT32)1 << 1) /* accept all multicast */
730 #define ERC_RDT ((LM_UINT32)1 << 2) /* receive disable while transmitting */
731 #define ERC_PE ((LM_UINT32)1 << 3) /* promiscuous enable */
732 #define ERC_LE ((LM_UINT32)1 << 4) /* loopback enable */
733 #define ERC_EF ((LM_UINT32)1 << 5) /* enable flow control */
734 #define ERC_UF ((LM_UINT32)1 << 6) /* accept unicast flow control frame */
735 #define ERC_RF ((LM_UINT32)1 << 7) /* reject filter */
736
737 /* emac mdio control */
738 #define MC_MF_MASK 0x7f /* mdc frequency */
739 #define MC_PE ((LM_UINT32)1 << 7) /* mii preamble enable */
740
741 /* emac mdio data */
742 #define MD_DATA_MASK 0xffffL /* r/w data */
743 #define MD_TA_MASK 0x30000L /* turnaround value */
744 #define MD_TA_SHIFT 16
745 #define MD_TA_VALID (2L << MD_TA_SHIFT) /* valid ta */
746 #define MD_RA_MASK 0x7c0000L /* register address */
747 #define MD_RA_SHIFT 18
748 #define MD_PMD_MASK 0xf800000L /* physical media device */
749 #define MD_PMD_SHIFT 23
750 #define MD_OP_MASK 0x30000000L /* opcode */
751 #define MD_OP_SHIFT 28
752 #define MD_OP_WRITE (1L << MD_OP_SHIFT) /* write op */
753 #define MD_OP_READ (2L << MD_OP_SHIFT) /* read op */
754 #define MD_SB_MASK 0xc0000000L /* start bits */
755 #define MD_SB_SHIFT 30
756 #define MD_SB_START (0x1L << MD_SB_SHIFT) /* start of frame */
757
758 /* emac intstatus and intmask */
759 #define EI_MII ((LM_UINT32)1 << 0) /* mii mdio interrupt */
760 #define EI_MIB ((LM_UINT32)1 << 1) /* mib interrupt */
761 #define EI_FLOW ((LM_UINT32)1 << 2) /* flow control interrupt */
762
763 /* emac cam data high */
764 #define CD_V ((LM_UINT32)1 << 16) /* valid bit */
765
766 /* emac cam control */
767 #define CC_CE ((LM_UINT32)1 << 0) /* cam enable */
768 #define CC_MS ((LM_UINT32)1 << 1) /* mask select */
769 #define CC_RD ((LM_UINT32)1 << 2) /* read */
770 #define CC_WR ((LM_UINT32)1 << 3) /* write */
771 #define CC_INDEX_MASK 0x3f0000 /* index */
772 #define CC_INDEX_SHIFT 16
773 #define CC_CB ((LM_UINT32)1 << 31) /* cam busy */
774
775 /* emac ethernet control */
776 #define EC_EE ((LM_UINT32)1 << 0) /* emac enable */
777 #define EC_ED ((LM_UINT32)1 << 1) /* emac disable */
778 #define EC_ES ((LM_UINT32)1 << 2) /* emac soft reset */
779 #define EC_EP ((LM_UINT32)1 << 3) /* external phy select */
780
781 /* emac transmit control */
782 #define EXC_FD ((LM_UINT32)1 << 0) /* full duplex */
783 #define EXC_FM ((LM_UINT32)1 << 1) /* flowmode */
784 #define EXC_SB ((LM_UINT32)1 << 2) /* single backoff enable */
785 #define EXC_SS ((LM_UINT32)1 << 3) /* small slottime */
786
787 /* emac mib control */
788 #define EMC_RZ ((LM_UINT32)1 << 0) /* autoclear on read */
789
790 /*
791 * The Ethernet MAC core returns an 8-byte Receive Frame Data Header
792 * with every frame consisting of
793 * 16bits of frame length, followed by
794 * 16bits of EMAC rx descriptor info, followed by 32bits of undefined.
795 */
796 typedef volatile struct {
797 LM_UINT16 len;
798 LM_UINT16 flags;
799 LM_UINT16 pad[12];
800 } bcmenetrxh_t;
801
802 #define RXHDR_LEN 28
803
804 #define RXF_L ((LM_UINT16)1 << 11) /* last buffer in a frame */
805 #define RXF_MISS ((LM_UINT16)1 << 7) /* received due to promisc mode */
806 #define RXF_BRDCAST ((LM_UINT16)1 << 6) /* dest is broadcast address */
807 #define RXF_MULT ((LM_UINT16)1 << 5) /* dest is multicast address */
808 #define RXF_LG ((LM_UINT16)1 << 4) /* frame length > rxmaxlength */
809 #define RXF_NO ((LM_UINT16)1 << 3) /* odd number of nibbles */
810 #define RXF_RXER ((LM_UINT16)1 << 2) /* receive symbol error */
811 #define RXF_CRC ((LM_UINT16)1 << 1) /* crc error */
812 #define RXF_OV ((LM_UINT16)1 << 0) /* fifo overflow */
813
814 #define RXF_ERRORS (RXF_NO | RXF_CRC | RXF_OV)
815
816 /* Sonics side: PCI core and host control registers */
817 typedef struct sbpciregs {
818 LM_UINT32 control; /* PCI control */
819 LM_UINT32 PAD[3];
820 LM_UINT32 arbcontrol; /* PCI arbiter control */
821 LM_UINT32 PAD[3];
822 LM_UINT32 intstatus; /* Interrupt status */
823 LM_UINT32 intmask; /* Interrupt mask */
824 LM_UINT32 sbtopcimailbox; /* Sonics to PCI mailbox */
825 LM_UINT32 PAD[9];
826 LM_UINT32 bcastaddr; /* Sonics broadcast address */
827 LM_UINT32 bcastdata; /* Sonics broadcast data */
828 LM_UINT32 PAD[42];
829 LM_UINT32 sbtopci0; /* Sonics to PCI translation 0 */
830 LM_UINT32 sbtopci1; /* Sonics to PCI translation 1 */
831 LM_UINT32 sbtopci2; /* Sonics to PCI translation 2 */
832 LM_UINT32 PAD[445];
833 LM_UINT16 sprom[36]; /* SPROM shadow Area */
834 LM_UINT32 PAD[46];
835 } sbpciregs_t;
836
837 /* PCI control */
838 #define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
839 #define PCI_RST 0x02 /* Value driven out to pin */
840 #define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
841 #define PCI_CLK 0x08 /* Gate for clock driven out to pin */
842
843 /* PCI arbiter control */
844 #define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
845 #define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
846 #define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
847 #define PCI_PARKID_SHIFT 1
848 #define PCI_PARKID_LAST 0 /* Last requestor */
849 #define PCI_PARKID_4710 1 /* 4710 */
850 #define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
851 #define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
852
853 /* Interrupt status/mask */
854 #define PCI_INTA 0x01 /* PCI INTA# is asserted */
855 #define PCI_INTB 0x02 /* PCI INTB# is asserted */
856 #define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
857 #define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
858 #define PCI_PME 0x10 /* PCI PME# is asserted */
859
860 /* (General) PCI/SB mailbox interrupts, two bits per pci function */
861 #define MAILBOX_F0_0 0x100 /* function 0, int 0 */
862 #define MAILBOX_F0_1 0x200 /* function 0, int 1 */
863 #define MAILBOX_F1_0 0x400 /* function 1, int 0 */
864 #define MAILBOX_F1_1 0x800 /* function 1, int 1 */
865 #define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
866 #define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
867 #define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
868 #define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
869
870 /* Sonics broadcast address */
871 #define BCAST_ADDR_MASK 0xff /* Broadcast register address */
872
873 /* Sonics to PCI translation types */
874 #define SBTOPCI0_MASK 0xfc000000
875 #define SBTOPCI1_MASK 0xfc000000
876 #define SBTOPCI2_MASK 0xc0000000
877 #define SBTOPCI_MEM 0
878 #define SBTOPCI_IO 1
879 #define SBTOPCI_CFG0 2
880 #define SBTOPCI_CFG1 3
881 #define SBTOPCI_PREF 0x4 /* prefetch enable */
882 #define SBTOPCI_BURST 0x8 /* burst enable */
883
884 /* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
885 #define cap_list rsvd_a[0]
886 #define bar0_window dev_dep[0x80 - 0x40]
887 #define bar1_window dev_dep[0x84 - 0x40]
888 #define sprom_control dev_dep[0x88 - 0x40]
889
890 #define PCI_BAR0_WIN 0x80
891 #define PCI_BAR1_WIN 0x84
892 #define PCI_SPROM_CONTROL 0x88
893 #define PCI_BAR1_CONTROL 0x8c
894
895 #define PCI_BAR0_SPROM_OFFSET 4096 /* top 4K of bar0 accesses external sprom */
896
897 /* PCI clock must be active and stable to read SPROM */
898 #ifdef MIPSEL
899 #define pci_host(sprom) ((sprom[0] == 1) && (sprom[2] == 0x4710) && (sprom[8] == 0xf))
900 #else
901 #define pci_host(sprom) ((sprom[1] == 1) && (sprom[3] == 0x4710) && (sprom[9] == 0xf))
902 #endif
903
904 DECLARE_QUEUE_TYPE(LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT);
905 DECLARE_QUEUE_TYPE(LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT);
906
907 typedef struct _LM_PACKET {
908 /* Set in LM. */
909 LM_STATUS PacketStatus;
910
911 /* Set in LM for Rx, in UM for Tx. */
912 LM_UINT32 PacketSize;
913
914 union {
915 /* Send info. */
916 struct {
917 /* Set up by UM. */
918 LM_UINT32 FragCount;
919
920 } Tx;
921
922 /* Receive info. */
923 struct {
924 /* Receive buffer size */
925 LM_UINT32 RxBufferSize;
926
927 /* Virtual and physical address of the receive buffer. */
928 LM_UINT8 *pRxBufferVirt;
929 LM_PHYSICAL_ADDRESS RxBufferPhy;
930
931 } Rx;
932 } u;
933 } LM_PACKET;
934
935 #ifdef BCM_WOL
936
937 #define BCMENET_PMPSIZE 0x80
938 #define BCMENET_PMMSIZE 0x10
939
940 #endif
941
942 typedef struct _LM_DEVICE_BLOCK
943 {
944 /* Memory view. */
945 bcmenetregs_t *pMemView;
946 LM_UINT8 *pMappedMemBase;
947
948 PLM_VOID pPacketDescBase;
949
950 LM_UINT32 RxPacketDescCnt;
951 LM_UINT32 MaxRxPacketDescCnt;
952 LM_UINT32 TxPacketDescCnt;
953 LM_UINT32 MaxTxPacketDescCnt;
954
955 LM_RX_PACKET_Q RxPacketFreeQ;
956 LM_RX_PACKET_Q RxPacketReceivedQ;
957 LM_TX_PACKET_Q TxPacketFreeQ;
958 LM_TX_PACKET_Q TxPacketXmittedQ;
959
960 LM_PACKET *RxPacketArr[DMAMAXRINGSZ / sizeof(dmadd_t)];
961 LM_PACKET *TxPacketArr[DMAMAXRINGSZ / sizeof(dmadd_t)];
962
963 MM_ATOMIC_T SendDescLeft;
964
965 /* Current node address. */
966 LM_UINT8 NodeAddress[6];
967
968 /* The adapter's node address. */
969 LM_UINT8 PermanentNodeAddress[6];
970
971 /* Multicast address list. */
972 LM_UINT32 McEntryCount;
973 LM_UINT8 McTable[LM_MAX_MC_TABLE_SIZE][LM_MC_ENTRY_SIZE];
974
975 LM_UINT16 PciVendorId;
976 LM_UINT16 PciDeviceId;
977 LM_UINT16 PciSubvendorId;
978 LM_UINT16 PciSubsystemId;
979 LM_UINT8 PciRevId;
980 LM_UINT8 Reserved1[3];
981
982 LM_UINT32 corerev;
983 LM_UINT32 coreunit;
984 LM_UINT32 pcirev;
985
986 LM_UINT32 PhyAddr;
987 LM_UINT32 MdcPort;
988
989 dmadd_t *pRxDesc;
990 LM_PHYSICAL_ADDRESS RxDescPhy;
991
992 dmadd_t *pTxDesc;
993 LM_PHYSICAL_ADDRESS TxDescPhy;
994
995 LM_UINT32 ddoffset;
996 LM_UINT32 dataoffset;
997 LM_UINT32 rxoffset;
998
999 LM_UINT32 rxin;
1000 LM_UINT32 rxout;
1001
1002 LM_UINT32 txin;
1003 LM_UINT32 txout;
1004
1005 LM_UINT32 lazyrxfc;
1006 LM_UINT32 lazyrxmult;
1007 LM_UINT32 lazytxfc;
1008 LM_UINT32 lazytxmult;
1009
1010 struct sbmap *sbmap;
1011
1012 LM_LINE_SPEED RequestedLineSpeed;
1013 LM_DUPLEX_MODE RequestedDuplexMode;
1014
1015 LM_LINE_SPEED LineSpeed;
1016 LM_DUPLEX_MODE DuplexMode;
1017
1018 LM_FLOW_CONTROL FlowControlCap;
1019 LM_FLOW_CONTROL FlowControl;
1020
1021 LM_UINT32 Advertising;
1022
1023 LM_UINT32 DisableAutoNeg;
1024
1025 LM_STATUS LinkStatus;
1026
1027 LM_UINT32 ReceiveMask;
1028
1029 LM_BOOL InitDone;
1030
1031 LM_BOOL InReset;
1032
1033 LM_BOOL mibgood;
1034
1035 LM_BOOL ShuttingDown;
1036
1037 LM_BOOL QueueRxPackets;
1038
1039 LM_UINT32 intstatus;
1040 LM_UINT32 intmask;
1041
1042 LM_COUNTER tx_good_octets;
1043 LM_COUNTER tx_good_pkts;
1044 LM_COUNTER tx_octets;
1045 LM_COUNTER tx_pkts;
1046 LM_COUNTER tx_broadcast_pkts;
1047 LM_COUNTER tx_multicast_pkts;
1048 LM_COUNTER tx_len_64;
1049 LM_COUNTER tx_len_65_to_127;
1050 LM_COUNTER tx_len_128_to_255;
1051 LM_COUNTER tx_len_256_to_511;
1052 LM_COUNTER tx_len_512_to_1023;
1053 LM_COUNTER tx_len_1024_to_max;
1054 LM_COUNTER tx_jabber_pkts;
1055 LM_COUNTER tx_oversize_pkts;
1056 LM_COUNTER tx_fragment_pkts;
1057 LM_COUNTER tx_underruns;
1058 LM_COUNTER tx_total_cols;
1059 LM_COUNTER tx_single_cols;
1060 LM_COUNTER tx_multiple_cols;
1061 LM_COUNTER tx_excessive_cols;
1062 LM_COUNTER tx_late_cols;
1063 LM_COUNTER tx_defered;
1064 LM_COUNTER tx_carrier_lost;
1065 LM_COUNTER tx_pause_pkts;
1066
1067 LM_COUNTER rx_good_octets;
1068 LM_COUNTER rx_good_pkts;
1069 LM_COUNTER rx_octets;
1070 LM_COUNTER rx_pkts;
1071 LM_COUNTER rx_broadcast_pkts;
1072 LM_COUNTER rx_multicast_pkts;
1073 LM_COUNTER rx_len_64;
1074 LM_COUNTER rx_len_65_to_127;
1075 LM_COUNTER rx_len_128_to_255;
1076 LM_COUNTER rx_len_256_to_511;
1077 LM_COUNTER rx_len_512_to_1023;
1078 LM_COUNTER rx_len_1024_to_max;
1079 LM_COUNTER rx_jabber_pkts;
1080 LM_COUNTER rx_oversize_pkts;
1081 LM_COUNTER rx_fragment_pkts;
1082 LM_COUNTER rx_missed_pkts;
1083 LM_COUNTER rx_crc_align_errs;
1084 LM_COUNTER rx_undersize;
1085 LM_COUNTER rx_crc_errs;
1086 LM_COUNTER rx_align_errs;
1087 LM_COUNTER rx_symbol_errs;
1088 LM_COUNTER rx_pause_pkts;
1089 LM_COUNTER rx_nonpause_pkts;
1090
1091 #ifdef BCM_WOL
1092 LM_WAKE_UP_MODE WakeUpMode;
1093 #endif
1094 #ifdef BCM_NAPI_RXPOLL
1095 LM_UINT32 RxPoll;
1096 #endif
1097 } LM_DEVICE_BLOCK;
1098
1099 /******************************************************************************/
1100 /* NIC register read/write macros. */
1101 /******************************************************************************/
1102
1103 #define REG_RD(pDevice, OffsetName) \
1104 MM_MEMREADL(&((pDevice)->pMemView->OffsetName))
1105
1106 #define REG_WR(pDevice, OffsetName, Value32) \
1107 (void) MM_MEMWRITEL(&((pDevice)->pMemView->OffsetName), Value32)
1108
1109 #define REG_RD_OFFSET(pDevice, Offset) \
1110 MM_MEMREADL(((LM_UINT8 *) (pDevice)->pMemView + Offset))
1111
1112 #define REG_WR_OFFSET(pDevice, Offset, Value32) \
1113 MM_MEMWRITEL(((LM_UINT8 *) (pDevice)->pMemView + Offset), Value32)
1114
1115 #define REG_OR(pDevice, OffsetName, Value32) \
1116 REG_WR(pDevice, OffsetName, REG_RD(pDevice, OffsetName) | Value32)
1117
1118 #define REG_AND(pDevice, OffsetName, Value32) \
1119 REG_WR(pDevice, OffsetName, REG_RD(pDevice, OffsetName) & Value32)
1120
1121 #define SPINWAIT(exp, us) { \
1122 LM_UINT32 countdown = (us) + 9; \
1123 while ((exp) && (countdown >= 10)) {\
1124 b44_MM_Wait(10); \
1125 countdown -= 10; \
1126 } \
1127 }
1128
1129 #endif /* B44_H */
1130
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