src/add-ons/kernel/drivers/network/ipro1000/if_em.h

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  33
  34 /*$FreeBSD: /repoman/r/ncvs/src/sys/dev/em/if_em.h,v 1.1.2.16 2003/11/18 17:25:52 pdeuskar Exp $*/
  35
  36 #ifndef _EM_H_DEFINED_
  37 #define _EM_H_DEFINED_
  38
  39 #include "if_em_osdep.h"
  40 #include "if_em_hw.h"
  41 #include "if_compat.h"
  42
  43 /* Tunables */
  44
  45 /*
  46  * EM_MAX_TXD: Maximum number of Transmit Descriptors
  47  * Valid Range: 80-256 for 82542 and 82543-based adapters
  48  *              80-4096 for others
  49  * Default Value: 256
  50  *   This value is the number of transmit descriptors allocated by the driver.
  51  *   Increasing this value allows the driver to queue more transmits. Each
  52  *   descriptor is 16 bytes.
  53  */
  54 #define EM_MAX_TXD                      256
  55
  56 /*
  57  * EM_MAX_RXD - Maximum number of receive Descriptors
  58  * Valid Range: 80-256 for 82542 and 82543-based adapters
  59  *              80-4096 for others
  60  * Default Value: 256
  61  *   This value is the number of receive descriptors allocated by the driver.
  62  *   Increasing this value allows the driver to buffer more incoming packets.
  63  *   Each descriptor is 16 bytes.  A receive buffer is also allocated for each
  64  *   descriptor. The maximum MTU size is 16110.
  65  *
  66  */
  67 #define EM_MAX_RXD                      256
  68
  69 /*
  70  * EM_TIDV - Transmit Interrupt Delay Value
  71  * Valid Range: 0-65535 (0=off)
  72  * Default Value: 64
  73  *   This value delays the generation of transmit interrupts in units of
  74  *   1.024 microseconds. Transmit interrupt reduction can improve CPU
  75  *   efficiency if properly tuned for specific network traffic. If the
  76  *   system is reporting dropped transmits, this value may be set too high
  77  *   causing the driver to run out of available transmit descriptors.
  78  */
  79 #define EM_TIDV                         64
  80
  81 /*
  82  * EM_TADV - Transmit Absolute Interrupt Delay Value (Not valid for 82542/82543/82544)
  83  * Valid Range: 0-65535 (0=off)
  84  * Default Value: 64
  85  *   This value, in units of 1.024 microseconds, limits the delay in which a
  86  *   transmit interrupt is generated. Useful only if EM_TIDV is non-zero,
  87  *   this value ensures that an interrupt is generated after the initial
  88  *   packet is sent on the wire within the set amount of time.  Proper tuning,
  89  *   along with EM_TIDV, may improve traffic throughput in specific
  90  *   network conditions.
  91  */
  92 #define EM_TADV                         64
  93
  94 /*
  95  * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer)
  96  * Valid Range: 0-65535 (0=off)
  97  * Default Value: 0
  98  *   This value delays the generation of receive interrupts in units of 1.024
  99  *   microseconds.  Receive interrupt reduction can improve CPU efficiency if
 100  *   properly tuned for specific network traffic. Increasing this value adds
 101  *   extra latency to frame reception and can end up decreasing the throughput
 102  *   of TCP traffic. If the system is reporting dropped receives, this value
 103  *   may be set too high, causing the driver to run out of available receive
 104  *   descriptors.
 105  *
 106  *   CAUTION: When setting EM_RDTR to a value other than 0, adapters
 107  *            may hang (stop transmitting) under certain network conditions.
 108  *            If this occurs a WATCHDOG message is logged in the system event log.
 109  *            In addition, the controller is automatically reset, restoring the
 110  *            network connection. To eliminate the potential for the hang
 111  *            ensure that EM_RDTR is set to 0.
 112  */
 113 #define EM_RDTR                         0
 114
 115 /*
 116  * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
 117  * Valid Range: 0-65535 (0=off)
 118  * Default Value: 64
 119  *   This value, in units of 1.024 microseconds, limits the delay in which a
 120  *   receive interrupt is generated. Useful only if EM_RDTR is non-zero,
 121  *   this value ensures that an interrupt is generated after the initial
 122  *   packet is received within the set amount of time.  Proper tuning,
 123  *   along with EM_RDTR, may improve traffic throughput in specific network
 124  *   conditions.
 125  */
 126 #define EM_RADV                         64
 127
 128
 129 /*
 130  * This parameter controls the maximum no of times the driver will loop
 131  * in the isr.
 132  *           Minimum Value = 1
 133  */
 134 #define EM_MAX_INTR                     3
 135
 136 /*
 137  * Inform the stack about transmit checksum offload capabilities.
 138  */
 139 #define EM_CHECKSUM_FEATURES            (CSUM_TCP | CSUM_UDP)
 140
 141 /*
 142  * This parameter controls the duration of transmit watchdog timer.
 143  */
 144 #define EM_TX_TIMEOUT                   5    /* set to 5 seconds */
 145
 146 /*
 147  * This parameter controls when the driver calls the routine to reclaim
 148  * transmit descriptors.
 149  */
 150 #define EM_TX_CLEANUP_THRESHOLD         EM_MAX_TXD / 8
 151
 152 /*
 153  * This parameter controls whether or not autonegotation is enabled.
 154  *              0 - Disable autonegotiation
 155  *              1 - Enable  autonegotiation
 156  */
 157 #define DO_AUTO_NEG                     1
 158
 159 /*
 160  * This parameter control whether or not the driver will wait for
 161  * autonegotiation to complete.
 162  *              1 - Wait for autonegotiation to complete
 163  *              0 - Don't wait for autonegotiation to complete
 164  */
 165 #define WAIT_FOR_AUTO_NEG_DEFAULT       0
 166
 167 /*
 168  * EM_MASTER_SLAVE is only defined to enable a workaround for a known compatibility issue
 169  * with 82541/82547 devices and some switches.  See the "Known Limitations" section of
 170  * the README file for a complete description and a list of affected switches.
 171  *
 172  *              0 = Hardware default
 173  *              1 = Master mode
 174  *              2 = Slave mode
 175  *              3 = Auto master/slave
 176  */
 177 /* #define EM_MASTER_SLAVE      2 */
 178
 179 /* Tunables -- End */
 180
 181 #define AUTONEG_ADV_DEFAULT             (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \
 182                                          ADVERTISE_100_HALF | ADVERTISE_100_FULL | \
 183                                          ADVERTISE_1000_FULL)
 184
 185 #define EM_VENDOR_ID                    0x8086
 186 #define EM_MMBA                         0x0010 /* Mem base address */
 187 #define EM_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1))
 188
 189 #define EM_JUMBO_PBA                    0x00000028
 190 #define EM_DEFAULT_PBA                  0x00000030
 191 #define EM_SMARTSPEED_DOWNSHIFT         3
 192 #define EM_SMARTSPEED_MAX               15
 193
 194
 195 #define MAX_NUM_MULTICAST_ADDRESSES     128
 196 #define PCI_ANY_ID                      (~0U)
 197 #define ETHER_ALIGN                     2
 198
 199
 200 /* Supported RX Buffer Sizes */
 201 #define EM_RXBUFFER_2048        2048
 202 #define EM_RXBUFFER_4096        4096
 203 #define EM_RXBUFFER_8192        8192
 204 #define EM_RXBUFFER_16384      16384
 205
 206
 207 struct em_buffer {
 208         struct mbuf    *m_head;
 209 };
 210
 211
 212 typedef enum _XSUM_CONTEXT_T {
 213         OFFLOAD_NONE,
 214         OFFLOAD_TCP_IP,
 215         OFFLOAD_UDP_IP
 216 } XSUM_CONTEXT_T;
 217
 218 struct adapter;
 219 struct em_int_delay_info {
 220         struct adapter *adapter;        /* Back-pointer to the adapter struct */
 221         int offset;                     /* Register offset to read/write */
 222         int value;                      /* Current value in usecs */
 223 };
 224
 225 /* For 82544 PCIX  Workaround */
 226 typedef struct _ADDRESS_LENGTH_PAIR
 227 {
 228     u_int64_t   address;
 229     u_int32_t   length;
 230 } ADDRESS_LENGTH_PAIR, *PADDRESS_LENGTH_PAIR;
 231
 232 typedef struct _DESCRIPTOR_PAIR
 233 {
 234     ADDRESS_LENGTH_PAIR descriptor[4];
 235     u_int32_t   elements;
 236 } DESC_ARRAY, *PDESC_ARRAY;
 237
 238 // used by interrupt and event handling thread
 239 enum {
 240         EVENT_LINK_CHANGED              = 0x01,
 241 };
 242
 243 /* Our adapter structure */
 244 struct adapter {
 245         struct arpcom   interface_data;
 246         struct em_hw    hw;
 247
 248         /* FreeBSD operating-system-specific structures */
 249         struct em_osdep osdep;
 250         struct device   *dev;
 251         struct resource *res_memory;
 252         struct resource *res_ioport;
 253         struct resource *res_interrupt;
 254         void            *int_handler_tag;
 255         struct ifmedia  media;
 256         struct callout_handle timer_handle;
 257         struct callout_handle tx_fifo_timer_handle;
 258         int             io_rid;
 259         u_int8_t        unit;
 260
 261         /* Event processing thread, to move link status change out of the interrupt */
 262         thread_id               event_thread;
 263         sem_id                  event_sem;
 264         volatile int32  event_flags;
 265
 266         /* Info about the board itself */
 267         u_int32_t       part_num;
 268         u_int8_t        link_active;
 269         u_int16_t       link_speed;
 270         u_int16_t       link_duplex;
 271         u_int32_t       smartspeed;
 272         struct em_int_delay_info tx_int_delay;
 273         struct em_int_delay_info tx_abs_int_delay;
 274         struct em_int_delay_info rx_int_delay;
 275         struct em_int_delay_info rx_abs_int_delay;
 276
 277         XSUM_CONTEXT_T  active_checksum_context;
 278
 279         /*
 280          * Transmit definitions
 281          *
 282          * We have an array of num_tx_desc descriptors (handled
 283          * by the controller) paired with an array of tx_buffers
 284          * (at tx_buffer_area).
 285          * The index of the next available descriptor is next_avail_tx_desc.
 286          * The number of remaining tx_desc is num_tx_desc_avail.
 287          */
 288         struct em_tx_desc *tx_desc_base;
 289         u_int32_t          next_avail_tx_desc;
 290         u_int32_t          oldest_used_tx_desc;
 291         volatile u_int16_t num_tx_desc_avail;
 292         u_int16_t          num_tx_desc;
 293         u_int32_t          txd_cmd;
 294         struct em_buffer   *tx_buffer_area;
 295
 296         /*
 297          * Receive definitions
 298          *
 299          * we have an array of num_rx_desc rx_desc (handled by the
 300          * controller), and paired with an array of rx_buffers
 301          * (at rx_buffer_area).
 302          * The next pair to check on receive is at offset next_rx_desc_to_check
 303          */
 304         struct em_rx_desc *rx_desc_base;
 305         u_int32_t          next_rx_desc_to_check;
 306         u_int16_t          num_rx_desc;
 307         u_int32_t          rx_buffer_len;
 308         struct em_buffer   *rx_buffer_area;
 309
 310         /* Jumbo frame */
 311         struct mbuf        *fmp;
 312         struct mbuf        *lmp;
 313
 314         u_int16_t          tx_fifo_head;
 315
 316         struct sysctl_ctx_list sysctl_ctx;
 317         struct sysctl_oid *sysctl_tree;
 318
 319         /* Misc stats maintained by the driver */
 320         unsigned long   dropped_pkts;
 321         unsigned long   mbuf_alloc_failed;
 322         unsigned long   mbuf_cluster_failed;
 323         unsigned long   no_tx_desc_avail1;
 324         unsigned long   no_tx_desc_avail2;
 325         u_int64_t       tx_fifo_reset;
 326         u_int64_t       tx_fifo_wrk;
 327
 328         /* For 82544 PCIX Workaround */
 329         boolean_t pcix_82544;
 330         boolean_t in_detach;
 331
 332 #if DEBUG_DISPLAY_STATS
 333         unsigned long   no_pkts_avail;
 334         unsigned long   clean_tx_interrupts;
 335 #endif
 336
 337         struct em_hw_stats stats;
 338 };
 339
 340 #endif                                                  /* _EM_H_DEFINED_ */