src/add-ons/kernel/drivers/network/pegasus/if_auereg.h

   1 /*
   2  * Pegasus BeOS Driver
   3  *
   4  * Copyright 2006, Haiku, Inc. All Rights Reserved.
   5  * Distributed under the terms of the MIT License.
   6  *
   7  * Authors:
   8  *              Jérôme Duval
   9  */
  10
  11 /*-
  12  * Copyright (c) 1997, 1998, 1999
  13  *      Bill Paul <wpaul@ee.columbia.edu>.  All rights reserved.
  14  *
  15  * Redistribution and use in source and binary forms, with or without
  16  * modification, are permitted provided that the following conditions
  17  * are met:
  18  * 1. Redistributions of source code must retain the above copyright
  19  *    notice, this list of conditions and the following disclaimer.
  20  * 2. Redistributions in binary form must reproduce the above copyright
  21  *    notice, this list of conditions and the following disclaimer in the
  22  *    documentation and/or other materials provided with the distribution.
  23  * 3. All advertising materials mentioning features or use of this software
  24  *    must display the following acknowledgement:
  25  *      This product includes software developed by Bill Paul.
  26  * 4. Neither the name of the author nor the names of any co-contributors
  27  *    may be used to endorse or promote products derived from this software
  28  *    without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  31  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  32  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  33  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  34  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  35  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  36  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  37  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  38  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  39  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  40  * THE POSSIBILITY OF SUCH DAMAGE.
  41  *
  42  * $FreeBSD: /repoman/r/ncvs/src/sys/dev/usb/if_auereg.h,v 1.22 2005/06/10 16:49:15 brooks Exp $
  43  */
  44
  45 /*
  46  * Register definitions for ADMtek Pegasus AN986 USB to Ethernet
  47  * chip. The Pegasus uses a total of four USB endpoints: the control
  48  * endpoint (0), a bulk read endpoint for receiving packets (1),
  49  * a bulk write endpoint for sending packets (2) and an interrupt
  50  * endpoint for passing RX and TX status (3). Endpoint 0 is used
  51  * to read and write the ethernet module's registers. All registers
  52  * are 8 bits wide.
  53  *
  54  * Packet transfer is done in 64 byte chunks. The last chunk in a
  55  * transfer is denoted by having a length less that 64 bytes. For
  56  * the RX case, the data includes an optional RX status word.
  57  */
  58
  59 #define AUE_UR_READREG          0xF0
  60 #define AUE_UR_WRITEREG         0xF1
  61
  62 #define AUE_CONFIG_NO           1
  63 #define AUE_IFACE_IDX           0
  64
  65 /*
  66  * Note that while the ADMtek technically has four
  67  * endpoints, the control endpoint (endpoint 0) is
  68  * regarded as special by the USB code and drivers
  69  * don't have direct access to it. (We access it
  70  * using usbd_do_request() when reading/writing
  71  * registers.) Consequently, our endpoint indexes
  72  * don't match those in the ADMtek Pegasus manual:
  73  * we consider the RX data endpoint to be index 0
  74  * and work up from there.
  75  */
  76 #define AUE_ENDPT_RX            0x0
  77 #define AUE_ENDPT_TX            0x1
  78 #define AUE_ENDPT_INTR          0x2
  79 #define AUE_ENDPT_MAX           0x3
  80
  81 #define AUE_INTR_PKTLEN         0x8
  82
  83 #define AUE_CTL0                0x00
  84 #define AUE_CTL1                0x01
  85 #define AUE_CTL2                0x02
  86 #define AUE_MAR0                0x08
  87 #define AUE_MAR1                0x09
  88 #define AUE_MAR2                0x0A
  89 #define AUE_MAR3                0x0B
  90 #define AUE_MAR4                0x0C
  91 #define AUE_MAR5                0x0D
  92 #define AUE_MAR6                0x0E
  93 #define AUE_MAR7                0x0F
  94 #define AUE_MAR                 AUE_MAR0
  95 #define AUE_PAR0                0x10
  96 #define AUE_PAR1                0x11
  97 #define AUE_PAR2                0x12
  98 #define AUE_PAR3                0x13
  99 #define AUE_PAR4                0x14
 100 #define AUE_PAR5                0x15
 101 #define AUE_PAR                 AUE_PAR0
 102 #define AUE_PAUSE0              0x18
 103 #define AUE_PAUSE1              0x19
 104 #define AUE_PAUSE               AUE_PAUSE0
 105 #define AUE_RX_FLOWCTL_CNT      0x1A
 106 #define AUE_RX_FLOWCTL_FIFO     0x1B
 107 #define AUE_REG_1D              0x1D
 108 #define AUE_EE_REG              0x20
 109 #define AUE_EE_DATA0            0x21
 110 #define AUE_EE_DATA1            0x22
 111 #define AUE_EE_DATA             AUE_EE_DATA0
 112 #define AUE_EE_CTL              0x23
 113 #define AUE_PHY_ADDR            0x25
 114 #define AUE_PHY_DATA0           0x26
 115 #define AUE_PHY_DATA1           0x27
 116 #define AUE_PHY_DATA            AUE_PHY_DATA0
 117 #define AUE_PHY_CTL             0x28
 118 #define AUE_USB_STS             0x2A
 119 #define AUE_TXSTAT0             0x2B
 120 #define AUE_TXSTAT1             0x2C
 121 #define AUE_TXSTAT              AUE_TXSTAT0
 122 #define AUE_RXSTAT              0x2D
 123 #define AUE_PKTLOST0            0x2E
 124 #define AUE_PKTLOST1            0x2F
 125 #define AUE_PKTLOST             AUE_PKTLOST0
 126
 127 #define AUE_REG_7B              0x7B
 128 #define AUE_GPIO0               0x7E
 129 #define AUE_GPIO1               0x7F
 130 #define AUE_REG_81              0x81
 131
 132 #define AUE_CTL0_INCLUDE_RXCRC  0x01
 133 #define AUE_CTL0_ALLMULTI       0x02
 134 #define AUE_CTL0_STOP_BACKOFF   0x04
 135 #define AUE_CTL0_RXSTAT_APPEND  0x08
 136 #define AUE_CTL0_WAKEON_ENB     0x10
 137 #define AUE_CTL0_RXPAUSE_ENB    0x20
 138 #define AUE_CTL0_RX_ENB         0x40
 139 #define AUE_CTL0_TX_ENB         0x80
 140
 141 #define AUE_CTL1_HOMELAN        0x04
 142 #define AUE_CTL1_RESETMAC       0x08
 143 #define AUE_CTL1_SPEEDSEL       0x10    /* 0 = 10mbps, 1 = 100mbps */
 144 #define AUE_CTL1_DUPLEX         0x20    /* 0 = half, 1 = full */
 145 #define AUE_CTL1_DELAYHOME      0x40
 146
 147 #define AUE_CTL2_EP3_CLR        0x01    /* reading EP3 clrs status regs */
 148 #define AUE_CTL2_RX_BADFRAMES   0x02
 149 #define AUE_CTL2_RX_PROMISC     0x04
 150 #define AUE_CTL2_LOOPBACK       0x08
 151 #define AUE_CTL2_EEPROMWR_ENB   0x10
 152 #define AUE_CTL2_EEPROM_LOAD    0x20
 153
 154 #define AUE_EECTL_WRITE         0x01
 155 #define AUE_EECTL_READ          0x02
 156 #define AUE_EECTL_DONE          0x04
 157
 158 #define AUE_PHYCTL_PHYREG       0x1F
 159 #define AUE_PHYCTL_WRITE        0x20
 160 #define AUE_PHYCTL_READ         0x40
 161 #define AUE_PHYCTL_DONE         0x80
 162
 163 #define AUE_USBSTS_SUSPEND      0x01
 164 #define AUE_USBSTS_RESUME       0x02
 165
 166 #define AUE_TXSTAT0_JABTIMO     0x04
 167 #define AUE_TXSTAT0_CARLOSS     0x08
 168 #define AUE_TXSTAT0_NOCARRIER   0x10
 169 #define AUE_TXSTAT0_LATECOLL    0x20
 170 #define AUE_TXSTAT0_EXCESSCOLL  0x40
 171 #define AUE_TXSTAT0_UNDERRUN    0x80
 172
 173 #define AUE_TXSTAT1_PKTCNT      0x0F
 174 #define AUE_TXSTAT1_FIFO_EMPTY  0x40
 175 #define AUE_TXSTAT1_FIFO_FULL   0x80
 176
 177 #define AUE_RXSTAT_OVERRUN      0x01
 178 #define AUE_RXSTAT_PAUSE        0x02
 179
 180 #define AUE_GPIO_IN0            0x01
 181 #define AUE_GPIO_OUT0           0x02
 182 #define AUE_GPIO_SEL0           0x04
 183 #define AUE_GPIO_IN1            0x08
 184 #define AUE_GPIO_OUT1           0x10
 185 #define AUE_GPIO_SEL1           0x20
 186
 187 struct aue_intrpkt {
 188         u_int8_t                aue_txstat0;
 189         u_int8_t                aue_txstat1;
 190         u_int8_t                aue_rxstat;
 191         u_int8_t                aue_rxlostpkt0;
 192         u_int8_t                aue_rxlostpkt1;
 193         u_int8_t                aue_wakeupstat;
 194         u_int8_t                aue_rsvd;
 195 };
 196
 197 struct aue_rxpkt {
 198         u_int16_t               aue_pktlen;
 199         u_int8_t                aue_rxstat;
 200 };
 201
 202 #define AUE_RXSTAT_MCAST        0x01
 203 #define AUE_RXSTAT_GIANT        0x02
 204 #define AUE_RXSTAT_RUNT         0x04
 205 #define AUE_RXSTAT_CRCERR       0x08
 206 #define AUE_RXSTAT_DRIBBLE      0x10
 207 #define AUE_RXSTAT_MASK         0x1E
 208
 209 #define AUE_INC(x, y)           (x) = (x + 1) % y
 210
 211 #if 0
 212 #define AUE_LOCK(_sc)           mtx_lock(&(_sc)->aue_mtx)
 213 #define AUE_UNLOCK(_sc)         mtx_unlock(&(_sc)->aue_mtx)
 214 #else
 215 #define AUE_LOCK(_sc)
 216 #define AUE_UNLOCK(_sc)
 217 #endif
 218
 219 #define AUE_TIMEOUT             1000
 220 #define AUE_MIN_FRAMELEN        60
 221 #define AUE_TX_TIMEOUT          10000 /* ms */
 222 #define AUE_INTR_INTERVAL       100 /* ms */
 223 #define AUE_BUFSZ               1536
 224 #define ETHER_ALIGN             2
 225
 226
 227 /***************************** Media Independent Interface *****************************/
 228
 229
 230 enum MII_address {
 231         // standard registers
 232         MII_CONTROL             = 0x00,
 233         MII_STATUS              = 0x01,
 234         MII_PHY_ID0             = 0x02,
 235         MII_PHY_ID1             = 0x03,
 236         MII_AUTONEG_ADV                         = 0x04,
 237         MII_AUTONEG_LINK_PARTNER        = 0x05,
 238         MII_AUTONEG_EXT                         = 0x06,
 239 };
 240
 241 enum MII_control {
 242         MII_CONTROL_RESET                       = 0x8000,
 243         MII_CONTROL_RESET_AUTONEG       = 0x0200,
 244         MII_CONTROL_AUTO                        = 0x1000,
 245         MII_CONTROL_FULL_DUPLEX         = 0x0100,
 246         MII_CONTROL_ISOLATE                     = 0x0400
 247 };
 248
 249 enum SiS900_MII_commands {
 250         MII_CMD_READ            = 0x6000,
 251         MII_CMD_WRITE           = 0x5002,
 252
 253         MII_PHY_SHIFT           = 7,
 254         MII_REG_SHIFT           = 2,
 255 };
 256
 257 enum MII_status_bits {
 258         MII_STATUS_EXT                  = 0x0001,
 259         MII_STATUS_JAB                  = 0x0002,
 260         MII_STATUS_LINK                 = 0x0004,
 261         MII_STATUS_CAN_AUTO             = 0x0008,
 262         MII_STATUS_FAULT                = 0x0010,
 263         MII_STATUS_AUTO_DONE    = 0x0020,
 264         MII_STATUS_CAN_T                = 0x0800,
 265         MII_STATUS_CAN_T_FDX    = 0x1000,
 266         MII_STATUS_CAN_TX               = 0x2000,
 267         MII_STATUS_CAN_TX_FDX   = 0x4000,
 268         MII_STATUS_CAN_T4               = 0x8000
 269 };
 270
 271
 272 enum MII_link_status {
 273         MII_LINK_FAIL                   = 0x4000,
 274         MII_LINK_100_MBIT               = 0x0080,
 275         MII_LINK_FULL_DUPLEX    = 0x0040
 276 };