3 ** Naive RealTek 8139C driver for the DC Broadband Adapter. Some
4 ** assistance on names of things from the NetBSD-DC sources.
14 /* RTL8139C register definitions */
15 #define RT_IDR0 0x00 /* Mac address */
16 #define RT_MAR0 0x08 /* Multicast filter */
17 #define RT_TXSTATUS0 0x10 /* Transmit status (4 32bit regs) */
18 #define RT_TXADDR0 0x20 /* Tx descriptors (also 4 32bit) */
19 #define RT_RXBUF 0x30 /* Receive buffer start address */
20 #define RT_RXEARLYCNT 0x34 /* Early Rx byte count */
21 #define RT_RXEARLYSTATUS 0x36 /* Early Rx status */
22 #define RT_CHIPCMD 0x37 /* Command register */
23 #define RT_RXBUFTAIL 0x38 /* Current address of packet read (queue tail) */
24 #define RT_RXBUFHEAD 0x3A /* Current buffer address (queue head) */
25 #define RT_INTRMASK 0x3C /* Interrupt mask */
26 #define RT_INTRSTATUS 0x3E /* Interrupt status */
27 #define RT_TXCONFIG 0x40 /* Tx config */
28 #define RT_RXCONFIG 0x44 /* Rx config */
29 #define RT_TIMER 0x48 /* A general purpose counter */
30 #define RT_RXMISSED 0x4C /* 24 bits valid, write clears */
31 #define RT_CFG9346 0x50 /* 93C46 command register */
32 #define RT_CONFIG0 0x51 /* Configuration reg 0 */
33 #define RT_CONFIG1 0x52 /* Configuration reg 1 */
34 #define RT_TIMERINT 0x54 /* Timer interrupt register (32 bits) */
35 #define RT_MEDIASTATUS 0x58 /* Media status register */
36 #define RT_CONFIG3 0x59 /* Config register 3 */
37 #define RT_CONFIG4 0x5A /* Config register 4 */
38 #define RT_MULTIINTR 0x5C /* Multiple interrupt select */
39 #define RT_MII_TSAD 0x60 /* Transmit status of all descriptors (16 bits) */
40 #define RT_MII_BMCR 0x62 /* Basic Mode Control Register (16 bits) */
41 #define RT_MII_BMSR 0x64 /* Basic Mode Status Register (16 bits) */
42 #define RT_AS_ADVERT 0x66 /* Auto-negotiation advertisement reg (16 bits) */
43 #define RT_AS_LPAR 0x68 /* Auto-negotiation link partner reg (16 bits) */
44 #define RT_AS_EXPANSION 0x6A /* Auto-negotiation expansion reg (16 bits) */
46 /* RTL8193C command bits; or these together and write teh resulting value
47 into CHIPCMD to execute it. */
48 #define RT_CMD_RESET 0x10
49 #define RT_CMD_RX_ENABLE 0x08
50 #define RT_CMD_TX_ENABLE 0x04
51 #define RT_CMD_RX_BUF_EMPTY 0x01
53 /* RTL8139C interrupt status bits */
54 #define RT_INT_PCIERR 0x8000 /* PCI Bus error */
55 #define RT_INT_TIMEOUT 0x4000 /* Set when TCTR reaches TimerInt value */
56 #define RT_INT_RXFIFO_OVERFLOW 0x0040 /* Rx FIFO overflow */
57 #define RT_INT_RXFIFO_UNDERRUN 0x0020 /* Packet underrun / link change */
58 #define RT_INT_RXBUF_OVERFLOW 0x0010 /* Rx BUFFER overflow */
59 #define RT_INT_TX_ERR 0x0008
60 #define RT_INT_TX_OK 0x0004
61 #define RT_INT_RX_ERR 0x0002
62 #define RT_INT_RX_OK 0x0001
64 /* RTL8139C transmit status bits */
65 #define RT_TX_CARRIER_LOST 0x80000000 /* Carrier sense lost */
66 #define RT_TX_ABORTED 0x40000000 /* Transmission aborted */
67 #define RT_TX_OUT_OF_WINDOW 0x20000000 /* Out of window collision */
68 #define RT_TX_STATUS_OK 0x00008000 /* Status ok: a good packet was transmitted */
69 #define RT_TX_UNDERRUN 0x00004000 /* Transmit FIFO underrun */
70 #define RT_TX_HOST_OWNS 0x00002000 /* Set to 1 when DMA operation is completed */
71 #define RT_TX_SIZE_MASK 0x00001fff /* Descriptor size mask */
73 /* RTL8139C receive status bits */
74 #define RT_RX_MULTICAST 0x00008000 /* Multicast packet */
75 #define RT_RX_PAM 0x00004000 /* Physical address matched */
76 #define RT_RX_BROADCAST 0x00002000 /* Broadcast address matched */
77 #define RT_RX_BAD_SYMBOL 0x00000020 /* Invalid symbol in 100TX packet */
78 #define RT_RX_RUNT 0x00000010 /* Packet size is <64 bytes */
79 #define RT_RX_TOO_LONG 0x00000008 /* Packet size is >4K bytes */
80 #define RT_RX_CRC_ERR 0x00000004 /* CRC error */
81 #define RT_RX_FRAME_ALIGN 0x00000002 /* Frame alignment error */
82 #define RT_RX_STATUS_OK 0x00000001 /* Status ok: a good packet was received */
