vfs: check userland buffers before reading them.
[haiku.git] / src / add-ons / accelerants / radeon / palette.c
blob5aab89affee773b73043bded167b712b05969f01
1 /*
2 Copyright (c) 2002-2004, Thomas Kurschel
5 Part of Radeon accelerant
7 Palette handling. Though it's very often referred to as
8 being part of the DAC, this is not really true as palette
9 lookup is part of the CRTC unit (else it wouldn't work for
10 digital output like DVI)
14 #include "GlobalData.h"
15 #include "dac_regs.h"
16 #include "mmio.h"
17 #include "CP.h"
18 #include "generic.h"
20 // set standard colour palette (needed for non-palette modes)
21 void Radeon_InitPalette(
22 accelerator_info *ai, int crtc_idx )
24 int i;
26 if ( ai->si->acc_dma ) {
27 START_IB();
29 WRITE_IB_REG( RADEON_DAC_CNTL2,
30 (crtc_idx == 0 ? 0 : RADEON_DAC2_PALETTE_ACC_CTL) |
31 (ai->si->dac_cntl2 & ~RADEON_DAC2_PALETTE_ACC_CTL) );
33 WRITE_IB_REG( RADEON_PALETTE_INDEX, 0 );
35 for( i = 0; i < 256; ++i )
36 WRITE_IB_REG( RADEON_PALETTE_DATA, (i << 16) | (i << 8) | i );
38 SUBMIT_IB();
39 } else {
40 Radeon_WaitForFifo ( ai , 1 );
41 OUTREG( ai->regs, RADEON_DAC_CNTL2,
42 (crtc_idx == 0 ? 0 : RADEON_DAC2_PALETTE_ACC_CTL) |
43 (ai->si->dac_cntl2 & ~RADEON_DAC2_PALETTE_ACC_CTL) );
45 OUTREG( ai->regs, RADEON_PALETTE_INDEX, 0 );
46 for( i = 0; i < 256; ++i ) {
47 Radeon_WaitForFifo ( ai , 1 ); // TODO FIXME good god this is gonna be slow...
48 OUTREG( ai->regs, RADEON_PALETTE_DATA, (i << 16) | (i << 8) | i );
53 static void setPalette(
54 accelerator_info *ai, int crtc_idx,
55 uint count, uint8 first, uint8 *color_data );
57 // public function: set colour palette
58 void SET_INDEXED_COLORS(
59 uint count, uint8 first, uint8 *color_data, uint32 flags )
61 virtual_card *vc = ai->vc;
63 (void)flags;
65 SHOW_FLOW( 3, "first=%d, count=%d", first, count );
67 if( vc->mode.space != B_CMAP8 ) {
68 SHOW_ERROR0( 2, "Tried to set palette in non-palette mode" );
69 return;
72 if( vc->used_crtc[0] )
73 setPalette( ai, 0, count, first, color_data );
74 if( vc->used_crtc[1] )
75 setPalette( ai, 1, count, first, color_data );
79 // set palette of one DAC
80 static void setPalette(
81 accelerator_info *ai, int crtc_idx,
82 uint count, uint8 first, uint8 *color_data )
84 uint i;
86 if ( ai->si->acc_dma ) {
87 START_IB();
89 WRITE_IB_REG( RADEON_DAC_CNTL2,
90 (crtc_idx == 0 ? 0 : RADEON_DAC2_PALETTE_ACC_CTL) |
91 (ai->si->dac_cntl2 & ~RADEON_DAC2_PALETTE_ACC_CTL) );
93 WRITE_IB_REG( RADEON_PALETTE_INDEX, first );
95 for( i = 0; i < count; ++i, color_data += 3 )
96 WRITE_IB_REG( RADEON_PALETTE_DATA,
97 ((uint32)color_data[0] << 16) |
98 ((uint32)color_data[1] << 8) |
99 color_data[2] );
101 SUBMIT_IB();
102 } else {
103 Radeon_WaitForFifo ( ai , 1 );
104 OUTREG( ai->regs, RADEON_DAC_CNTL2,
105 (crtc_idx == 0 ? 0 : RADEON_DAC2_PALETTE_ACC_CTL) |
106 (ai->si->dac_cntl2 & ~RADEON_DAC2_PALETTE_ACC_CTL) );
108 OUTREG( ai->regs, RADEON_PALETTE_INDEX, first );
109 for( i = 0; i < count; ++i, color_data += 3 ) {
110 Radeon_WaitForFifo ( ai , 1 ); // TODO FIXME good god this is gonna be slow...
111 OUTREG( ai->regs, RADEON_PALETTE_DATA,
112 ((uint32)color_data[0] << 16) |
113 ((uint32)color_data[1] << 8) |
114 color_data[2] );