src/add-ons/accelerants/radeon_hd/accelerant.h

   1 /*
   2  * Copyright 2006-2011, Haiku, Inc. All Rights Reserved.
   3  * Distributed under the terms of the MIT License.
   4  *
   5  * Authors:
   6  *              Axel Dörfler, axeld@pinc-software.de
   7  *              Alexander von Gluck, kallisti5@unixzen.com
   8  */
   9 #ifndef RADEON_HD_ACCELERANT_H
  10 #define RADEON_HD_ACCELERANT_H
  11
  12
  13 #include <ByteOrder.h>
  14 #include <edid.h>
  15
  16 #include "atom.h"
  17 #include "dp.h"
  18 #include "encoder.h"
  19 #include "mode.h"
  20 #include "pll.h"
  21 #include "radeon_hd.h"
  22 #include "ringqueue.h"
  23
  24
  25 #define MAX_DISPLAY 2
  26         // Maximum displays (more then two requires AtomBIOS)
  27 #define MAX_GPIO_PINS   64
  28         // Maximum possible GPIO pins in gGPIOInfo
  29
  30 struct gpu_state {
  31         uint32 d1vgaControl;
  32         uint32 d2vgaControl;
  33         uint32 vgaRenderControl;
  34         uint32 vgaHdpControl;
  35         uint32 d1crtcControl;
  36         uint32 d2crtcControl;
  37 };
  38
  39
  40 struct fb_info {
  41         bool            valid;
  42         uint64          vramStart;
  43         uint64          vramEnd;
  44         uint64          vramSize;
  45
  46         uint64          gartStart;
  47         uint64          gartEnd;
  48         uint64          gartSize;
  49         uint64          agpBase;
  50 };
  51
  52
  53 struct accelerant_info {
  54         vuint8*                 regs;
  55         area_id                 regs_area;
  56
  57         radeon_shared_info* shared_info;
  58         area_id                 shared_info_area;
  59
  60         display_mode*   mode_list;              // cloned list of standard display modes
  61         area_id                 mode_list_area;
  62
  63         uint8*                  rom;
  64         area_id                 rom_area;
  65
  66         edid1_info              edid_info;
  67         bool                    has_edid;
  68
  69         int                             device;
  70         bool                    is_clone;
  71
  72         struct fb_info  fb;     // used for frame buffer info within MC
  73
  74         volatile uint32 dpms_mode;              // current driver dpms mode
  75
  76         uint32                  maximumPixelClock;
  77         uint32                  displayClockFrequency;
  78         uint32                  dpExternalClock;
  79
  80         uint32                  lvdsSpreadSpectrumID;
  81
  82         RingQueue*              ringQueue[RADEON_QUEUE_MAX]; // Ring buffer command processor
  83 };
  84
  85
  86 struct register_info {
  87         uint16  crtcOffset;
  88         uint16  vgaControl;
  89         uint16  grphEnable;
  90         uint16  grphControl;
  91         uint16  grphSwapControl;
  92         uint16  grphPrimarySurfaceAddr;
  93         uint16  grphSecondarySurfaceAddr;
  94         uint16  grphPrimarySurfaceAddrHigh;
  95         uint16  grphSecondarySurfaceAddrHigh;
  96         uint16  grphPitch;
  97         uint16  grphSurfaceOffsetX;
  98         uint16  grphSurfaceOffsetY;
  99         uint16  grphXStart;
 100         uint16  grphYStart;
 101         uint16  grphXEnd;
 102         uint16  grphYEnd;
 103         uint16  modeDesktopHeight;
 104         uint16  modeDataFormat;
 105         uint16  viewportStart;
 106         uint16  viewportSize;
 107 };
 108
 109
 110 typedef struct {
 111         bool    valid;
 112
 113         uint32  hwPin;  // GPIO hardware pin on GPU
 114         uint32  hwReg;  // GPIO register
 115         uint32  hwMask; // GPIO pin mask
 116
 117         struct {
 118                 bool valid;
 119                 bool hwCapable; // can do hw assisted i2c
 120                 uint32 sclMaskReg;
 121                 uint32 sdaMaskReg;
 122                 uint32 sclMask;
 123                 uint32 sdaMask;
 124
 125                 uint32 sclEnReg;
 126                 uint32 sdaEnReg;
 127                 uint32 sclEnMask;
 128                 uint32 sdaEnMask;
 129
 130                 uint32 sclYReg;
 131                 uint32 sdaYReg;
 132                 uint32 sclYMask;
 133                 uint32 sdaYMask;
 134
 135                 uint32 sclAReg;
 136                 uint32 sdaAReg;
 137                 uint32 sclAMask;
 138                 uint32 sdaAMask;
 139         } i2c;
 140 } gpio_info;
 141
 142
 143 struct encoder_info {
 144         bool            valid;
 145         uint16          objectID;
 146         uint32          type;
 147         uint32          capabilities;
 148         uint32          linkEnumeration; // ex. linkb == GRAPH_OBJECT_ENUM_ID2
 149         bool            isExternal;
 150         bool            isDPBridge;
 151         struct pll_info pll;
 152 };
 153
 154
 155 typedef struct {
 156         bool            valid;
 157         uint16          objectID;
 158         uint32          type;
 159         uint32          flags;
 160         uint32          lvdsFlags;
 161         uint16          i2cPinIndex; // id of gpio pin for i2c communications
 162         uint16          hpdPinIndex; // id of gpio pin for hotplug detection
 163         struct encoder_info encoder;
 164         struct encoder_info encoderExternal;
 165         dp_info         dpInfo;
 166 } connector_info;
 167
 168
 169 typedef struct {
 170         bool                    attached;
 171         bool                    powered;
 172         uint32                  connectorIndex; // matches connector id in connector_info
 173         register_info*  regs;
 174         bool                    foundRanges;
 175         uint32                  vfreqMax;
 176         uint32                  vfreqMin;
 177         uint32                  hfreqMax;
 178         uint32                  hfreqMin;
 179         edid1_info              edidData;
 180         display_mode    preferredMode;
 181         display_mode    currentMode;
 182 } display_info;
 183
 184
 185 // register MMIO modes
 186 #define OUT 0x1 // Direct MMIO calls
 187 #define CRT 0x2 // Crt controller calls
 188 #define VGA 0x3 // Vga calls
 189 #define PLL 0x4 // PLL calls
 190 #define MC      0x5 // Memory controller calls
 191
 192
 193 extern accelerant_info* gInfo;
 194 extern atom_context* gAtomContext;
 195 extern display_info* gDisplay[MAX_DISPLAY];
 196 extern connector_info* gConnector[ATOM_MAX_SUPPORTED_DEVICE];
 197 extern gpio_info* gGPIOInfo[MAX_GPIO_PINS];
 198
 199
 200 // register access
 201
 202 inline uint32
 203 _read32(uint32 offset)
 204 {
 205         return *(volatile uint32*)(gInfo->regs + offset);
 206 }
 207
 208
 209 inline void
 210 _write32(uint32 offset, uint32 value)
 211 {
 212         *(volatile uint32 *)(gInfo->regs + offset) = value;
 213 }
 214
 215
 216 // AtomBIOS cail register calls (are *4... no clue why)
 217 inline uint32
 218 Read32Cail(uint32 offset)
 219 {
 220         return _read32(offset * 4);
 221 }
 222
 223
 224 inline void
 225 Write32Cail(uint32 offset, uint32 value)
 226 {
 227         _write32(offset * 4, value);
 228 }
 229
 230
 231 inline uint32
 232 Read32(uint32 subsystem, uint32 offset)
 233 {
 234         switch (subsystem) {
 235                 default:
 236                 case OUT:
 237                 case VGA:
 238                 case CRT:
 239                 case PLL:
 240                         return _read32(offset);
 241                 case MC:
 242                         return _read32(offset);
 243         };
 244 }
 245
 246
 247 inline void
 248 Write32(uint32 subsystem, uint32 offset, uint32 value)
 249 {
 250         switch (subsystem) {
 251                 default:
 252                 case OUT:
 253                 case VGA:
 254                 case CRT:
 255                 case PLL:
 256                         _write32(offset, value);
 257                         return;
 258                 case MC:
 259                         _write32(offset, value);
 260                         return;
 261         };
 262 }
 263
 264
 265 inline void
 266 Write32Mask(uint32 subsystem, uint32 offset, uint32 value, uint32 mask)
 267 {
 268         uint32 temp;
 269         switch (subsystem) {
 270                 default:
 271                 case OUT:
 272                 case VGA:
 273                 case MC:
 274                         temp = _read32(offset);
 275                         break;
 276                 case CRT:
 277                         temp = _read32(offset);
 278                         break;
 279                 case PLL:
 280                         temp = _read32(offset);
 281                         //temp = _read32PLL(offset);
 282                         break;
 283         };
 284
 285         // only effect mask
 286         temp &= ~mask;
 287         temp |= value & mask;
 288
 289         switch (subsystem) {
 290                 default:
 291                 case OUT:
 292                 case VGA:
 293                 case MC:
 294                         _write32(offset, temp);
 295                         return;
 296                 case CRT:
 297                         _write32(offset, temp);
 298                         return;
 299                 case PLL:
 300                         _write32(offset, temp);
 301                         //_write32PLL(offset, temp);
 302                         return;
 303         };
 304 }
 305
 306
 307 #endif  /* RADEON_HD_ACCELERANT_H */