src/add-ons/accelerants/radeon_hd/pll.h

   1 /*
   2  * Copyright 2006-2011, Haiku, Inc. All Rights Reserved.
   3  * Distributed under the terms of the MIT License.
   4  *
   5  * Authors:
   6  *      Alexander von Gluck, kallisti5@unixzen.com
   7  */
   8 #ifndef RADEON_HD_PLL_H
   9 #define RADEON_HD_PLL_H
  10
  11
  12 #include <Accelerant.h>
  13 #include <SupportDefs.h>
  14
  15
  16 #define MAX_TOLERANCE 10
  17
  18 #define PLL_MIN_DEFAULT 16000
  19 #define PLL_MAX_DEFAULT 400000
  20 #define PLL_REFERENCE_DEFAULT 27000
  21
  22 /* limited by the number of bits available */
  23 #define FB_DIV_MIN 4
  24 #define FB_DIV_LIMIT 2048
  25 #define REF_DIV_MIN 2
  26 #define REF_DIV_LIMIT 1024
  27 #define POST_DIV_MIN 2
  28 #define POST_DIV_LIMIT 127
  29
  30 /* pll flags */
  31 #define PLL_USE_BIOS_DIVS        (1 << 0)
  32 #define PLL_NO_ODD_POST_DIV      (1 << 1)
  33 #define PLL_USE_REF_DIV          (1 << 2)
  34 #define PLL_LEGACY               (1 << 3)
  35 #define PLL_PREFER_LOW_REF_DIV   (1 << 4)
  36 #define PLL_PREFER_HIGH_REF_DIV  (1 << 5)
  37 #define PLL_PREFER_LOW_FB_DIV    (1 << 6)
  38 #define PLL_PREFER_HIGH_FB_DIV   (1 << 7)
  39 #define PLL_PREFER_LOW_POST_DIV  (1 << 8)
  40 #define PLL_PREFER_HIGH_POST_DIV (1 << 9)
  41 #define PLL_USE_FRAC_FB_DIV      (1 << 10)
  42 #define PLL_PREFER_CLOSEST_LOWER (1 << 11)
  43 #define PLL_USE_POST_DIV         (1 << 12)
  44 #define PLL_IS_LCD               (1 << 13)
  45 #define PLL_PREFER_MINM_OVER_MAXP (1 << 14)
  46
  47
  48 struct pll_info {
  49         /* pixel clock to be programmed (kHz)*/
  50         uint32 pixelClock;
  51
  52         /* flags for the current clock */
  53         uint32 flags;
  54
  55         /* pll id */
  56         uint32 id;
  57
  58         /* reference frequency */
  59         uint32 referenceFreq;
  60
  61         /* fixed dividers */
  62         uint32 postDiv;
  63         uint32 referenceDiv;
  64         uint32 feedbackDiv;
  65         uint32 feedbackDivFrac;
  66
  67         /* pll in/out limits */
  68         uint32 pllInMin;
  69         uint32 pllInMax;
  70         uint32 pllOutMin;
  71         uint32 pllOutMax;
  72         uint32 lcdPllOutMin;
  73         uint32 lcdPllOutMax;
  74         uint32 bestVco;
  75
  76         /* divider limits */
  77         uint32 minRefDiv;
  78         uint32 maxRefDiv;
  79         uint32 minPostDiv;
  80         uint32 maxPostDiv;
  81         uint32 minFeedbackDiv;
  82         uint32 maxFeedbackDiv;
  83         uint32 minFeedbackDivFrac;
  84         uint32 maxFeedbackDivFrac;
  85
  86         /* spread spectrum info */
  87         bool ssEnabled;
  88         uint8 ssType;
  89         uint8 ssDelay;
  90         uint8 ssRange;
  91         uint8 ssReferenceDiv;
  92         uint16 ssPercentage;
  93         uint16 ssStep;
  94         /* asic spread spectrum */
  95         uint16 ssRate;
  96         uint16 ssAmount;
  97         uint16 ssPercentageDiv;
  98
  99         /* pixel clock to be used in pll calculations (kHz) */
 100         uint32 adjustedClock;
 101 };
 102
 103
 104 void pll_external_init();
 105 status_t pll_set_external(uint32 clock);
 106 status_t pll_set_dce(uint32 clock, uint8 clockType, uint8 clockSource);
 107
 108 status_t pll_adjust(pll_info* pll, display_mode* mode, uint8 crtcID);
 109 uint32 pll_usage_mask();
 110 uint32 pll_usage_count(uint32 pllID);
 111 uint32 pll_shared_dp();
 112 uint32 pll_next_available();
 113 status_t pll_compute(pll_info* pll);
 114 void pll_setup_flags(pll_info* pll, uint8 crtcID);
 115 status_t pll_limit_probe(pll_info* pll);
 116 status_t pll_ppll_ss_probe(pll_info* pll, uint32 ssID);
 117 status_t pll_asic_ss_probe(pll_info* pll, uint32 ssID);
 118 status_t pll_set(display_mode* mode, uint8 crtcID);
 119 status_t pll_pick(uint32 connectorIndex);
 120
 121
 122 #endif /* RADEON_HD_PLL_H */