src/add-ons/accelerants/skeleton/engine/dac.c

   1 /* program the DAC */
   2 /* Author:
   3    Rudolf Cornelissen 12/2003-10/2004
   4 */
   5
   6 #define MODULE_BIT 0x00010000
   7
   8 #include "std.h"
   9
  10 static status_t nv4_nv10_nv20_dac_pix_pll_find(
  11         display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test);
  12
  13 /* see if an analog VGA monitor is connected to connector #1 */
  14 bool eng_dac_crt_connected(void)
  15 {
  16         uint32 output, dac;
  17         bool present;
  18
  19         /* save output connector setting */
  20         output = DACR(OUTPUT);
  21         /* save DAC state */
  22         dac = DACR(TSTCTRL);
  23
  24         /* turn on DAC */
  25         DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeffff));
  26         /* select primary head and turn off CRT (and DVI?) outputs */
  27         DACW(OUTPUT, (output & 0x0000feee));
  28         /* wait for signal lines to stabilize */
  29         snooze(1000);
  30         /* re-enable CRT output */
  31         DACW(OUTPUT, (DACR(OUTPUT) | 0x00000001));
  32
  33         /* setup RGB test signal levels to approx 30% of DAC range and enable them */
  34         DACW(TSTDATA, ((0x2 << 30) | (0x140 << 20) | (0x140 << 10) | (0x140 << 0)));
  35         /* route test signals to output */
  36         DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000));
  37         /* wait for signal lines to stabilize */
  38         snooze(1000);
  39
  40         /* do actual detection: all signals paths high == CRT connected */
  41         if (DACR(TSTCTRL) & 0x10000000)
  42         {
  43                 present = true;
  44                 LOG(4,("DAC: CRT detected on connector #1\n"));
  45         }
  46         else
  47         {
  48                 present = false;
  49                 LOG(4,("DAC: no CRT detected on connector #1\n"));
  50         }
  51
  52         /* kill test signal routing */
  53         DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff));
  54
  55         /* restore output connector setting */
  56         DACW(OUTPUT, output);
  57         /* restore DAC state */
  58         DACW(TSTCTRL, dac);
  59
  60         return present;
  61 }
  62
  63 /*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/
  64 status_t eng_dac_mode(int mode,float brightness)
  65 {
  66         uint8 *r,*g,*b;
  67         int i, ri;
  68
  69         /*set colour arrays to point to space reserved in shared info*/
  70         r = si->color_data;
  71         g = r + 256;
  72         b = g + 256;
  73
  74         LOG(4,("DAC: Setting screen mode %d brightness %f\n", mode, brightness));
  75         /* init the palette for brightness specified */
  76         /* (Nvidia cards always use MSbits from screenbuffer as index for PAL) */
  77         for (i = 0; i < 256; i++)
  78         {
  79                 ri = i * brightness;
  80                 if (ri > 255) ri = 255;
  81                 b[i] = g[i] = r[i] = ri;
  82         }
  83
  84         if (eng_dac_palette(r,g,b) != B_OK) return B_ERROR;
  85
  86         /* disable palette RAM adressing mask */
  87         ENG_REG8(RG8_PALMASK) = 0xff;
  88         LOG(2,("DAC: PAL pixrdmsk readback $%02x\n", ENG_REG8(RG8_PALMASK)));
  89
  90         return B_OK;
  91 }
  92
  93 /*program the DAC palette using the given r,g,b values*/
  94 status_t eng_dac_palette(uint8 r[256],uint8 g[256],uint8 b[256])
  95 {
  96         int i;
  97
  98         LOG(4,("DAC: setting palette\n"));
  99
 100         /* select first PAL adress before starting programming */
 101         ENG_REG8(RG8_PALINDW) = 0x00;
 102
 103         /* loop through all 256 to program DAC */
 104         for (i = 0; i < 256; i++)
 105         {
 106                 /* the 6 implemented bits are on b0-b5 of the bus */
 107                 ENG_REG8(RG8_PALDATA) = r[i];
 108                 ENG_REG8(RG8_PALDATA) = g[i];
 109                 ENG_REG8(RG8_PALDATA) = b[i];
 110         }
 111         if (ENG_REG8(RG8_PALINDW) != 0x00)
 112         {
 113                 LOG(8,("DAC: PAL write index incorrect after programming\n"));
 114                 return B_ERROR;
 115         }
 116 if (1)
 117  {//reread LUT
 118         uint8 R, G, B;
 119
 120         /* select first PAL adress to read (modulo 3 counter) */
 121         ENG_REG8(RG8_PALINDR) = 0x00;
 122         for (i = 0; i < 256; i++)
 123         {
 124                 R = ENG_REG8(RG8_PALDATA);
 125                 G = ENG_REG8(RG8_PALDATA);
 126                 B = ENG_REG8(RG8_PALDATA);
 127                 if ((r[i] != R) || (g[i] != G) || (b[i] != B))
 128                         LOG(1,("DAC palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed
 129         }
 130  }
 131
 132         return B_OK;
 133 }
 134
 135 /*program the pixpll - frequency in kHz*/
 136 status_t eng_dac_set_pix_pll(display_mode target)
 137 {
 138         uint8 m=0,n=0,p=0;
 139 //      uint time = 0;
 140
 141         float pix_setting, req_pclk;
 142         status_t result;
 143
 144         /* we offer this option because some panels have very tight restrictions,
 145          * and there's no overlapping settings range that makes them all work.
 146          * note:
 147          * this assumes the cards BIOS correctly programmed the panel (is likely) */
 148         //fixme: when VESA DDC EDID stuff is implemented, this option can be deleted...
 149         if (si->ps.tmds1_active && !si->settings.pgm_panel)
 150         {
 151                 LOG(4,("DAC: Not programming DFP refresh (specified in skel.settings)\n"));
 152                 return B_OK;
 153         }
 154
 155         /* fix a DVI or laptop flatpanel to 60Hz refresh! */
 156         /* Note:
 157          * The pixelclock drives the flatpanel modeline, not the CRTC modeline. */
 158         if (si->ps.tmds1_active)
 159         {
 160                 LOG(4,("DAC: Fixing DFP refresh to 60Hz!\n"));
 161
 162                 /* use the panel's modeline to determine the needed pixelclock */
 163                 target.timing.pixel_clock = si->ps.p1_timing.pixel_clock;
 164         }
 165
 166         req_pclk = (target.timing.pixel_clock)/1000.0;
 167         LOG(4,("DAC: Setting PIX PLL for pixelclock %f\n", req_pclk));
 168
 169         /* signal that we actually want to set the mode */
 170         result = eng_dac_pix_pll_find(target,&pix_setting,&m,&n,&p, 1);
 171         if (result != B_OK)
 172         {
 173                 return result;
 174         }
 175
 176         /*reprogram (disable,select,wait for stability,enable)*/
 177 //      DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0F)|0x04);  /*disable the PIXPLL*/
 178 //      DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0C)|0x01);  /*select the PIXPLL*/
 179
 180         /* program new frequency */
 181         DACW(PIXPLLC, ((p << 16) | (n << 8) | m));
 182
 183         /* program 2nd set N and M scalers if they exist (b31=1 enables them) */
 184         if (si->ps.ext_pll) DACW(PIXPLLC2, 0x80000401);
 185
 186         /* Wait for the PIXPLL frequency to lock until timeout occurs */
 187 //fixme: do NV cards have a LOCK indication bit??
 188 /*      while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000))
 189         {
 190                 time++;
 191                 snooze(1);
 192         }
 193
 194         if (time > 2000)
 195                 LOG(2,("DAC: PIX PLL frequency not locked!\n"));
 196         else
 197                 LOG(2,("DAC: PIX PLL frequency locked\n"));
 198         DXIW(PIXCLKCTRL,DXIR(PIXCLKCTRL)&0x0B);         //enable the PIXPLL
 199 */
 200
 201 //for now:
 202         /* Give the PIXPLL frequency some time to lock... */
 203         snooze(1000);
 204         LOG(2,("DAC: PIX PLL frequency should be locked now...\n"));
 205
 206         return B_OK;
 207 }
 208
 209 /* find nearest valid pix pll */
 210 status_t eng_dac_pix_pll_find
 211         (display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test)
 212 {
 213         switch (si->ps.card_type) {
 214                 default:   return nv4_nv10_nv20_dac_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test);
 215         }
 216         return B_ERROR;
 217 }
 218
 219 /* find nearest valid pixel PLL setting */
 220 static status_t nv4_nv10_nv20_dac_pix_pll_find(
 221         display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test)
 222 {
 223         int m = 0, n = 0, p = 0/*, m_max*/;
 224         float error, error_best = 999999999;
 225         int best[3];
 226         float f_vco, max_pclk;
 227         float req_pclk = target.timing.pixel_clock/1000.0;
 228
 229         /* determine the max. reference-frequency postscaler setting for the
 230          * current card (see G100, G200 and G400 specs). */
 231 /*      switch(si->ps.card_type)
 232         {
 233         case G100:
 234                 LOG(4,("DAC: G100 restrictions apply\n"));
 235                 m_max = 7;
 236                 break;
 237         case G200:
 238                 LOG(4,("DAC: G200 restrictions apply\n"));
 239                 m_max = 7;
 240                 break;
 241         default:
 242                 LOG(4,("DAC: G400/G400MAX restrictions apply\n"));
 243                 m_max = 32;
 244                 break;
 245         }
 246 */
 247         LOG(4,("DAC: NV4/NV10/NV20 restrictions apply\n"));
 248
 249         /* determine the max. pixelclock for the current videomode */
 250         switch (target.space)
 251         {
 252                 case B_CMAP8:
 253                         max_pclk = si->ps.max_dac1_clock_8;
 254                         break;
 255                 case B_RGB15_LITTLE:
 256                 case B_RGB16_LITTLE:
 257                         max_pclk = si->ps.max_dac1_clock_16;
 258                         break;
 259                 case B_RGB24_LITTLE:
 260                         max_pclk = si->ps.max_dac1_clock_24;
 261                         break;
 262                 case B_RGB32_LITTLE:
 263                         max_pclk = si->ps.max_dac1_clock_32;
 264                         break;
 265                 default:
 266                         /* use fail-safe value */
 267                         max_pclk = si->ps.max_dac1_clock_32;
 268                         break;
 269         }
 270         /* if some dualhead mode is active, an extra restriction might apply */
 271         if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE))
 272                 max_pclk = si->ps.max_dac1_clock_32dh;
 273
 274         /* Make sure the requested pixelclock is within the PLL's operational limits */
 275         /* lower limit is min_pixel_vco divided by highest postscaler-factor */
 276         if (req_pclk < (si->ps.min_pixel_vco / 16.0))
 277         {
 278                 LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n",
 279                                                                                 req_pclk, (float)(si->ps.min_pixel_vco / 16.0)));
 280                 req_pclk = (si->ps.min_pixel_vco / 16.0);
 281         }
 282         /* upper limit is given by pins in combination with current active mode */
 283         if (req_pclk > max_pclk)
 284         {
 285                 LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n",
 286                                                                                                                 req_pclk, (float)max_pclk));
 287                 req_pclk = max_pclk;
 288         }
 289
 290         /* iterate through all valid PLL postscaler settings */
 291         for (p=0x01; p < 0x20; p = p<<1)
 292         {
 293                 /* calculate the needed VCO frequency for this postscaler setting */
 294                 f_vco = req_pclk * p;
 295
 296                 /* check if this is within range of the VCO specs */
 297                 if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco))
 298                 {
 299                         /* FX5600 and FX5700 tweak for 2nd set N and M scalers */
 300                         if (si->ps.ext_pll) f_vco /= 4;
 301
 302                         /* iterate trough all valid reference-frequency postscaler settings */
 303                         for (m = 7; m <= 14; m++)
 304                         {
 305                                 /* check if phase-discriminator will be within operational limits */
 306                                 //fixme: PLL calcs will be resetup/splitup/updated...
 307                                 if (si->ps.card_type == NV36)
 308                                 {
 309                                         if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue;
 310                                 }
 311                                 else
 312                                 {
 313                                         if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue;
 314                                 }
 315
 316                                 /* calculate VCO postscaler setting for current setup.. */
 317                                 n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);
 318
 319                                 /* ..and check for validity */
 320                                 if ((n < 1) || (n > 255))       continue;
 321
 322                                 /* find error in frequency this setting gives */
 323                                 if (si->ps.ext_pll)
 324                                 {
 325                                         /* FX5600 and FX5700 tweak for 2nd set N and M scalers */
 326                                         error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p));
 327                                 }
 328                                 else
 329                                         error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p));
 330
 331                                 /* note the setting if best yet */
 332                                 if (error < error_best)
 333                                 {
 334                                         error_best = error;
 335                                         best[0]=m;
 336                                         best[1]=n;
 337                                         best[2]=p;
 338                                 }
 339                         }
 340                 }
 341         }
 342
 343         /* setup the scalers programming values for found optimum setting */
 344         m = best[0];
 345         n = best[1];
 346         p = best[2];
 347
 348         /* log the VCO frequency found */
 349         f_vco = ((si->ps.f_ref / m) * n);
 350         /* FX5600 and FX5700 tweak for 2nd set N and M scalers */
 351         if (si->ps.ext_pll) f_vco *= 4;
 352
 353         LOG(2,("DAC: pix VCO frequency found %fMhz\n", f_vco));
 354
 355         /* return the results */
 356         *calc_pclk = (f_vco / p);
 357         *m_result = m;
 358         *n_result = n;
 359         switch(p)
 360         {
 361         case 1:
 362                 p = 0x00;
 363                 break;
 364         case 2:
 365                 p = 0x01;
 366                 break;
 367         case 4:
 368                 p = 0x02;
 369                 break;
 370         case 8:
 371                 p = 0x03;
 372                 break;
 373         case 16:
 374                 p = 0x04;
 375                 break;
 376         }
 377         *p_result = p;
 378
 379         /* display the found pixelclock values */
 380         LOG(2,("DAC: pix PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n",
 381                 req_pclk, *calc_pclk, *m_result, *n_result, *p_result));
 382
 383         return B_OK;
 384 }
 385
 386 /* find nearest valid system PLL setting */
 387 status_t eng_dac_sys_pll_find(
 388         float req_sclk, float* calc_sclk, uint8* m_result, uint8* n_result, uint8* p_result, uint8 test)
 389 {
 390         int m = 0, n = 0, p = 0, m_max, p_max;
 391         float error, error_best = 999999999;
 392         int best[3];
 393         float f_vco, discr_low, discr_high;
 394
 395         /* determine the max. reference-frequency postscaler setting for the
 396          * current requested clock */
 397         switch (si->ps.card_arch)
 398         {
 399         case NV04A:
 400                 LOG(4,("DAC: NV04 restrictions apply\n"));
 401                 /* set phase-discriminator frequency range (Mhz) (verified) */
 402                 discr_low = 1.0;
 403                 discr_high = 2.0;
 404                 /* set max. useable reference frequency postscaler divider factor */
 405                 m_max = 14;
 406                 /* set max. useable VCO output postscaler divider factor */
 407                 p_max = 16;
 408                 break;
 409         default:
 410                 switch (si->ps.card_type)
 411                 {
 412                 case NV28:
 413                         //fixme: how about some other cards???
 414                         LOG(4,("DAC: NV28 restrictions apply\n"));
 415                         /* set max. useable reference frequency postscaler divider factor;
 416                          * apparantly we would get distortions on high PLL output frequencies if
 417                          * we use the phase-discriminator at low frequencies */
 418                         if (req_sclk > 340.0) m_max = 2;                        /* Fpll > 340Mhz */
 419                         else if (req_sclk > 200.0) m_max = 4;           /* 200Mhz < Fpll <= 340Mhz */
 420                                 else if (req_sclk > 150.0) m_max = 6;   /* 150Mhz < Fpll <= 200Mhz */
 421                                         else m_max = 14;                                        /* Fpll < 150Mhz */
 422
 423                         /* set max. useable VCO output postscaler divider factor */
 424                         p_max = 32;
 425                         /* set phase-discriminator frequency range (Mhz) (verified) */
 426                         discr_low = 1.0;
 427                         discr_high = 27.0;
 428                         break;
 429                 default:
 430                         LOG(4,("DAC: NV10/NV20/NV30 restrictions apply\n"));
 431                         /* set max. useable reference frequency postscaler divider factor;
 432                          * apparantly we would get distortions on high PLL output frequencies if
 433                          * we use the phase-discriminator at low frequencies */
 434                         if (req_sclk > 340.0) m_max = 2;                /* Fpll > 340Mhz */
 435                         else if (req_sclk > 250.0) m_max = 6;   /* 250Mhz < Fpll <= 340Mhz */
 436                                 else m_max = 14;                                        /* Fpll < 250Mhz */
 437
 438                         /* set max. useable VCO output postscaler divider factor */
 439                         p_max = 16;
 440                         /* set phase-discriminator frequency range (Mhz) (verified) */
 441                         if (si->ps.card_type == NV36) discr_low = 3.2;
 442                         else discr_low = 1.0;
 443                         /* (high discriminator spec is failsafe) */
 444                         discr_high = 14.0;
 445                         break;
 446                 }
 447                 break;
 448         }
 449
 450         LOG(4,("DAC: PLL reference frequency postscaler divider range is 1 - %d\n", m_max));
 451         LOG(4,("DAC: PLL VCO output postscaler divider range is 1 - %d\n", p_max));
 452         LOG(4,("DAC: PLL discriminator input frequency range is %2.2fMhz - %2.2fMhz\n",
 453                 discr_low, discr_high));
 454
 455         /* Make sure the requested clock is within the PLL's operational limits */
 456         /* lower limit is min_system_vco divided by highest postscaler-factor */
 457         if (req_sclk < (si->ps.min_system_vco / ((float)p_max)))
 458         {
 459                 LOG(4,("DAC: clamping sysclock: requested %fMHz, set to %fMHz\n",
 460                         req_sclk, (si->ps.min_system_vco / ((float)p_max))));
 461                 req_sclk = (si->ps.min_system_vco / ((float)p_max));
 462         }
 463         /* upper limit is given by pins */
 464         if (req_sclk > si->ps.max_system_vco)
 465         {
 466                 LOG(4,("DAC: clamping sysclock: requested %fMHz, set to %fMHz\n",
 467                         req_sclk, (float)si->ps.max_system_vco));
 468                 req_sclk = si->ps.max_system_vco;
 469         }
 470
 471         /* iterate through all valid PLL postscaler settings */
 472         for (p=0x01; p <= p_max; p = p<<1)
 473         {
 474                 /* calculate the needed VCO frequency for this postscaler setting */
 475                 f_vco = req_sclk * p;
 476
 477                 /* check if this is within range of the VCO specs */
 478                 if ((f_vco >= si->ps.min_system_vco) && (f_vco <= si->ps.max_system_vco))
 479                 {
 480                         /* FX5600 and FX5700 tweak for 2nd set N and M scalers */
 481                         if (si->ps.ext_pll) f_vco /= 4;
 482
 483                         /* iterate trough all valid reference-frequency postscaler settings */
 484                         for (m = 1; m <= m_max; m++)
 485                         {
 486                                 /* check if phase-discriminator will be within operational limits */
 487                                 if (((si->ps.f_ref / m) < discr_low) || ((si->ps.f_ref / m) > discr_high))
 488                                         continue;
 489
 490                                 /* calculate VCO postscaler setting for current setup.. */
 491                                 n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5);
 492
 493                                 /* ..and check for validity */
 494                                 if ((n < 1) || (n > 255)) continue;
 495
 496                                 /* find error in frequency this setting gives */
 497                                 if (si->ps.ext_pll)
 498                                 {
 499                                         /* FX5600 and FX5700 tweak for 2nd set N and M scalers */
 500                                         error = fabs((req_sclk / 4) - (((si->ps.f_ref / m) * n) / p));
 501                                 }
 502                                 else
 503                                         error = fabs(req_sclk - (((si->ps.f_ref / m) * n) / p));
 504
 505                                 /* note the setting if best yet */
 506                                 if (error < error_best)
 507                                 {
 508                                         error_best = error;
 509                                         best[0]=m;
 510                                         best[1]=n;
 511                                         best[2]=p;
 512                                 }
 513                         }
 514                 }
 515         }
 516
 517         /* setup the scalers programming values for found optimum setting */
 518         m = best[0];
 519         n = best[1];
 520         p = best[2];
 521
 522         /* log the VCO frequency found */
 523         f_vco = ((si->ps.f_ref / m) * n);
 524         /* FX5600 and FX5700 tweak for 2nd set N and M scalers */
 525         if (si->ps.ext_pll) f_vco *= 4;
 526
 527         LOG(2,("DAC: sys VCO frequency found %fMhz\n", f_vco));
 528
 529         /* return the results */
 530         *calc_sclk = (f_vco / p);
 531         *m_result = m;
 532         *n_result = n;
 533         switch(p)
 534         {
 535         case 1:
 536                 p = 0x00;
 537                 break;
 538         case 2:
 539                 p = 0x01;
 540                 break;
 541         case 4:
 542                 p = 0x02;
 543                 break;
 544         case 8:
 545                 p = 0x03;
 546                 break;
 547         case 16:
 548                 p = 0x04;
 549                 break;
 550         case 32:
 551                 p = 0x05;
 552                 break;
 553         }
 554         *p_result = p;
 555
 556         /* display the found pixelclock values */
 557         LOG(2,("DAC: sys PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n",
 558                 req_sclk, *calc_sclk, *m_result, *n_result, *p_result));
 559
 560         return B_OK;
 561 }