| blob | d0e884d3a7372f003f1777aeba1f6ccc15c2e26c |
1 /*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/pinctrl/omap.h>
15 #include "skeleton.dtsi"
17 / {
18 compatible = "ti,omap3430", "ti,omap3";
19 interrupt-parent = <&intc>;
21 aliases {
22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 i2c2 = &i2c3;
25 serial0 = &uart1;
26 serial1 = &uart2;
27 serial2 = &uart3;
28 };
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
34 cpu@0 {
35 compatible = "arm,cortex-a8";
36 device_type = "cpu";
37 reg = <0x0>;
39 clocks = <&dpll1_ck>;
40 clock-names = "cpu";
42 clock-latency = <300000>; /* From omap-cpufreq driver */
43 };
44 };
46 pmu {
47 compatible = "arm,cortex-a8-pmu";
48 reg = <0x54000000 0x800000>;
49 interrupts = <3>;
50 ti,hwmods = "debugss";
51 };
53 /*
54 * The soc node represents the soc top level view. It is used for IPs
55 * that are not memory mapped in the MPU view or for the MPU itself.
56 */
57 soc {
58 compatible = "ti,omap-infra";
59 mpu {
60 compatible = "ti,omap3-mpu";
61 ti,hwmods = "mpu";
62 };
64 iva: iva {
65 compatible = "ti,iva2.2";
66 ti,hwmods = "iva";
68 dsp {
69 compatible = "ti,omap3-c64";
70 };
71 };
72 };
74 /*
75 * XXX: Use a flat representation of the OMAP3 interconnect.
76 * The real OMAP interconnect network is quite complex.
77 * Since it will not bring real advantage to represent that in DT for
78 * the moment, just use a fake OCP bus entry to represent the whole bus
79 * hierarchy.
80 */
81 ocp {
82 compatible = "simple-bus";
83 reg = <0x68000000 0x10000>;
84 interrupts = <9 10>;
85 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges;
88 ti,hwmods = "l3_main";
90 aes: aes@480c5000 {
91 compatible = "ti,omap3-aes";
92 ti,hwmods = "aes";
93 reg = <0x480c5000 0x50>;
94 interrupts = <0>;
95 };
97 prm: prm@48306000 {
98 compatible = "ti,omap3-prm";
99 reg = <0x48306000 0x4000>;
100 interrupts = <11>;
102 prm_clocks: clocks {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 };
107 prm_clockdomains: clockdomains {
108 };
109 };
111 cm: cm@48004000 {
112 compatible = "ti,omap3-cm";
113 reg = <0x48004000 0x4000>;
115 cm_clocks: clocks {
116 #address-cells = <1>;
117 #size-cells = <0>;
118 };
120 cm_clockdomains: clockdomains {
121 };
122 };
124 scrm: scrm@48002000 {
125 compatible = "ti,omap3-scrm";
126 reg = <0x48002000 0x2000>;
128 scrm_clocks: clocks {
129 #address-cells = <1>;
130 #size-cells = <0>;
131 };
133 scrm_clockdomains: clockdomains {
134 };
135 };
137 counter32k: counter@48320000 {
138 compatible = "ti,omap-counter32k";
139 reg = <0x48320000 0x20>;
140 ti,hwmods = "counter_32k";
141 };
143 intc: interrupt-controller@48200000 {
144 compatible = "ti,omap3-intc";
145 interrupt-controller;
146 #interrupt-cells = <1>;
147 reg = <0x48200000 0x1000>;
148 };
150 sdma: dma-controller@48056000 {
151 compatible = "ti,omap3630-sdma", "ti,omap3430-sdma";
152 reg = <0x48056000 0x1000>;
153 interrupts = <12>,
154 <13>,
155 <14>,
156 <15>;
157 #dma-cells = <1>;
158 #dma-channels = <32>;
159 #dma-requests = <96>;
160 };
162 omap3_pmx_core: pinmux@48002030 {
163 compatible = "ti,omap3-padconf", "pinctrl-single";
164 reg = <0x48002030 0x0238>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 #interrupt-cells = <1>;
168 interrupt-controller;
169 pinctrl-single,register-width = <16>;
170 pinctrl-single,function-mask = <0xff1f>;
171 };
173 omap3_pmx_wkup: pinmux@48002a00 {
174 compatible = "ti,omap3-padconf", "pinctrl-single";
175 reg = <0x48002a00 0x5c>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 #interrupt-cells = <1>;
179 interrupt-controller;
180 pinctrl-single,register-width = <16>;
181 pinctrl-single,function-mask = <0xff1f>;
182 };
184 omap3_scm_general: tisyscon@48002270 {
185 compatible = "syscon";
186 reg = <0x48002270 0x2f0>;
187 };
189 pbias_regulator: pbias_regulator {
190 compatible = "ti,pbias-omap";
191 reg = <0x2b0 0x4>;
192 syscon = <&omap3_scm_general>;
193 pbias_mmc_reg: pbias_mmc_omap2430 {
194 regulator-name = "pbias_mmc_omap2430";
195 regulator-min-microvolt = <1800000>;
196 regulator-max-microvolt = <3000000>;
197 };
198 };
200 gpio1: gpio@48310000 {
201 compatible = "ti,omap3-gpio";
202 reg = <0x48310000 0x200>;
203 interrupts = <29>;
204 ti,hwmods = "gpio1";
205 ti,gpio-always-on;
206 gpio-controller;
207 #gpio-cells = <2>;
208 interrupt-controller;
209 #interrupt-cells = <2>;
210 };
212 gpio2: gpio@49050000 {
213 compatible = "ti,omap3-gpio";
214 reg = <0x49050000 0x200>;
215 interrupts = <30>;
216 ti,hwmods = "gpio2";
217 gpio-controller;
218 #gpio-cells = <2>;
219 interrupt-controller;
220 #interrupt-cells = <2>;
221 };
223 gpio3: gpio@49052000 {
224 compatible = "ti,omap3-gpio";
225 reg = <0x49052000 0x200>;
226 interrupts = <31>;
227 ti,hwmods = "gpio3";
228 gpio-controller;
229 #gpio-cells = <2>;
230 interrupt-controller;
231 #interrupt-cells = <2>;
232 };
234 gpio4: gpio@49054000 {
235 compatible = "ti,omap3-gpio";
236 reg = <0x49054000 0x200>;
237 interrupts = <32>;
238 ti,hwmods = "gpio4";
239 gpio-controller;
240 #gpio-cells = <2>;
241 interrupt-controller;
242 #interrupt-cells = <2>;
243 };
245 gpio5: gpio@49056000 {
246 compatible = "ti,omap3-gpio";
247 reg = <0x49056000 0x200>;
248 interrupts = <33>;
249 ti,hwmods = "gpio5";
250 gpio-controller;
251 #gpio-cells = <2>;
252 interrupt-controller;
253 #interrupt-cells = <2>;
254 };
256 gpio6: gpio@49058000 {
257 compatible = "ti,omap3-gpio";
258 reg = <0x49058000 0x200>;
259 interrupts = <34>;
260 ti,hwmods = "gpio6";
261 gpio-controller;
262 #gpio-cells = <2>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
265 };
267 uart1: serial@4806a000 {
268 compatible = "ti,omap3-uart";
269 reg = <0x4806a000 0x2000>;
270 interrupts-extended = <&intc 72>;
271 dmas = <&sdma 49 &sdma 50>;
272 dma-names = "tx", "rx";
273 ti,hwmods = "uart1";
274 clock-frequency = <48000000>;
275 };
277 uart2: serial@4806c000 {
278 compatible = "ti,omap3-uart";
279 reg = <0x4806c000 0x400>;
280 interrupts-extended = <&intc 73>;
281 dmas = <&sdma 51 &sdma 52>;
282 dma-names = "tx", "rx";
283 ti,hwmods = "uart2";
284 clock-frequency = <48000000>;
285 };
287 uart3: serial@49020000 {
288 compatible = "ti,omap3-uart";
289 reg = <0x49020000 0x400>;
290 interrupts-extended = <&intc 74>;
291 dmas = <&sdma 53 &sdma 54>;
292 dma-names = "tx", "rx";
293 ti,hwmods = "uart3";
294 clock-frequency = <48000000>;
295 };
297 i2c1: i2c@48070000 {
298 compatible = "ti,omap3-i2c";
299 reg = <0x48070000 0x80>;
300 interrupts = <56>;
301 dmas = <&sdma 27 &sdma 28>;
302 dma-names = "tx", "rx";
303 #address-cells = <1>;
304 #size-cells = <0>;
305 ti,hwmods = "i2c1";
306 };
308 i2c2: i2c@48072000 {
309 compatible = "ti,omap3-i2c";
310 reg = <0x48072000 0x80>;
311 interrupts = <57>;
312 dmas = <&sdma 29 &sdma 30>;
313 dma-names = "tx", "rx";
314 #address-cells = <1>;
315 #size-cells = <0>;
316 ti,hwmods = "i2c2";
317 };
319 i2c3: i2c@48060000 {
320 compatible = "ti,omap3-i2c";
321 reg = <0x48060000 0x80>;
322 interrupts = <61>;
323 dmas = <&sdma 25 &sdma 26>;
324 dma-names = "tx", "rx";
325 #address-cells = <1>;
326 #size-cells = <0>;
327 ti,hwmods = "i2c3";
328 };
330 mailbox: mailbox@48094000 {
331 compatible = "ti,omap3-mailbox";
332 ti,hwmods = "mailbox";
333 reg = <0x48094000 0x200>;
334 interrupts = <26>;
335 ti,mbox-num-users = <2>;
336 ti,mbox-num-fifos = <2>;
337 mbox_dsp: dsp {
338 ti,mbox-tx = <0 0 0>;
339 ti,mbox-rx = <1 0 0>;
340 };
341 };
343 mcspi1: spi@48098000 {
344 compatible = "ti,omap2-mcspi";
345 reg = <0x48098000 0x100>;
346 interrupts = <65>;
347 #address-cells = <1>;
348 #size-cells = <0>;
349 ti,hwmods = "mcspi1";
350 ti,spi-num-cs = <4>;
351 dmas = <&sdma 35>,
352 <&sdma 36>,
353 <&sdma 37>,
354 <&sdma 38>,
355 <&sdma 39>,
356 <&sdma 40>,
357 <&sdma 41>,
358 <&sdma 42>;
359 dma-names = "tx0", "rx0", "tx1", "rx1",
360 "tx2", "rx2", "tx3", "rx3";
361 };
363 mcspi2: spi@4809a000 {
364 compatible = "ti,omap2-mcspi";
365 reg = <0x4809a000 0x100>;
366 interrupts = <66>;
367 #address-cells = <1>;
368 #size-cells = <0>;
369 ti,hwmods = "mcspi2";
370 ti,spi-num-cs = <2>;
371 dmas = <&sdma 43>,
372 <&sdma 44>,
373 <&sdma 45>,
374 <&sdma 46>;
375 dma-names = "tx0", "rx0", "tx1", "rx1";
376 };
378 mcspi3: spi@480b8000 {
379 compatible = "ti,omap2-mcspi";
380 reg = <0x480b8000 0x100>;
381 interrupts = <91>;
382 #address-cells = <1>;
383 #size-cells = <0>;
384 ti,hwmods = "mcspi3";
385 ti,spi-num-cs = <2>;
386 dmas = <&sdma 15>,
387 <&sdma 16>,
388 <&sdma 23>,
389 <&sdma 24>;
390 dma-names = "tx0", "rx0", "tx1", "rx1";
391 };
393 mcspi4: spi@480ba000 {
394 compatible = "ti,omap2-mcspi";
395 reg = <0x480ba000 0x100>;
396 interrupts = <48>;
397 #address-cells = <1>;
398 #size-cells = <0>;
399 ti,hwmods = "mcspi4";
400 ti,spi-num-cs = <1>;
401 dmas = <&sdma 70>, <&sdma 71>;
402 dma-names = "tx0", "rx0";
403 };
405 hdqw1w: 1w@480b2000 {
406 compatible = "ti,omap3-1w";
407 reg = <0x480b2000 0x1000>;
408 interrupts = <58>;
409 ti,hwmods = "hdq1w";
410 };
412 mmc1: mmc@4809c000 {
413 compatible = "ti,omap3-hsmmc";
414 reg = <0x4809c000 0x200>;
415 interrupts = <83>;
416 ti,hwmods = "mmc1";
417 ti,dual-volt;
418 dmas = <&sdma 61>, <&sdma 62>;
419 dma-names = "tx", "rx";
420 pbias-supply = <&pbias_mmc_reg>;
421 };
423 mmc2: mmc@480b4000 {
424 compatible = "ti,omap3-hsmmc";
425 reg = <0x480b4000 0x200>;
426 interrupts = <86>;
427 ti,hwmods = "mmc2";
428 dmas = <&sdma 47>, <&sdma 48>;
429 dma-names = "tx", "rx";
430 };
432 mmc3: mmc@480ad000 {
433 compatible = "ti,omap3-hsmmc";
434 reg = <0x480ad000 0x200>;
435 interrupts = <94>;
436 ti,hwmods = "mmc3";
437 dmas = <&sdma 77>, <&sdma 78>;
438 dma-names = "tx", "rx";
439 };
441 mmu_isp: mmu@480bd400 {
442 compatible = "ti,omap2-iommu";
443 reg = <0x480bd400 0x80>;
444 interrupts = <24>;
445 ti,hwmods = "mmu_isp";
446 ti,#tlb-entries = <8>;
447 };
449 mmu_iva: mmu@5d000000 {
450 compatible = "ti,omap2-iommu";
451 reg = <0x5d000000 0x80>;
452 interrupts = <28>;
453 ti,hwmods = "mmu_iva";
454 status = "disabled";
455 };
457 wdt2: wdt@48314000 {
458 compatible = "ti,omap3-wdt";
459 reg = <0x48314000 0x80>;
460 ti,hwmods = "wd_timer2";
461 };
463 mcbsp1: mcbsp@48074000 {
464 compatible = "ti,omap3-mcbsp";
465 reg = <0x48074000 0xff>;
466 reg-names = "mpu";
467 interrupts = <16>, /* OCP compliant interrupt */
468 <59>, /* TX interrupt */
469 <60>; /* RX interrupt */
470 interrupt-names = "common", "tx", "rx";
471 ti,buffer-size = <128>;
472 ti,hwmods = "mcbsp1";
473 dmas = <&sdma 31>,
474 <&sdma 32>;
475 dma-names = "tx", "rx";
476 status = "disabled";
477 };
479 mcbsp2: mcbsp@49022000 {
480 compatible = "ti,omap3-mcbsp";
481 reg = <0x49022000 0xff>,
482 <0x49028000 0xff>;
483 reg-names = "mpu", "sidetone";
484 interrupts = <17>, /* OCP compliant interrupt */
485 <62>, /* TX interrupt */
486 <63>, /* RX interrupt */
487 <4>; /* Sidetone */
488 interrupt-names = "common", "tx", "rx", "sidetone";
489 ti,buffer-size = <1280>;
490 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
491 dmas = <&sdma 33>,
492 <&sdma 34>;
493 dma-names = "tx", "rx";
494 status = "disabled";
495 };
497 mcbsp3: mcbsp@49024000 {
498 compatible = "ti,omap3-mcbsp";
499 reg = <0x49024000 0xff>,
500 <0x4902a000 0xff>;
501 reg-names = "mpu", "sidetone";
502 interrupts = <22>, /* OCP compliant interrupt */
503 <89>, /* TX interrupt */
504 <90>, /* RX interrupt */
505 <5>; /* Sidetone */
506 interrupt-names = "common", "tx", "rx", "sidetone";
507 ti,buffer-size = <128>;
508 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
509 dmas = <&sdma 17>,
510 <&sdma 18>;
511 dma-names = "tx", "rx";
512 status = "disabled";
513 };
515 mcbsp4: mcbsp@49026000 {
516 compatible = "ti,omap3-mcbsp";
517 reg = <0x49026000 0xff>;
518 reg-names = "mpu";
519 interrupts = <23>, /* OCP compliant interrupt */
520 <54>, /* TX interrupt */
521 <55>; /* RX interrupt */
522 interrupt-names = "common", "tx", "rx";
523 ti,buffer-size = <128>;
524 ti,hwmods = "mcbsp4";
525 dmas = <&sdma 19>,
526 <&sdma 20>;
527 dma-names = "tx", "rx";
528 status = "disabled";
529 };
531 mcbsp5: mcbsp@48096000 {
532 compatible = "ti,omap3-mcbsp";
533 reg = <0x48096000 0xff>;
534 reg-names = "mpu";
535 interrupts = <27>, /* OCP compliant interrupt */
536 <81>, /* TX interrupt */
537 <82>; /* RX interrupt */
538 interrupt-names = "common", "tx", "rx";
539 ti,buffer-size = <128>;
540 ti,hwmods = "mcbsp5";
541 dmas = <&sdma 21>,
542 <&sdma 22>;
543 dma-names = "tx", "rx";
544 status = "disabled";
545 };
547 sham: sham@480c3000 {
548 compatible = "ti,omap3-sham";
549 ti,hwmods = "sham";
550 reg = <0x480c3000 0x64>;
551 interrupts = <49>;
552 };
554 smartreflex_core: smartreflex@480cb000 {
555 compatible = "ti,omap3-smartreflex-core";
556 ti,hwmods = "smartreflex_core";
557 reg = <0x480cb000 0x400>;
558 interrupts = <19>;
559 };
561 smartreflex_mpu_iva: smartreflex@480c9000 {
562 compatible = "ti,omap3-smartreflex-iva";
563 ti,hwmods = "smartreflex_mpu_iva";
564 reg = <0x480c9000 0x400>;
565 interrupts = <18>;
566 };
568 timer1: timer@48318000 {
569 compatible = "ti,omap3430-timer";
570 reg = <0x48318000 0x400>;
571 interrupts = <37>;
572 ti,hwmods = "timer1";
573 ti,timer-alwon;
574 };
576 timer2: timer@49032000 {
577 compatible = "ti,omap3430-timer";
578 reg = <0x49032000 0x400>;
579 interrupts = <38>;
580 ti,hwmods = "timer2";
581 };
583 timer3: timer@49034000 {
584 compatible = "ti,omap3430-timer";
585 reg = <0x49034000 0x400>;
586 interrupts = <39>;
587 ti,hwmods = "timer3";
588 };
590 timer4: timer@49036000 {
591 compatible = "ti,omap3430-timer";
592 reg = <0x49036000 0x400>;
593 interrupts = <40>;
594 ti,hwmods = "timer4";
595 };
597 timer5: timer@49038000 {
598 compatible = "ti,omap3430-timer";
599 reg = <0x49038000 0x400>;
600 interrupts = <41>;
601 ti,hwmods = "timer5";
602 ti,timer-dsp;
603 };
605 timer6: timer@4903a000 {
606 compatible = "ti,omap3430-timer";
607 reg = <0x4903a000 0x400>;
608 interrupts = <42>;
609 ti,hwmods = "timer6";
610 ti,timer-dsp;
611 };
613 timer7: timer@4903c000 {
614 compatible = "ti,omap3430-timer";
615 reg = <0x4903c000 0x400>;
616 interrupts = <43>;
617 ti,hwmods = "timer7";
618 ti,timer-dsp;
619 };
621 timer8: timer@4903e000 {
622 compatible = "ti,omap3430-timer";
623 reg = <0x4903e000 0x400>;
624 interrupts = <44>;
625 ti,hwmods = "timer8";
626 ti,timer-pwm;
627 ti,timer-dsp;
628 };
630 timer9: timer@49040000 {
631 compatible = "ti,omap3430-timer";
632 reg = <0x49040000 0x400>;
633 interrupts = <45>;
634 ti,hwmods = "timer9";
635 ti,timer-pwm;
636 };
638 timer10: timer@48086000 {
639 compatible = "ti,omap3430-timer";
640 reg = <0x48086000 0x400>;
641 interrupts = <46>;
642 ti,hwmods = "timer10";
643 ti,timer-pwm;
644 };
646 timer11: timer@48088000 {
647 compatible = "ti,omap3430-timer";
648 reg = <0x48088000 0x400>;
649 interrupts = <47>;
650 ti,hwmods = "timer11";
651 ti,timer-pwm;
652 };
654 timer12: timer@48304000 {
655 compatible = "ti,omap3430-timer";
656 reg = <0x48304000 0x400>;
657 interrupts = <95>;
658 ti,hwmods = "timer12";
659 ti,timer-alwon;
660 ti,timer-secure;
661 };
663 usbhstll: usbhstll@48062000 {
664 compatible = "ti,usbhs-tll";
665 reg = <0x48062000 0x1000>;
666 interrupts = <78>;
667 ti,hwmods = "usb_tll_hs";
668 };
670 usbhshost: usbhshost@48064000 {
671 compatible = "ti,usbhs-host";
672 reg = <0x48064000 0x400>;
673 ti,hwmods = "usb_host_hs";
674 #address-cells = <1>;
675 #size-cells = <1>;
676 ranges;
678 usbhsohci: ohci@48064400 {
679 compatible = "ti,ohci-omap3";
680 reg = <0x48064400 0x400>;
681 interrupt-parent = <&intc>;
682 interrupts = <76>;
683 };
685 usbhsehci: ehci@48064800 {
686 compatible = "ti,ehci-omap";
687 reg = <0x48064800 0x400>;
688 interrupt-parent = <&intc>;
689 interrupts = <77>;
690 };
691 };
693 gpmc: gpmc@6e000000 {
694 compatible = "ti,omap3430-gpmc";
695 ti,hwmods = "gpmc";
696 reg = <0x6e000000 0x02d0>;
697 interrupts = <20>;
698 gpmc,num-cs = <8>;
699 gpmc,num-waitpins = <4>;
700 #address-cells = <2>;
701 #size-cells = <1>;
702 };
704 usb_otg_hs: usb_otg_hs@480ab000 {
705 compatible = "ti,omap3-musb";
706 reg = <0x480ab000 0x1000>;
707 interrupts = <92>, <93>;
708 interrupt-names = "mc", "dma";
709 ti,hwmods = "usb_otg_hs";
710 multipoint = <1>;
711 num-eps = <16>;
712 ram-bits = <12>;
713 };
715 dss: dss@48050000 {
716 compatible = "ti,omap3-dss";
717 reg = <0x48050000 0x200>;
718 status = "disabled";
719 ti,hwmods = "dss_core";
720 clocks = <&dss1_alwon_fck>;
721 clock-names = "fck";
722 #address-cells = <1>;
723 #size-cells = <1>;
724 ranges;
726 dispc@48050400 {
727 compatible = "ti,omap3-dispc";
728 reg = <0x48050400 0x400>;
729 interrupts = <25>;
730 ti,hwmods = "dss_dispc";
731 clocks = <&dss1_alwon_fck>;
732 clock-names = "fck";
733 };
735 dsi: encoder@4804fc00 {
736 compatible = "ti,omap3-dsi";
737 reg = <0x4804fc00 0x200>,
738 <0x4804fe00 0x40>,
739 <0x4804ff00 0x20>;
740 reg-names = "proto", "phy", "pll";
741 interrupts = <25>;
742 status = "disabled";
743 ti,hwmods = "dss_dsi1";
744 clocks = <&dss1_alwon_fck>, <&dss2_alwon_fck>;
745 clock-names = "fck", "sys_clk";
746 };
748 rfbi: encoder@48050800 {
749 compatible = "ti,omap3-rfbi";
750 reg = <0x48050800 0x100>;
751 status = "disabled";
752 ti,hwmods = "dss_rfbi";
753 clocks = <&dss1_alwon_fck>, <&dss_ick>;
754 clock-names = "fck", "ick";
755 };
757 venc: encoder@48050c00 {
758 compatible = "ti,omap3-venc";
759 reg = <0x48050c00 0x100>;
760 status = "disabled";
761 ti,hwmods = "dss_venc";
762 clocks = <&dss_tv_fck>;
763 clock-names = "fck";
764 };
765 };
767 ssi: ssi-controller@48058000 {
768 compatible = "ti,omap3-ssi";
769 ti,hwmods = "ssi";
771 status = "disabled";
773 reg = <0x48058000 0x1000>,
774 <0x48059000 0x1000>;
775 reg-names = "sys",
776 "gdd";
778 interrupts = <71>;
779 interrupt-names = "gdd_mpu";
781 #address-cells = <1>;
782 #size-cells = <1>;
783 ranges;
785 ssi_port1: ssi-port@4805a000 {
786 compatible = "ti,omap3-ssi-port";
788 reg = <0x4805a000 0x800>,
789 <0x4805a800 0x800>;
790 reg-names = "tx",
791 "rx";
793 interrupt-parent = <&intc>;
794 interrupts = <67>,
795 <68>;
796 };
798 ssi_port2: ssi-port@4805b000 {
799 compatible = "ti,omap3-ssi-port";
801 reg = <0x4805b000 0x800>,
802 <0x4805b800 0x800>;
803 reg-names = "tx",
804 "rx";
806 interrupt-parent = <&intc>;
807 interrupts = <69>,
808 <70>;
809 };
810 };
811 };
812 };
814 /include/ "omap3xxx-clocks.dtsi"