headers/private/firewire/fwphyreg.h

   1 /*-
   2  * Copyright (C) 2003
   3  *      Hidetoshi Shimokawa. All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. All advertising materials mentioning features or use of this software
  14  *    must display the following acknowledgement:
  15  *
  16  *      This product includes software developed by Hidetoshi Shimokawa.
  17  *
  18  * 4. Neither the name of the author nor the names of its contributors
  19  *    may be used to endorse or promote products derived from this software
  20  *    without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  *
  34  * $FreeBSD: src/sys/dev/firewire/fwphyreg.h,v 1.3 2005/01/06 01:42:41 imp Exp $
  35  */
  36
  37 /*
  38  * IEEE 1394a
  39  * Figure 5B - 1
  40  */
  41 struct phyreg_base {
  42 #if BYTE_ORDER == BIG_ENDIAN
  43         uint8_t phy_id:6,
  44                 r:1,
  45                 cps:1;
  46         uint8_t rhb:1,
  47                 ibr:1,
  48                 gap_count:6;
  49         uint8_t extended:3,
  50                 num_ports:5;
  51         uint8_t phy_speed:3,
  52                 :1,
  53                 delay:4;
  54         uint8_t lctrl:1,
  55                 c:1,
  56                 jitter:3,
  57                 pwr_class:3;
  58         uint8_t wdie:1,
  59                 isbr:1,
  60                 ctoi:1,
  61                 cpsi:1,
  62                 stoi:1,
  63                 pei:1,
  64                 eaa:1,
  65                 emc:1;
  66         uint8_t legacy_spd:3,
  67                 blink:1,
  68                 bridge:2,
  69                 :2;
  70         uint8_t page_select:3,
  71                 :1,
  72                 port_select:4;
  73 #else
  74         uint8_t cps:1,
  75                 r:1,
  76                 phy_id:6;
  77         uint8_t gap_count:6,
  78                 ibr:1,
  79                 rhb:1;
  80         uint8_t num_ports:5,
  81                 extended:3;
  82         uint8_t delay:4,
  83                 :1,
  84                 phy_speed:3;
  85         uint8_t pwr_class:3,
  86                 jitter:3,
  87                 c:1,
  88                 lctrl:1;
  89         uint8_t emc:1,
  90                 eaa:1,
  91                 pei:1,
  92                 stoi:1,
  93                 cpsi:1,
  94                 ctoi:1,
  95                 isbr:1,
  96                 wdie:1;
  97         uint8_t :2,
  98                 bridge:2,
  99                 blink:1,
 100                 legacy_spd:3;
 101         uint8_t port_select:4,
 102                 :1,
 103                 page_select:3;
 104 #endif
 105 };
 106
 107 /*
 108  * IEEE 1394a
 109  * Figure 5B - 2
 110  */
 111 struct phyreg_page0 {
 112 #if BYTE_ORDER == BIG_ENDIAN
 113         uint8_t astat:2,
 114                 bstat:2,
 115                 ch:1,
 116                 con:1,
 117                 rxok:1,
 118                 dis:1;
 119         uint8_t negotiated_speed:3,
 120                 pie:1,
 121                 fault:1,
 122                 stanby_fault:1,
 123                 disscrm:1,
 124                 b_only:1;
 125         uint8_t dc_connected:1,
 126                 max_port_speed:3,
 127                 lpp:1,
 128                 cable_speed:3;
 129         uint8_t connection_unreliable:1,
 130                 :3,
 131                 beta_mode:1,
 132                 :3;
 133         uint8_t port_error;
 134         uint8_t :5,
 135                 loop_disable:1,
 136                 in_standby:1,
 137                 hard_disable:1;
 138         uint8_t :8;
 139         uint8_t :8;
 140 #else
 141         uint8_t dis:1,
 142                 rxok:1,
 143                 con:1,
 144                 ch:1,
 145                 bstat:2,
 146                 astat:2;
 147         uint8_t b_only:1,
 148                 disscrm:1,
 149                 stanby_fault:1,
 150                 fault:1,
 151                 pie:1,
 152                 negotiated_speed:3;
 153         uint8_t cable_speed:3,
 154                 lpp:1,
 155                 max_port_speed:3,
 156                 dc_connected:1;
 157         uint8_t :3,
 158                 beta_mode:1,
 159                 :3,
 160                 connection_unreliable:1;
 161         uint8_t port_error;
 162         uint8_t hard_disable:1,
 163                 in_standby:1,
 164                 loop_disable:1,
 165                 :5;
 166         uint8_t :8;
 167         uint8_t :8;
 168 #endif
 169 };
 170
 171 /*
 172  * IEEE 1394a
 173  * Figure 5B - 3
 174  */
 175 struct phyreg_page1 {
 176         uint8_t compliance;
 177         uint8_t :8;
 178         uint8_t vendor_id[3];
 179         uint8_t product_id[3];
 180 };