btrfs: [] on the end of a struct field is a variable length array.
[haiku.git] / headers / private / graphics / radeon / fp_regs.h
blobe145173c830c2314bb8e809248b63126778a62e4
1 /*
2 Copyright (c) 2002, Thomas Kurschel
5 Part of Radeon driver
7 Flat Panel controller registers
8 */
10 #ifndef _FP_REGS_H
11 #define _FP_REGS_H
13 #define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250
14 #define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254
15 #define RADEON_FP_GEN_CNTL 0x0284
16 # define RADEON_FP_FPON (1 << 0)
17 # define RADEON_FP_TMDS_EN (1 << 2)
18 # define RADEON_FP_PANEL_FORMAT (1 << 3)
19 # define RADEON_FP_EN_TMDS (1 << 7)
20 # define RADEON_FP_DETECT_SENSE (1 << 8)
21 # define RADEON_FP_SEL_CRTC2 (1 << 13)
22 # define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
23 # define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
24 # define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
25 # define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)
26 # define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
27 # define RADEON_FP_DFP_SYNC_SEL (1 << 21)
28 # define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)
29 # define RADEON_FP_CRT_SYNC_SEL (1 << 23)
30 # define RADEON_FP_USE_SHADOW_EN (1 << 24)
31 # define RADEON_FP_CRT_SYNC_ALT (1 << 26)
32 #define RADEON_FP2_GEN_CNTL 0x0288
33 # define RADEON_FP2_BLANK_EN (1 << 1)
34 # define RADEON_FP2_FPON (1 << 2)
35 # define RADEON_FP2_PANEL_FORMAT (1 << 3)
36 # define RADEON_FP2_SOURCE_SEL_MASK (3 << 10)
37 # define RADEON_FP2_SOURCE_SEL_CRTC2 (1 << 10)
38 # define RADEON_FP2_SOURCE_SEL_RMX (2 << 10)
39 # define RADEON_FP2_SRC_SEL_MASK (3 << 13)
40 # define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)
41 # define RADEON_FP2_FP_POL (1 << 16)
42 # define RADEON_FP2_LP_POL (1 << 17)
43 # define RADEON_FP2_SCK_POL (1 << 18)
44 # define RADEON_FP2_LCD_CNTL_MASK (7 << 19)
45 # define RADEON_FP2_PAD_FLOP_EN (1 << 22)
46 # define RADEON_FP2_CRC_EN (1 << 23)
47 # define RADEON_FP2_CRC_READ_EN (1 << 24)
48 # define RADEON_FP2_DV0_EN (1 << 25)
49 # define RADEON_FP2_DV0_RATE_SEL_SDR (1 << 26)
50 #define RADEON_FP_HORZ_STRETCH 0x028c
51 # define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff
52 # define RADEON_HORZ_STRETCH_RATIO_MAX 4096
53 # define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)
54 # define RADEON_HORZ_PANEL_SIZE_SHIFT 16
55 # define RADEON_HORZ_STRETCH_PIXREP (0 << 25)
56 # define RADEON_HORZ_STRETCH_BLEND (1 << 26)
57 # define RADEON_HORZ_STRETCH_ENABLE (1 << 25)
58 # define RADEON_HORZ_AUTO_RATIO (1 << 27)
59 # define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)
60 # define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)
61 #define RADEON_FP_VERT_STRETCH 0x0290
62 # define RADEON_VERT_PANEL_SIZE (0xfff << 12)
63 # define RADEON_VERT_PANEL_SIZE_SHIFT 12
64 # define RADEON_VERT_STRETCH_RATIO_MASK 0xfff
65 # define RADEON_VERT_STRETCH_RATIO_SHIFT 0
66 # define RADEON_VERT_STRETCH_RATIO_MAX 4096
67 # define RADEON_VERT_STRETCH_ENABLE (1 << 25)
68 # define RADEON_VERT_STRETCH_LINEREP (0 << 26)
69 # define RADEON_VERT_STRETCH_BLEND (1 << 26)
70 # define RADEON_VERT_AUTO_RATIO_EN (1 << 27)
71 # define RADEON_VERT_STRETCH_RESERVED 0xf1000000
73 #define RADEON_TMDS_PLL_CNTL 0x02a8
74 #define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4
75 # define RADEON_TMDS_TRANSMITTER_PLLEN 1
76 # define RADEON_TMDS_TRANSMITTER_PLLRST 2
78 #define RADEON_FP_H_SYNC_STRT_WID 0x02c4
79 #define RADEON_FP_V_SYNC_STRT_WID 0x02c8
81 #define RADEON_LVDS_GEN_CNTL 0x02d0
82 # define RADEON_LVDS_ON (1 << 0)
83 # define RADEON_LVDS_DISPLAY_DIS (1 << 1)
84 # define RADEON_LVDS_PANEL_TYPE (1 << 2)
85 # define RADEON_LVDS_PANEL_FORMAT (1 << 3)
86 # define RADEON_LVDS_EN (1 << 7)
87 # define RADEON_LVDS_DIGON (1 << 18)
88 # define RADEON_LVDS_BLON (1 << 19)
89 # define RADEON_LVDS_SEL_CRTC2 (1 << 23)
90 #define RADEON_LVDS_PLL_CNTL 0x02d4
91 # define RADEON_HSYNC_DELAY_SHIFT 28
92 # define RADEON_HSYNC_DELAY_MASK (0xf << 28)
94 #define RADEON_FP_CRTC2_H_TOTAL_DISP 0x0350
95 #define RADEON_FP_CRTC2_V_TOTAL_DISP 0x0354
96 /*added for FP support------------------------------------------*/
97 # define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff
98 # define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000
99 # define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff
100 # define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000
101 # define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
102 # define RADEON_FP_H_SYNC_WID_MASK 0x003f0000
103 # define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff
104 # define RADEON_FP_V_SYNC_WID_MASK 0x001f0000
105 # define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000
106 # define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010
107 # define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000
108 # define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010
109 # define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
110 # define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010
111 # define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000
112 # define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010
113 /*-----------------------------------------------------------------*/
115 #define RADEON_FP_HORZ2_STRETCH 0x038c
116 #define RADEON_FP_VERT2_STRETCH 0x0390
117 #define RADEON_FP_H2_SYNC_STRT_WID 0x03c4
119 #define RADEON_FP_V2_SYNC_STRT_WID 0x03c8
121 #define RADEON_BIOS_0_SCRATCH 0x0010
122 #define RADEON_BIOS_1_SCRATCH 0x0014
123 #define RADEON_BIOS_2_SCRATCH 0x0018
124 #define RADEON_BIOS_3_SCRATCH 0x001c
125 #define RADEON_BIOS_4_SCRATCH 0x0020
126 #define RADEON_BIOS_5_SCRATCH 0x0024
127 #define RADEON_BIOS_6_SCRATCH 0x0028
128 #define RADEON_BIOS_7_SCRATCH 0x002c
130 #endif