headers/private/graphics/radeon/rbbm_regs.h

   1 /*
   2         Copyright (c) 2002, Thomas Kurschel
   3
   4
   5         Part of Radeon driver
   6
   7         Register Backbone Manager registers
   8 */
   9
  10 #ifndef _RBBM_REGS_H
  11 #define _RBBM_REGS_H
  12
  13 #define RADEON_GEN_INT_CNTL                 0x0040
  14 #               define RADEON_CRTC_VBLANK_MASK          (1 <<  0)
  15 #               define RADEON_CRTC2_VBLANK_MASK         (1 <<  9)
  16 #               define RADEON_GUIDMA_MASK                       (1 <<  30)
  17 #               define RADEON_VIDDMA_MASK                       (1 <<  31)
  18 #define RADEON_GEN_INT_STATUS               0x0044
  19 #               define RADEON_CRTC_VBLANK_STAT          (1 <<  0)
  20 #               define RADEON_CRTC_VBLANK_STAT_AK       (1 <<  0)
  21 #               define RADEON_CAP0_INT_ACTIVE           (1 <<  8)
  22 #               define RADEON_CRTC2_VBLANK_STAT         (1 <<  9)
  23 #               define RADEON_CRTC2_VBLANK_STAT_AK      (1 <<  9)
  24 #               define RADEON_GUIDMA_STAT                       (1 <<  30)
  25 #               define RADEON_GUIDMA_AK                         (1 <<  30)
  26 #               define RADEON_VIDDMA_STAT                       (1 <<  31)
  27 #               define RADEON_VIDDMA_AK                         (1 <<  31)
  28
  29 #define RADEON_CAP_INT_CNTL                                     0x0908
  30 #define RADEON_CAP_INT_STATUS                           0x090c
  31
  32 #define RADEON_RBBM_SOFT_RESET              0x00f0
  33 #       define RADEON_SOFT_RESET_CP           (1 <<  0)
  34 #       define RADEON_SOFT_RESET_HI           (1 <<  1)
  35 #       define RADEON_SOFT_RESET_SE           (1 <<  2)
  36 #       define RADEON_SOFT_RESET_RE           (1 <<  3)
  37 #       define RADEON_SOFT_RESET_PP           (1 <<  4)
  38 #       define RADEON_SOFT_RESET_E2           (1 <<  5)
  39 #       define RADEON_SOFT_RESET_RB           (1 <<  6)
  40 #       define RADEON_SOFT_RESET_HDP          (1 <<  7)
  41 #       define RADEON_SOFT_RESET_MC           (1 <<  8)
  42 #       define RADEON_SOFT_RESET_AIC          (1 <<  9)
  43
  44 #define RADEON_CRC_CMDFIFO_ADDR             0x0740
  45 #define RADEON_CRC_CMDFIFO_DOUT             0x0744
  46
  47 #define RADEON_RBBM_STATUS                  0x0e40
  48 #       define RADEON_RBBM_FIFOCNT_MASK     0x007f
  49 #       define RADEON_RBBM_ACTIVE           (1 << 31)
  50
  51 #define RADEON_WAIT_UNTIL                   0x1720
  52 #       define RADEON_WAIT_CRTC_PFLIP       (1 << 0)
  53 #       define RADEON_WAIT_2D_IDLECLEAN     (1 << 16)
  54 #       define RADEON_WAIT_3D_IDLECLEAN     (1 << 17)
  55 #       define RADEON_WAIT_HOST_IDLECLEAN   (1 << 18)
  56
  57 // these regs are only described for R200+
  58 // but they are used in the original Radeon SDK already
  59 #define RADEON_RB2D_DSTCACHE_CTLSTAT        0x342c
  60 #       define RADEON_RB2D_DC_FLUSH         (3 << 0)
  61 #       define RADEON_RB2D_DC_FREE          (3 << 2)
  62 #       define RADEON_RB2D_DC_FLUSH_ALL     0xf
  63 #       define RADEON_RB2D_DC_BUSY          (1 << 31)
  64 #define RADEON_RB2D_DSTCACHE_MODE           0x3428
  65
  66
  67 #endif