src/system/kernel/arch/m68k/paging/040/paging.h

   1 /*
   2  * Copyright 2010, Ingo Weinhold, ingo_weinhold@gmx.de.
   3  * Copyright 2005-2009, Axel Dörfler, axeld@pinc-software.de.
   4  * Distributed under the terms of the MIT License.
   5  *
   6  * Copyright 2001-2002, Travis Geiselbrecht. All rights reserved.
   7  * Distributed under the terms of the NewOS License.
   8  */
   9 #ifndef _KERNEL_ARCH_M68K_PAGING_040_PAGING_H
  10 #define _KERNEL_ARCH_M68K_PAGING_040_PAGING_H
  11
  12
  13 #include <SupportDefs.h>
  14
  15 #include <int.h>
  16 #include <kernel.h>
  17
  18 #include <arch_040_mmu.h>
  19
  20 /*  (mmu_man) Implementation details on 68030 and others:
  21
  22         Unlike on x86 we can't just switch the context to another team by just
  23         setting a register to another page directory, since we only have one
  24         page table containing both kernel and user address mappings.
  25         The 030 supports arbitrary layout of the page directory tree, including
  26         a 1-bit first level (2 entries top level table) that would map kernel
  27         and user land at a single place. But 040 and later only support a fixed
  28         splitting of 7/7/6 for 4K pages.
  29
  30         Since 68k SMP hardware is rare enough we don't want to support them, we
  31         can take some shortcuts.
  32
  33         As we don't want a separate user and kernel space, we'll use a single
  34         table. With the 7/7/6 split the 2nd level would require 32KB of tables,
  35         which is small enough to not want to use the list hack from x86.
  36         XXX: we use the hack for now, check later
  37
  38         Since page directories/tables don't fit exactly a page, we stuff more
  39         than one per page, and allocate them all at once, and add them at the
  40         same time to the tree. So we guarantee all higher-level entries modulo
  41         the number of tables/page are either invalid or present.
  42  */
  43
  44 // 4 MB of iospace
  45 ////#define IOSPACE_SIZE (4*1024*1024)
  46 //#define IOSPACE_SIZE (16*1024*1024)
  47 // 256K = 2^6*4K
  48 //#define IOSPACE_CHUNK_SIZE (NUM_PAGEENT_PER_TBL*B_PAGE_SIZE)
  49
  50 #define PAGE_INVALIDATE_CACHE_SIZE 64
  51
  52 #define FIRST_USER_PGROOT_ENT    (VADDR_TO_PRENT(USER_BASE))
  53 #define FIRST_USER_PGDIR_ENT    (VADDR_TO_PDENT(USER_BASE))
  54 #define NUM_USER_PGROOT_ENTS     (VADDR_TO_PRENT(ROUNDUP(USER_SIZE, B_PAGE_SIZE * 64 * 128)))
  55 #define NUM_USER_PGDIR_ENTS     (VADDR_TO_PDENT(ROUNDUP(USER_SIZE, B_PAGE_SIZE * 64)))
  56 #define FIRST_KERNEL_PGROOT_ENT  (VADDR_TO_PRENT(KERNEL_BASE))
  57 #define FIRST_KERNEL_PGDIR_ENT  (VADDR_TO_PDENT(KERNEL_BASE))
  58 #define NUM_KERNEL_PGROOT_ENTS   (VADDR_TO_PRENT(KERNEL_SIZE))
  59 #define NUM_KERNEL_PGDIR_ENTS   (VADDR_TO_PDENT(KERNEL_SIZE))
  60 //#define IS_KERNEL_MAP(map)            (map->arch_data->rtdir_phys == sKernelPhysicalPageRoot)
  61
  62
  63 // page tables are allocated as groups, so better use them all.
  64 static const size_t kPageTableAlignment = B_PAGE_SIZE
  65          * NUM_PAGETBL_PER_PAGE * NUM_PAGEENT_PER_TBL;
  66
  67 static const size_t kPageDirAlignment = B_PAGE_SIZE
  68         * NUM_PAGEENT_PER_TBL
  69         * NUM_DIRTBL_PER_PAGE * NUM_DIRENT_PER_TBL;
  70
  71
  72
  73 #if 0
  74
  75 #define VADDR_TO_PDENT(va) (((va) / B_PAGE_SIZE) / 1024)
  76 #define VADDR_TO_PTENT(va) (((va) / B_PAGE_SIZE) % 1024)
  77
  78
  79 // page directory entry bits
  80 #define M68K_PDE_PRESENT                                0x00000001
  81 #define M68K_PDE_WRITABLE                       0x00000002
  82 #define M68K_PDE_USER                           0x00000004
  83 #define M68K_PDE_WRITE_THROUGH          0x00000008
  84 #define M68K_PDE_CACHING_DISABLED       0x00000010
  85 #define M68K_PDE_ACCESSED                       0x00000020
  86 #define M68K_PDE_IGNORED1                       0x00000040
  87 #define M68K_PDE_RESERVED1                      0x00000080
  88 #define M68K_PDE_IGNORED2                       0x00000100
  89 #define M68K_PDE_IGNORED3                       0x00000200
  90 #define M68K_PDE_IGNORED4                       0x00000400
  91 #define M68K_PDE_IGNORED5                       0x00000800
  92 #define M68K_PDE_ADDRESS_MASK           0xfffff000
  93
  94 // page table entry bits
  95 #define M68K_PTE_PRESENT                                0x00000001
  96 #define M68K_PTE_WRITABLE                       0x00000002
  97 #define M68K_PTE_USER                           0x00000004
  98 #define M68K_PTE_WRITE_THROUGH          0x00000008
  99 #define M68K_PTE_CACHING_DISABLED       0x00000010
 100 #define M68K_PTE_ACCESSED                       0x00000020
 101 #define M68K_PTE_DIRTY                          0x00000040
 102 #define M68K_PTE_PAT                                    0x00000080
 103 #define M68K_PTE_GLOBAL                         0x00000100
 104 #define M68K_PTE_IGNORED1                       0x00000200
 105 #define M68K_PTE_IGNORED2                       0x00000400
 106 #define M68K_PTE_IGNORED3                       0x00000800
 107 #define M68K_PTE_ADDRESS_MASK           0xfffff000
 108 #define M68K_PTE_PROTECTION_MASK                (M68K_PTE_WRITABLE | M68K_PTE_USER)
 109 #define M68K_PTE_MEMORY_TYPE_MASK       (M68K_PTE_WRITE_THROUGH \
 110                                                                                 | M68K_PTE_CACHING_DISABLED)
 111
 112 #define FIRST_USER_PGDIR_ENT    (VADDR_TO_PDENT(USER_BASE))
 113 #define NUM_USER_PGDIR_ENTS     (VADDR_TO_PDENT(ROUNDUP(USER_SIZE, \
 114                                                                         B_PAGE_SIZE * 1024)))
 115 #define FIRST_KERNEL_PGDIR_ENT  (VADDR_TO_PDENT(KERNEL_BASE))
 116 #define NUM_KERNEL_PGDIR_ENTS   (VADDR_TO_PDENT(KERNEL_SIZE))
 117
 118
 119 static const size_t kPageTableAlignment = 1024 * B_PAGE_SIZE;
 120
 121
 122 typedef uint32 page_table_entry;
 123 typedef uint32 page_directory_entry;
 124
 125 #endif // 0
 126
 127 #endif  // _KERNEL_ARCH_M68K_PAGING_040_PAGING_H