uspace/drv/block/pci-ide/pci-ide.h

   1 /*
   2  * Copyright (c) 2024 Jiri Svoboda
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * - Redistributions of source code must retain the above copyright
  10  *   notice, this list of conditions and the following disclaimer.
  11  * - Redistributions in binary form must reproduce the above copyright
  12  *   notice, this list of conditions and the following disclaimer in the
  13  *   documentation and/or other materials provided with the distribution.
  14  * - The name of the author may not be used to endorse or promote products
  15  *   derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @addtogroup pci-ide
  30  * @{
  31  */
  32 /** @file PCI IDE driver definitions.
  33  */
  34
  35 #ifndef PCI_IDE_H
  36 #define PCI_IDE_H
  37
  38 #include <ata/ata.h>
  39 #include <ata/ata_hw.h>
  40 #include <ddf/driver.h>
  41 #include <fibril_synch.h>
  42 #include <stdbool.h>
  43 #include <stdint.h>
  44 #include "pci-ide_hw.h"
  45
  46 #define NAME "pci-ide"
  47
  48 /** PCI IDE hardware resources */
  49 typedef struct {
  50         uintptr_t bmregs; /** PCI Bus Master register block base address. */
  51         uintptr_t cmd1; /**< Primary channel command block base address. */
  52         uintptr_t ctl1; /**< Primary channel control block base address. */
  53         uintptr_t cmd2; /**< Secondary channel command block base address. */
  54         uintptr_t ctl2; /**< Secondary channel control block base address. */
  55         int irq1;       /**< Primary channel IRQ */
  56         int irq2;       /**< Secondary channel IRQ */
  57 } pci_ide_hwres_t;
  58
  59 /** PCI IDE channel */
  60 typedef struct pci_ide_channel {
  61         /** Parent controller */
  62         struct pci_ide_ctrl *ctrl;
  63         /** I/O base address of the command registers */
  64         uintptr_t cmd_physical;
  65         /** I/O base address of the control registers */
  66         uintptr_t ctl_physical;
  67
  68         /** Command registers */
  69         ata_cmd_t *cmd;
  70         /** Control registers */
  71         ata_ctl_t *ctl;
  72         /** IRQ (-1 if not used) */
  73         int irq;
  74         /** IRQ handle */
  75         cap_irq_handle_t ihandle;
  76
  77         /** Synchronize controller access */
  78         fibril_mutex_t lock;
  79         /** Value of status register read by interrupt handler */
  80         uint8_t irq_status;
  81
  82         /** Physical region descriptor table */
  83         pci_ide_prd_t *prdt;
  84         /** Physical region descriptor table physical address */
  85         uintptr_t prdt_pa;
  86         /** DMA buffer */
  87         void *dma_buf;
  88         /** DMA buffer physical address */
  89         uintptr_t dma_buf_pa;
  90         /** DMA buffer size */
  91         size_t dma_buf_size;
  92         /** Current DMA transfer direction */
  93         ata_dma_dir_t cur_dir;
  94         /** Current data buffer */
  95         void *cur_buf;
  96         /** Current data buffer size */
  97         size_t cur_buf_size;
  98
  99         /** Libata ATA channel */
 100         ata_channel_t *channel;
 101         struct pci_ide_fun *fun[2];
 102
 103         /** Channel ID */
 104         unsigned chan_id;
 105 } pci_ide_channel_t;
 106
 107 /** ISA IDE controller */
 108 typedef struct pci_ide_ctrl {
 109         /** DDF device */
 110         ddf_dev_t *dev;
 111
 112         /** I/O base address of bus master IDE registers */
 113         uintptr_t bmregs_physical;
 114         /** Bus master IDE registers */
 115         pci_ide_regs_t *bmregs;
 116         /** Primary and secondary channel */
 117         pci_ide_channel_t channel[2];
 118 } pci_ide_ctrl_t;
 119
 120 /** PCI IDE function */
 121 typedef struct pci_ide_fun {
 122         ddf_fun_t *fun;
 123         void *charg;
 124 } pci_ide_fun_t;
 125
 126 extern errno_t pci_ide_ctrl_init(pci_ide_ctrl_t *, pci_ide_hwres_t *);
 127 extern errno_t pci_ide_ctrl_fini(pci_ide_ctrl_t *);
 128 extern errno_t pci_ide_channel_init(pci_ide_ctrl_t *, pci_ide_channel_t *,
 129     unsigned, pci_ide_hwres_t *);
 130 extern errno_t pci_ide_channel_fini(pci_ide_channel_t *);
 131
 132 #endif
 133
 134 /** @}
 135  */