uspace/drv/block/pci-ide/pci-ide_hw.h

   1 /*
   2  * Copyright (c) 2024 Jiri Svoboda
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * - Redistributions of source code must retain the above copyright
  10  *   notice, this list of conditions and the following disclaimer.
  11  * - Redistributions in binary form must reproduce the above copyright
  12  *   notice, this list of conditions and the following disclaimer in the
  13  *   documentation and/or other materials provided with the distribution.
  14  * - The name of the author may not be used to endorse or promote products
  15  *   derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /** @addtogroup pci-ide
  30  * @{
  31  */
  32 /** @file PCI IDE hardware protocol (registers, data structures).
  33  *
  34  * Based on Intel 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) document.
  35  */
  36
  37 #ifndef PCI_IDE_HW_H
  38 #define PCI_IDE_HW_H
  39
  40 #include <stddef.h>
  41 #include <stdint.h>
  42
  43 /** PCI Bus Master IDE I/O Registers */
  44 typedef struct {
  45         /** Bus Master IDE Command (primary) */
  46         uint8_t bmicp;
  47         uint8_t rsvd1;
  48         /** Bus Master IDE Command (secondary) */
  49         uint8_t bmisp;
  50         uint8_t rsvd3;
  51         /** Bus Master IDE Descriptor Table Pointer (primary) */
  52         uint32_t bmidtpp;
  53         /** Bus Master IDE Status (secondary) */
  54         uint8_t bmics;
  55         uint8_t rsvd9;
  56         /** Bus Master IDE Status (secondary) */
  57         uint8_t bmiss;
  58         uint8_t rsvd11;
  59         /** Bus Master IDE Descriptor Table Pointer (secondary) */
  60         uint32_t bmidtps;
  61 } pci_ide_regs_t;
  62
  63 enum pci_ide_bmicx_bits {
  64         /** Bus Master Read/Write Control */
  65         bmicx_rwcon = 0x08,
  66         /** Start/Stop Bus Master */
  67         bmicx_ssbm = 0x01
  68 };
  69
  70 enum pci_ide_bmisx_bits {
  71         /** Drive 1 DMA Capable */
  72         bmisx_dma1cap = 0x40,
  73         /** Drive 0 DMA Capable */
  74         bmisx_dma0cap = 0x20,
  75         /** IDE Interrupte Status */
  76         bmisx_ideints = 0x04,
  77         /** IDE DMA Error */
  78         bmisx_idedmaerr = 0x02,
  79         /** Bus Master IDR Active */
  80         bmisx_bmidea = 0x01
  81 };
  82
  83 #define PCI_IDE_CFG_IDETIM 0x40
  84 #define PCI_IDE_CFG_SIDETIM 0x44
  85 #define PCI_IDE_CFG_UDMACTL 0x48
  86 #define PCI_IDE_CFG_UDMATIM 0x4a
  87
  88 /*
  89  * For PIIX we need to use ATA ports at fixed legacy ISA addresses.
  90  * There are no corresponding PCI I/O ranges and these adresses are
  91  * fixed and cannot be reconfigured.
  92  */
  93 enum {
  94         pci_ide_ata_cmd_p = 0x01f0,
  95         pci_ide_ata_ctl_p = 0x03f4,
  96         pci_ide_ata_cmd_s = 0x0170,
  97         pci_ide_ata_ctl_s = 0x0374
  98 };
  99
 100 enum {
 101         pci_ide_prd_eot = 0x8000
 102 };
 103
 104 /** PIIX physical region descriptor */
 105 typedef struct {
 106         /** Physical base address */
 107         uint32_t pba;
 108         /** Byte count */
 109         uint16_t bcnt;
 110         /** EOT / reserved */
 111         uint16_t eot_res;
 112 } pci_ide_prd_t;
 113
 114 #endif
 115
 116 /** @}
 117  */