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[NETFILTER]: ipt_TCPMSS: remove impossible condition
[hh.org.git] / drivers / scsi / ata_piix.c
bloba9bb3cb7e89b1f925c300c66390c5f897820a39c
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
83 */
84
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
94
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "2.00"
97
98 enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
103
104 PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108
109 /* combined mode. if set, PATA is channel 0.
110 * if clear, PATA is channel 1.
111 */
112 PIIX_PORT_ENABLED = (1 << 0),
113 PIIX_PORT_PRESENT = (1 << 4),
114
115 PIIX_80C_PRI = (1 << 5) | (1 << 4),
116 PIIX_80C_SEC = (1 << 7) | (1 << 6),
117
118 /* controller IDs */
119 piix4_pata = 0,
120 ich5_pata = 1,
121 ich5_sata = 2,
122 esb_sata = 3,
123 ich6_sata = 4,
124 ich6_sata_ahci = 5,
125 ich6m_sata_ahci = 6,
126 ich7m_sata_ahci = 7,
127 ich8_sata_ahci = 8,
128
129 /* constants for mapping table */
130 P0 = 0, /* port 0 */
131 P1 = 1, /* port 1 */
132 P2 = 2, /* port 2 */
133 P3 = 3, /* port 3 */
134 IDE = -1, /* IDE */
135 NA = -2, /* not avaliable */
136 RV = -3, /* reserved */
137
138 PIIX_AHCI_DEVICE = 6,
139 };
140
141 struct piix_map_db {
142 const u32 mask;
143 const u16 port_enable;
144 const int present_shift;
145 const int map[][4];
146 };
147
148 struct piix_host_priv {
149 const int *map;
150 const struct piix_map_db *map_db;
151 };
152
153 static int piix_init_one (struct pci_dev *pdev,
154 const struct pci_device_id *ent);
155 static void piix_host_stop(struct ata_host_set *host_set);
156 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
157 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
158 static void piix_pata_error_handler(struct ata_port *ap);
159 static void piix_sata_error_handler(struct ata_port *ap);
160
161 static unsigned int in_module_init = 1;
162
163 static const struct pci_device_id piix_pci_tbl[] = {
164 #ifdef ATA_ENABLE_PATA
165 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
166 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
167 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
168 { 0x8086, 0x27df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
169 #endif
170
171 /* NOTE: The following PCI ids must be kept in sync with the
172 * list in drivers/pci/quirks.c.
173 */
174
175 /* 82801EB (ICH5) */
176 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
177 /* 82801EB (ICH5) */
178 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
179 /* 6300ESB (ICH5 variant with broken PCS present bits) */
180 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
181 /* 6300ESB pretending RAID */
182 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
183 /* 82801FB/FW (ICH6/ICH6W) */
184 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
185 /* 82801FR/FRW (ICH6R/ICH6RW) */
186 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
187 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
188 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
189 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
190 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
191 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
192 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7m_sata_ahci },
193 /* Enterprise Southbridge 2 (where's the datasheet?) */
194 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
195 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
196 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
197 /* SATA Controller 2 IDE (ICH8, ditto) */
198 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
199 /* Mobile SATA Controller IDE (ICH8M, ditto) */
200 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
201
202 { } /* terminate list */
203 };
204
205 static struct pci_driver piix_pci_driver = {
206 .name = DRV_NAME,
207 .id_table = piix_pci_tbl,
208 .probe = piix_init_one,
209 .remove = ata_pci_remove_one,
210 .suspend = ata_pci_device_suspend,
211 .resume = ata_pci_device_resume,
212 };
213
214 static struct scsi_host_template piix_sht = {
215 .module = THIS_MODULE,
216 .name = DRV_NAME,
217 .ioctl = ata_scsi_ioctl,
218 .queuecommand = ata_scsi_queuecmd,
219 .can_queue = ATA_DEF_QUEUE,
220 .this_id = ATA_SHT_THIS_ID,
221 .sg_tablesize = LIBATA_MAX_PRD,
222 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
223 .emulated = ATA_SHT_EMULATED,
224 .use_clustering = ATA_SHT_USE_CLUSTERING,
225 .proc_name = DRV_NAME,
226 .dma_boundary = ATA_DMA_BOUNDARY,
227 .slave_configure = ata_scsi_slave_config,
228 .slave_destroy = ata_scsi_slave_destroy,
229 .bios_param = ata_std_bios_param,
230 .resume = ata_scsi_device_resume,
231 .suspend = ata_scsi_device_suspend,
232 };
233
234 static const struct ata_port_operations piix_pata_ops = {
235 .port_disable = ata_port_disable,
236 .set_piomode = piix_set_piomode,
237 .set_dmamode = piix_set_dmamode,
238 .mode_filter = ata_pci_default_filter,
239
240 .tf_load = ata_tf_load,
241 .tf_read = ata_tf_read,
242 .check_status = ata_check_status,
243 .exec_command = ata_exec_command,
244 .dev_select = ata_std_dev_select,
245
246 .bmdma_setup = ata_bmdma_setup,
247 .bmdma_start = ata_bmdma_start,
248 .bmdma_stop = ata_bmdma_stop,
249 .bmdma_status = ata_bmdma_status,
250 .qc_prep = ata_qc_prep,
251 .qc_issue = ata_qc_issue_prot,
252 .data_xfer = ata_pio_data_xfer,
253
254 .freeze = ata_bmdma_freeze,
255 .thaw = ata_bmdma_thaw,
256 .error_handler = piix_pata_error_handler,
257 .post_internal_cmd = ata_bmdma_post_internal_cmd,
258
259 .irq_handler = ata_interrupt,
260 .irq_clear = ata_bmdma_irq_clear,
261
262 .port_start = ata_port_start,
263 .port_stop = ata_port_stop,
264 .host_stop = piix_host_stop,
265 };
266
267 static const struct ata_port_operations piix_sata_ops = {
268 .port_disable = ata_port_disable,
269
270 .tf_load = ata_tf_load,
271 .tf_read = ata_tf_read,
272 .check_status = ata_check_status,
273 .exec_command = ata_exec_command,
274 .dev_select = ata_std_dev_select,
275
276 .bmdma_setup = ata_bmdma_setup,
277 .bmdma_start = ata_bmdma_start,
278 .bmdma_stop = ata_bmdma_stop,
279 .bmdma_status = ata_bmdma_status,
280 .qc_prep = ata_qc_prep,
281 .qc_issue = ata_qc_issue_prot,
282 .data_xfer = ata_pio_data_xfer,
283
284 .freeze = ata_bmdma_freeze,
285 .thaw = ata_bmdma_thaw,
286 .error_handler = piix_sata_error_handler,
287 .post_internal_cmd = ata_bmdma_post_internal_cmd,
288
289 .irq_handler = ata_interrupt,
290 .irq_clear = ata_bmdma_irq_clear,
291
292 .port_start = ata_port_start,
293 .port_stop = ata_port_stop,
294 .host_stop = piix_host_stop,
295 };
296
297 static const struct piix_map_db ich5_map_db = {
298 .mask = 0x7,
299 .port_enable = 0x3,
300 .present_shift = 4,
301 .map = {
302 /* PM PS SM SS MAP */
303 { P0, NA, P1, NA }, /* 000b */
304 { P1, NA, P0, NA }, /* 001b */
305 { RV, RV, RV, RV },
306 { RV, RV, RV, RV },
307 { P0, P1, IDE, IDE }, /* 100b */
308 { P1, P0, IDE, IDE }, /* 101b */
309 { IDE, IDE, P0, P1 }, /* 110b */
310 { IDE, IDE, P1, P0 }, /* 111b */
311 },
312 };
313
314 static const struct piix_map_db ich6_map_db = {
315 .mask = 0x3,
316 .port_enable = 0xf,
317 .present_shift = 4,
318 .map = {
319 /* PM PS SM SS MAP */
320 { P0, P2, P1, P3 }, /* 00b */
321 { IDE, IDE, P1, P3 }, /* 01b */
322 { P0, P2, IDE, IDE }, /* 10b */
323 { RV, RV, RV, RV },
324 },
325 };
326
327 static const struct piix_map_db ich6m_map_db = {
328 .mask = 0x3,
329 .port_enable = 0x5,
330 .present_shift = 4,
331 .map = {
332 /* PM PS SM SS MAP */
333 { P0, P2, RV, RV }, /* 00b */
334 { RV, RV, RV, RV },
335 { P0, P2, IDE, IDE }, /* 10b */
336 { RV, RV, RV, RV },
337 },
338 };
339
340 static const struct piix_map_db ich7m_map_db = {
341 .mask = 0x3,
342 .port_enable = 0x5,
343 .present_shift = 4,
344
345 /* Map 01b isn't specified in the doc but some notebooks use
346 * it anyway. ATM, the only case spotted carries subsystem ID
347 * 1025:0107. This is the only difference from ich6m.
348 */
349 .map = {
350 /* PM PS SM SS MAP */
351 { P0, P2, RV, RV }, /* 00b */
352 { IDE, IDE, P1, P3 }, /* 01b */
353 { P0, P2, IDE, IDE }, /* 10b */
354 { RV, RV, RV, RV },
355 },
356 };
357
358 static const struct piix_map_db ich8_map_db = {
359 .mask = 0x3,
360 .port_enable = 0x3,
361 .present_shift = 8,
362 .map = {
363 /* PM PS SM SS MAP */
364 { P0, NA, P1, NA }, /* 00b (hardwired) */
365 { RV, RV, RV, RV },
366 { RV, RV, RV, RV }, /* 10b (never) */
367 { RV, RV, RV, RV },
368 },
369 };
370
371 static const struct piix_map_db *piix_map_db_table[] = {
372 [ich5_sata] = &ich5_map_db,
373 [esb_sata] = &ich5_map_db,
374 [ich6_sata] = &ich6_map_db,
375 [ich6_sata_ahci] = &ich6_map_db,
376 [ich6m_sata_ahci] = &ich6m_map_db,
377 [ich7m_sata_ahci] = &ich7m_map_db,
378 [ich8_sata_ahci] = &ich8_map_db,
379 };
380
381 static struct ata_port_info piix_port_info[] = {
382 /* piix4_pata */
383 {
384 .sht = &piix_sht,
385 .host_flags = ATA_FLAG_SLAVE_POSS,
386 .pio_mask = 0x1f, /* pio0-4 */
387 #if 0
388 .mwdma_mask = 0x06, /* mwdma1-2 */
389 #else
390 .mwdma_mask = 0x00, /* mwdma broken */
391 #endif
392 .udma_mask = ATA_UDMA_MASK_40C,
393 .port_ops = &piix_pata_ops,
394 },
395
396 /* ich5_pata */
397 {
398 .sht = &piix_sht,
399 .host_flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
400 .pio_mask = 0x1f, /* pio0-4 */
401 #if 0
402 .mwdma_mask = 0x06, /* mwdma1-2 */
403 #else
404 .mwdma_mask = 0x00, /* mwdma broken */
405 #endif
406 .udma_mask = 0x3f, /* udma0-5 */
407 .port_ops = &piix_pata_ops,
408 },
409
410 /* ich5_sata */
411 {
412 .sht = &piix_sht,
413 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR |
414 PIIX_FLAG_IGNORE_PCS,
415 .pio_mask = 0x1f, /* pio0-4 */
416 .mwdma_mask = 0x07, /* mwdma0-2 */
417 .udma_mask = 0x7f, /* udma0-6 */
418 .port_ops = &piix_sata_ops,
419 },
420
421 /* i6300esb_sata */
422 {
423 .sht = &piix_sht,
424 .host_flags = ATA_FLAG_SATA |
425 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS,
426 .pio_mask = 0x1f, /* pio0-4 */
427 .mwdma_mask = 0x07, /* mwdma0-2 */
428 .udma_mask = 0x7f, /* udma0-6 */
429 .port_ops = &piix_sata_ops,
430 },
431
432 /* ich6_sata */
433 {
434 .sht = &piix_sht,
435 .host_flags = ATA_FLAG_SATA |
436 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR,
437 .pio_mask = 0x1f, /* pio0-4 */
438 .mwdma_mask = 0x07, /* mwdma0-2 */
439 .udma_mask = 0x7f, /* udma0-6 */
440 .port_ops = &piix_sata_ops,
441 },
442
443 /* ich6_sata_ahci */
444 {
445 .sht = &piix_sht,
446 .host_flags = ATA_FLAG_SATA |
447 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
448 PIIX_FLAG_AHCI,
449 .pio_mask = 0x1f, /* pio0-4 */
450 .mwdma_mask = 0x07, /* mwdma0-2 */
451 .udma_mask = 0x7f, /* udma0-6 */
452 .port_ops = &piix_sata_ops,
453 },
454
455 /* ich6m_sata_ahci */
456 {
457 .sht = &piix_sht,
458 .host_flags = ATA_FLAG_SATA |
459 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
460 PIIX_FLAG_AHCI,
461 .pio_mask = 0x1f, /* pio0-4 */
462 .mwdma_mask = 0x07, /* mwdma0-2 */
463 .udma_mask = 0x7f, /* udma0-6 */
464 .port_ops = &piix_sata_ops,
465 },
466
467 /* ich7m_sata_ahci */
468 {
469 .sht = &piix_sht,
470 .host_flags = ATA_FLAG_SATA |
471 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
472 PIIX_FLAG_AHCI,
473 .pio_mask = 0x1f, /* pio0-4 */
474 .mwdma_mask = 0x07, /* mwdma0-2 */
475 .udma_mask = 0x7f, /* udma0-6 */
476 .port_ops = &piix_sata_ops,
477 },
478
479 /* ich8_sata_ahci */
480 {
481 .sht = &piix_sht,
482 .host_flags = ATA_FLAG_SATA |
483 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
484 PIIX_FLAG_AHCI,
485 .pio_mask = 0x1f, /* pio0-4 */
486 .mwdma_mask = 0x07, /* mwdma0-2 */
487 .udma_mask = 0x7f, /* udma0-6 */
488 .port_ops = &piix_sata_ops,
489 },
490 };
491
492 static struct pci_bits piix_enable_bits[] = {
493 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
494 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
495 };
496
497 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
498 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
499 MODULE_LICENSE("GPL");
500 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
501 MODULE_VERSION(DRV_VERSION);
502
503 static int force_pcs = 0;
504 module_param(force_pcs, int, 0444);
505 MODULE_PARM_DESC(force_pcs, "force honoring or ignoring PCS to work around "
506 "device mis-detection (0=default, 1=ignore PCS, 2=honor PCS)");
507
508 /**
509 * piix_pata_cbl_detect - Probe host controller cable detect info
510 * @ap: Port for which cable detect info is desired
511 *
512 * Read 80c cable indicator from ATA PCI device's PCI config
513 * register. This register is normally set by firmware (BIOS).
514 *
515 * LOCKING:
516 * None (inherited from caller).
517 */
518 static void piix_pata_cbl_detect(struct ata_port *ap)
519 {
520 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
521 u8 tmp, mask;
522
523 /* no 80c support in host controller? */
524 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
525 goto cbl40;
526
527 /* check BIOS cable detect results */
528 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
529 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
530 if ((tmp & mask) == 0)
531 goto cbl40;
532
533 ap->cbl = ATA_CBL_PATA80;
534 return;
535
536 cbl40:
537 ap->cbl = ATA_CBL_PATA40;
538 ap->udma_mask &= ATA_UDMA_MASK_40C;
539 }
540
541 /**
542 * piix_pata_prereset - prereset for PATA host controller
543 * @ap: Target port
544 *
545 * Prereset including cable detection.
546 *
547 * LOCKING:
548 * None (inherited from caller).
549 */
550 static int piix_pata_prereset(struct ata_port *ap)
551 {
552 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
553
554 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
555 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
556 ap->eh_context.i.action &= ~ATA_EH_RESET_MASK;
557 return 0;
558 }
559
560 piix_pata_cbl_detect(ap);
561
562 return ata_std_prereset(ap);
563 }
564
565 static void piix_pata_error_handler(struct ata_port *ap)
566 {
567 ata_bmdma_drive_eh(ap, piix_pata_prereset, ata_std_softreset, NULL,
568 ata_std_postreset);
569 }
570
571 /**
572 * piix_sata_present_mask - determine present mask for SATA host controller
573 * @ap: Target port
574 *
575 * Reads SATA PCI device's PCI config register Port Configuration
576 * and Status (PCS) to determine port and device availability.
577 *
578 * LOCKING:
579 * None (inherited from caller).
580 *
581 * RETURNS:
582 * determined present_mask
583 */
584 static unsigned int piix_sata_present_mask(struct ata_port *ap)
585 {
586 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
587 struct piix_host_priv *hpriv = ap->host_set->private_data;
588 const unsigned int *map = hpriv->map;
589 int base = 2 * ap->hard_port_no;
590 unsigned int present_mask = 0;
591 int port, i;
592 u16 pcs;
593
594 pci_read_config_word(pdev, ICH5_PCS, &pcs);
595 DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base);
596
597 for (i = 0; i < 2; i++) {
598 port = map[base + i];
599 if (port < 0)
600 continue;
601 if ((ap->flags & PIIX_FLAG_IGNORE_PCS) ||
602 (pcs & 1 << (hpriv->map_db->present_shift + port)))
603 present_mask |= 1 << i;
604 }
605
606 DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n",
607 ap->id, pcs, present_mask);
608
609 return present_mask;
610 }
611
612 /**
613 * piix_sata_softreset - reset SATA host port via ATA SRST
614 * @ap: port to reset
615 * @classes: resulting classes of attached devices
616 *
617 * Reset SATA host port via ATA SRST. On controllers with
618 * reliable PCS present bits, the bits are used to determine
619 * device presence.
620 *
621 * LOCKING:
622 * Kernel thread context (may sleep)
623 *
624 * RETURNS:
625 * 0 on success, -errno otherwise.
626 */
627 static int piix_sata_softreset(struct ata_port *ap, unsigned int *classes)
628 {
629 unsigned int present_mask;
630 int i, rc;
631
632 present_mask = piix_sata_present_mask(ap);
633
634 rc = ata_std_softreset(ap, classes);
635 if (rc)
636 return rc;
637
638 for (i = 0; i < ATA_MAX_DEVICES; i++) {
639 if (!(present_mask & (1 << i)))
640 classes[i] = ATA_DEV_NONE;
641 }
642
643 return 0;
644 }
645
646 static void piix_sata_error_handler(struct ata_port *ap)
647 {
648 ata_bmdma_drive_eh(ap, ata_std_prereset, piix_sata_softreset, NULL,
649 ata_std_postreset);
650 }
651
652 /**
653 * piix_set_piomode - Initialize host controller PATA PIO timings
654 * @ap: Port whose timings we are configuring
655 * @adev: um
656 *
657 * Set PIO mode for device, in host controller PCI config space.
658 *
659 * LOCKING:
660 * None (inherited from caller).
661 */
662
663 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
664 {
665 unsigned int pio = adev->pio_mode - XFER_PIO_0;
666 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
667 unsigned int is_slave = (adev->devno != 0);
668 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
669 unsigned int slave_port = 0x44;
670 u16 master_data;
671 u8 slave_data;
672
673 static const /* ISP RTC */
674 u8 timings[][2] = { { 0, 0 },
675 { 0, 0 },
676 { 1, 0 },
677 { 2, 1 },
678 { 2, 3 }, };
679
680 pci_read_config_word(dev, master_port, &master_data);
681 if (is_slave) {
682 master_data |= 0x4000;
683 /* enable PPE, IE and TIME */
684 master_data |= 0x0070;
685 pci_read_config_byte(dev, slave_port, &slave_data);
686 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
687 slave_data |=
688 (timings[pio][0] << 2) |
689 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
690 } else {
691 master_data &= 0xccf8;
692 /* enable PPE, IE and TIME */
693 master_data |= 0x0007;
694 master_data |=
695 (timings[pio][0] << 12) |
696 (timings[pio][1] << 8);
697 }
698 pci_write_config_word(dev, master_port, master_data);
699 if (is_slave)
700 pci_write_config_byte(dev, slave_port, slave_data);
701 }
702
703 /**
704 * piix_set_dmamode - Initialize host controller PATA PIO timings
705 * @ap: Port whose timings we are configuring
706 * @adev: um
707 * @udma: udma mode, 0 - 6
708 *
709 * Set UDMA mode for device, in host controller PCI config space.
710 *
711 * LOCKING:
712 * None (inherited from caller).
713 */
714
715 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
716 {
717 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
718 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
719 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
720 u8 speed = udma;
721 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
722 int a_speed = 3 << (drive_dn * 4);
723 int u_flag = 1 << drive_dn;
724 int v_flag = 0x01 << drive_dn;
725 int w_flag = 0x10 << drive_dn;
726 int u_speed = 0;
727 int sitre;
728 u16 reg4042, reg4a;
729 u8 reg48, reg54, reg55;
730
731 pci_read_config_word(dev, maslave, &reg4042);
732 DPRINTK("reg4042 = 0x%04x\n", reg4042);
733 sitre = (reg4042 & 0x4000) ? 1 : 0;
734 pci_read_config_byte(dev, 0x48, &reg48);
735 pci_read_config_word(dev, 0x4a, &reg4a);
736 pci_read_config_byte(dev, 0x54, &reg54);
737 pci_read_config_byte(dev, 0x55, &reg55);
738
739 switch(speed) {
740 case XFER_UDMA_4:
741 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
742 case XFER_UDMA_6:
743 case XFER_UDMA_5:
744 case XFER_UDMA_3:
745 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
746 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
747 case XFER_MW_DMA_2:
748 case XFER_MW_DMA_1: break;
749 default:
750 BUG();
751 return;
752 }
753
754 if (speed >= XFER_UDMA_0) {
755 if (!(reg48 & u_flag))
756 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
757 if (speed == XFER_UDMA_5) {
758 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
759 } else {
760 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
761 }
762 if ((reg4a & a_speed) != u_speed)
763 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
764 if (speed > XFER_UDMA_2) {
765 if (!(reg54 & v_flag))
766 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
767 } else
768 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
769 } else {
770 if (reg48 & u_flag)
771 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
772 if (reg4a & a_speed)
773 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
774 if (reg54 & v_flag)
775 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
776 if (reg55 & w_flag)
777 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
778 }
779 }
780
781 #define AHCI_PCI_BAR 5
782 #define AHCI_GLOBAL_CTL 0x04
783 #define AHCI_ENABLE (1 << 31)
784 static int piix_disable_ahci(struct pci_dev *pdev)
785 {
786 void __iomem *mmio;
787 u32 tmp;
788 int rc = 0;
789
790 /* BUG: pci_enable_device has not yet been called. This
791 * works because this device is usually set up by BIOS.
792 */
793
794 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
795 !pci_resource_len(pdev, AHCI_PCI_BAR))
796 return 0;
797
798 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
799 if (!mmio)
800 return -ENOMEM;
801
802 tmp = readl(mmio + AHCI_GLOBAL_CTL);
803 if (tmp & AHCI_ENABLE) {
804 tmp &= ~AHCI_ENABLE;
805 writel(tmp, mmio + AHCI_GLOBAL_CTL);
806
807 tmp = readl(mmio + AHCI_GLOBAL_CTL);
808 if (tmp & AHCI_ENABLE)
809 rc = -EIO;
810 }
811
812 pci_iounmap(pdev, mmio);
813 return rc;
814 }
815
816 /**
817 * piix_check_450nx_errata - Check for problem 450NX setup
818 * @ata_dev: the PCI device to check
819 *
820 * Check for the present of 450NX errata #19 and errata #25. If
821 * they are found return an error code so we can turn off DMA
822 */
823
824 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
825 {
826 struct pci_dev *pdev = NULL;
827 u16 cfg;
828 u8 rev;
829 int no_piix_dma = 0;
830
831 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
832 {
833 /* Look for 450NX PXB. Check for problem configurations
834 A PCI quirk checks bit 6 already */
835 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
836 pci_read_config_word(pdev, 0x41, &cfg);
837 /* Only on the original revision: IDE DMA can hang */
838 if (rev == 0x00)
839 no_piix_dma = 1;
840 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
841 else if (cfg & (1<<14) && rev < 5)
842 no_piix_dma = 2;
843 }
844 if (no_piix_dma)
845 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
846 if (no_piix_dma == 2)
847 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
848 return no_piix_dma;
849 }
850
851 static void __devinit piix_init_pcs(struct pci_dev *pdev,
852 struct ata_port_info *pinfo,
853 const struct piix_map_db *map_db)
854 {
855 u16 pcs, new_pcs;
856
857 pci_read_config_word(pdev, ICH5_PCS, &pcs);
858
859 new_pcs = pcs | map_db->port_enable;
860
861 if (new_pcs != pcs) {
862 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
863 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
864 msleep(150);
865 }
866
867 if (force_pcs == 1) {
868 dev_printk(KERN_INFO, &pdev->dev,
869 "force ignoring PCS (0x%x)\n", new_pcs);
870 pinfo[0].host_flags |= PIIX_FLAG_IGNORE_PCS;
871 pinfo[1].host_flags |= PIIX_FLAG_IGNORE_PCS;
872 } else if (force_pcs == 2) {
873 dev_printk(KERN_INFO, &pdev->dev,
874 "force honoring PCS (0x%x)\n", new_pcs);
875 pinfo[0].host_flags &= ~PIIX_FLAG_IGNORE_PCS;
876 pinfo[1].host_flags &= ~PIIX_FLAG_IGNORE_PCS;
877 }
878 }
879
880 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
881 struct ata_port_info *pinfo,
882 const struct piix_map_db *map_db)
883 {
884 struct piix_host_priv *hpriv = pinfo[0].private_data;
885 const unsigned int *map;
886 int i, invalid_map = 0;
887 u8 map_value;
888
889 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
890
891 map = map_db->map[map_value & map_db->mask];
892
893 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
894 for (i = 0; i < 4; i++) {
895 switch (map[i]) {
896 case RV:
897 invalid_map = 1;
898 printk(" XX");
899 break;
900
901 case NA:
902 printk(" --");
903 break;
904
905 case IDE:
906 WARN_ON((i & 1) || map[i + 1] != IDE);
907 pinfo[i / 2] = piix_port_info[ich5_pata];
908 pinfo[i / 2].private_data = hpriv;
909 i++;
910 printk(" IDE IDE");
911 break;
912
913 default:
914 printk(" P%d", map[i]);
915 if (i & 1)
916 pinfo[i / 2].host_flags |= ATA_FLAG_SLAVE_POSS;
917 break;
918 }
919 }
920 printk(" ]\n");
921
922 if (invalid_map)
923 dev_printk(KERN_ERR, &pdev->dev,
924 "invalid MAP value %u\n", map_value);
925
926 hpriv->map = map;
927 hpriv->map_db = map_db;
928 }
929
930 /**
931 * piix_init_one - Register PIIX ATA PCI device with kernel services
932 * @pdev: PCI device to register
933 * @ent: Entry in piix_pci_tbl matching with @pdev
934 *
935 * Called from kernel PCI layer. We probe for combined mode (sigh),
936 * and then hand over control to libata, for it to do the rest.
937 *
938 * LOCKING:
939 * Inherited from PCI layer (may sleep).
940 *
941 * RETURNS:
942 * Zero on success, or -ERRNO value.
943 */
944
945 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
946 {
947 static int printed_version;
948 struct ata_port_info port_info[2];
949 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
950 struct piix_host_priv *hpriv;
951 unsigned long host_flags;
952
953 if (!printed_version++)
954 dev_printk(KERN_DEBUG, &pdev->dev,
955 "version " DRV_VERSION "\n");
956
957 /* no hotplugging support (FIXME) */
958 if (!in_module_init)
959 return -ENODEV;
960
961 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
962 if (!hpriv)
963 return -ENOMEM;
964
965 port_info[0] = piix_port_info[ent->driver_data];
966 port_info[1] = piix_port_info[ent->driver_data];
967 port_info[0].private_data = hpriv;
968 port_info[1].private_data = hpriv;
969
970 host_flags = port_info[0].host_flags;
971
972 if (host_flags & PIIX_FLAG_AHCI) {
973 u8 tmp;
974 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
975 if (tmp == PIIX_AHCI_DEVICE) {
976 int rc = piix_disable_ahci(pdev);
977 if (rc)
978 return rc;
979 }
980 }
981
982 /* Initialize SATA map */
983 if (host_flags & ATA_FLAG_SATA) {
984 piix_init_sata_map(pdev, port_info,
985 piix_map_db_table[ent->driver_data]);
986 piix_init_pcs(pdev, port_info,
987 piix_map_db_table[ent->driver_data]);
988 }
989
990 /* On ICH5, some BIOSen disable the interrupt using the
991 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
992 * On ICH6, this bit has the same effect, but only when
993 * MSI is disabled (and it is disabled, as we don't use
994 * message-signalled interrupts currently).
995 */
996 if (host_flags & PIIX_FLAG_CHECKINTR)
997 pci_intx(pdev, 1);
998
999 if (piix_check_450nx_errata(pdev)) {
1000 /* This writes into the master table but it does not
1001 really matter for this errata as we will apply it to
1002 all the PIIX devices on the board */
1003 port_info[0].mwdma_mask = 0;
1004 port_info[0].udma_mask = 0;
1005 port_info[1].mwdma_mask = 0;
1006 port_info[1].udma_mask = 0;
1007 }
1008 return ata_pci_init_one(pdev, ppinfo, 2);
1009 }
1010
1011 static void piix_host_stop(struct ata_host_set *host_set)
1012 {
1013 if (host_set->next == NULL)
1014 kfree(host_set->private_data);
1015 ata_host_stop(host_set);
1016 }
1017
1018 static int __init piix_init(void)
1019 {
1020 int rc;
1021
1022 DPRINTK("pci_module_init\n");
1023 rc = pci_module_init(&piix_pci_driver);
1024 if (rc)
1025 return rc;
1026
1027 in_module_init = 0;
1028
1029 DPRINTK("done\n");
1030 return 0;
1031 }
1032
1033 static void __exit piix_exit(void)
1034 {
1035 pci_unregister_driver(&piix_pci_driver);
1036 }
1037
1038 module_init(piix_init);
1039 module_exit(piix_exit);
1040
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