include/asm-mips/tx4938/rbtx4938.h

   1 /*
   2  * linux/include/asm-mips/tx4938/rbtx4938.h
   3  * Definitions for TX4937/TX4938
   4  *
   5  * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
   6  * terms of the GNU General Public License version 2. This program is
   7  * licensed "as is" without any warranty of any kind, whether express
   8  * or implied.
   9  *
  10  * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  11  */
  12 #ifndef __ASM_TX_BOARDS_RBTX4938_H
  13 #define __ASM_TX_BOARDS_RBTX4938_H
  14
  15 #include <asm/addrspace.h>
  16 #include <asm/tx4938/tx4938.h>
  17
  18 /* CS */
  19 #define RBTX4938_CE0    0x1c000000      /* 64M */
  20 #define RBTX4938_CE2    0x17f00000      /* 1M */
  21
  22 /* Address map */
  23 #define RBTX4938_FPGA_REG_ADDR  (KSEG1 + RBTX4938_CE2 + 0x00000000)
  24 #define RBTX4938_FPGA_REV_ADDR  (KSEG1 + RBTX4938_CE2 + 0x00000002)
  25 #define RBTX4938_CONFIG1_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00000004)
  26 #define RBTX4938_CONFIG2_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00000006)
  27 #define RBTX4938_CONFIG3_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00000008)
  28 #define RBTX4938_LED_ADDR       (KSEG1 + RBTX4938_CE2 + 0x00001000)
  29 #define RBTX4938_DIPSW_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00001002)
  30 #define RBTX4938_BDIPSW_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00001004)
  31 #define RBTX4938_IMASK_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00002000)
  32 #define RBTX4938_IMASK2_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00002002)
  33 #define RBTX4938_INTPOL_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00002004)
  34 #define RBTX4938_ISTAT_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00002006)
  35 #define RBTX4938_ISTAT2_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00002008)
  36 #define RBTX4938_IMSTAT_ADDR    (KSEG1 + RBTX4938_CE2 + 0x0000200a)
  37 #define RBTX4938_IMSTAT2_ADDR   (KSEG1 + RBTX4938_CE2 + 0x0000200c)
  38 #define RBTX4938_SOFTINT_ADDR   (KSEG1 + RBTX4938_CE2 + 0x00003000)
  39 #define RBTX4938_PIOSEL_ADDR    (KSEG1 + RBTX4938_CE2 + 0x00005000)
  40 #define RBTX4938_SPICS_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00005002)
  41 #define RBTX4938_SFPWR_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00005008)
  42 #define RBTX4938_SFVOL_ADDR     (KSEG1 + RBTX4938_CE2 + 0x0000500a)
  43 #define RBTX4938_SOFTRESET_ADDR (KSEG1 + RBTX4938_CE2 + 0x00007000)
  44 #define RBTX4938_SOFTRESETLOCK_ADDR     (KSEG1 + RBTX4938_CE2 + 0x00007002)
  45 #define RBTX4938_PCIRESET_ADDR  (KSEG1 + RBTX4938_CE2 + 0x00007004)
  46 #define RBTX4938_ETHER_BASE     (KSEG1 + RBTX4938_CE2 + 0x00020000)
  47
  48 /* Ethernet port address (Jumperless Mode (W12:Open)) */
  49 #define RBTX4938_ETHER_ADDR     (RBTX4938_ETHER_BASE + 0x280)
  50
  51 /* bits for ISTAT/IMASK/IMSTAT */
  52 #define RBTX4938_INTB_PCID      0
  53 #define RBTX4938_INTB_PCIC      1
  54 #define RBTX4938_INTB_PCIB      2
  55 #define RBTX4938_INTB_PCIA      3
  56 #define RBTX4938_INTB_RTC       4
  57 #define RBTX4938_INTB_ATA       5
  58 #define RBTX4938_INTB_MODEM     6
  59 #define RBTX4938_INTB_SWINT     7
  60 #define RBTX4938_INTF_PCID      (1 << RBTX4938_INTB_PCID)
  61 #define RBTX4938_INTF_PCIC      (1 << RBTX4938_INTB_PCIC)
  62 #define RBTX4938_INTF_PCIB      (1 << RBTX4938_INTB_PCIB)
  63 #define RBTX4938_INTF_PCIA      (1 << RBTX4938_INTB_PCIA)
  64 #define RBTX4938_INTF_RTC       (1 << RBTX4938_INTB_RTC)
  65 #define RBTX4938_INTF_ATA       (1 << RBTX4938_INTB_ATA)
  66 #define RBTX4938_INTF_MODEM     (1 << RBTX4938_INTB_MODEM)
  67 #define RBTX4938_INTF_SWINT     (1 << RBTX4938_INTB_SWINT)
  68
  69 #define rbtx4938_fpga_rev_ptr   \
  70         ((volatile unsigned char *)RBTX4938_FPGA_REV_ADDR)
  71 #define rbtx4938_led_ptr        \
  72         ((volatile unsigned char *)RBTX4938_LED_ADDR)
  73 #define rbtx4938_dipsw_ptr      \
  74         ((volatile unsigned char *)RBTX4938_DIPSW_ADDR)
  75 #define rbtx4938_bdipsw_ptr     \
  76         ((volatile unsigned char *)RBTX4938_BDIPSW_ADDR)
  77 #define rbtx4938_imask_ptr      \
  78         ((volatile unsigned char *)RBTX4938_IMASK_ADDR)
  79 #define rbtx4938_imask2_ptr     \
  80         ((volatile unsigned char *)RBTX4938_IMASK2_ADDR)
  81 #define rbtx4938_intpol_ptr     \
  82         ((volatile unsigned char *)RBTX4938_INTPOL_ADDR)
  83 #define rbtx4938_istat_ptr      \
  84         ((volatile unsigned char *)RBTX4938_ISTAT_ADDR)
  85 #define rbtx4938_istat2_ptr     \
  86         ((volatile unsigned char *)RBTX4938_ISTAT2_ADDR)
  87 #define rbtx4938_imstat_ptr     \
  88         ((volatile unsigned char *)RBTX4938_IMSTAT_ADDR)
  89 #define rbtx4938_imstat2_ptr    \
  90         ((volatile unsigned char *)RBTX4938_IMSTAT2_ADDR)
  91 #define rbtx4938_softint_ptr    \
  92         ((volatile unsigned char *)RBTX4938_SOFTINT_ADDR)
  93 #define rbtx4938_piosel_ptr     \
  94         ((volatile unsigned char *)RBTX4938_PIOSEL_ADDR)
  95 #define rbtx4938_spics_ptr      \
  96         ((volatile unsigned char *)RBTX4938_SPICS_ADDR)
  97 #define rbtx4938_sfpwr_ptr      \
  98         ((volatile unsigned char *)RBTX4938_SFPWR_ADDR)
  99 #define rbtx4938_sfvol_ptr      \
 100         ((volatile unsigned char *)RBTX4938_SFVOL_ADDR)
 101 #define rbtx4938_softreset_ptr  \
 102         ((volatile unsigned char *)RBTX4938_SOFTRESET_ADDR)
 103 #define rbtx4938_softresetlock_ptr      \
 104         ((volatile unsigned char *)RBTX4938_SOFTRESETLOCK_ADDR)
 105 #define rbtx4938_pcireset_ptr   \
 106         ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR)
 107
 108 /* SPI */
 109 #define RBTX4938_SEEPROM1_CHIPID        0
 110 #define RBTX4938_SEEPROM2_CHIPID        1
 111 #define RBTX4938_SEEPROM3_CHIPID        2
 112 #define RBTX4938_SRTC_CHIPID    3
 113
 114 /*
 115  * IRQ mappings
 116  */
 117
 118 #define RBTX4938_SOFT_INT0      0       /* not used */
 119 #define RBTX4938_SOFT_INT1      1       /* not used */
 120 #define RBTX4938_IRC_INT        2
 121 #define RBTX4938_TIMER_INT      7
 122
 123 /* These are the virtual IRQ numbers, we divide all IRQ's into
 124  * 'spaces', the 'space' determines where and how to enable/disable
 125  * that particular IRQ on an RBTX4938 machine.  Add new 'spaces' as new
 126  * IRQ hardware is supported.
 127  */
 128 #define RBTX4938_NR_IRQ_LOCAL   8
 129 #define RBTX4938_NR_IRQ_IRC     32      /* On-Chip IRC */
 130 #define RBTX4938_NR_IRQ_IOC     8
 131
 132 #define MI8259_IRQ_ISA_RAW_BEG   0      /* optional backplane i8259 */
 133 #define MI8259_IRQ_ISA_RAW_END  15
 134 #define TX4938_IRQ_CP0_RAW_BEG   0      /* tx4938 cpu built-in cp0 */
 135 #define TX4938_IRQ_CP0_RAW_END   7
 136 #define TX4938_IRQ_PIC_RAW_BEG   0      /* tx4938 cpu build-in pic */
 137 #define TX4938_IRQ_PIC_RAW_END  31
 138
 139 #define MI8259_IRQ_ISA_BEG                          MI8259_IRQ_ISA_RAW_BEG      /*  0 */
 140 #define MI8259_IRQ_ISA_END                          MI8259_IRQ_ISA_RAW_END      /* 15 */
 141
 142 #define TX4938_IRQ_CP0_BEG  ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG)     /* 16 */
 143 #define TX4938_IRQ_CP0_END  ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END)     /* 23 */
 144
 145 #define TX4938_IRQ_PIC_BEG  ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG)     /* 24 */
 146 #define TX4938_IRQ_PIC_END  ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END)     /* 55 */
 147 #define TX4938_IRQ_NEST_EXT_ON_PIC  (TX4938_IRQ_PIC_BEG+2)
 148 #define TX4938_IRQ_NEST_PIC_ON_CP0  (TX4938_IRQ_CP0_BEG+2)
 149 #define TX4938_IRQ_USER0            (TX4938_IRQ_CP0_BEG+0)
 150 #define TX4938_IRQ_USER1            (TX4938_IRQ_CP0_BEG+1)
 151 #define TX4938_IRQ_CPU_TIMER        (TX4938_IRQ_CP0_BEG+7)
 152
 153 #define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG   0
 154 #define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END   7
 155
 156 #define TOSHIBA_RBTX4938_IRQ_IOC_BEG  ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */
 157 #define TOSHIBA_RBTX4938_IRQ_IOC_END  ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */
 158 #define RBTX4938_IRQ_LOCAL      TX4938_IRQ_CP0_BEG
 159 #define RBTX4938_IRQ_IRC        (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL)
 160 #define RBTX4938_IRQ_IOC        (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC)
 161 #define RBTX4938_IRQ_END        (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
 162
 163 #define RBTX4938_IRQ_LOCAL_SOFT0        (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0)
 164 #define RBTX4938_IRQ_LOCAL_SOFT1        (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1)
 165 #define RBTX4938_IRQ_LOCAL_IRC  (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT)
 166 #define RBTX4938_IRQ_LOCAL_TIMER        (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT)
 167 #define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
 168 #define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
 169 #define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
 170 #define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
 171 #define RBTX4938_IRQ_IRC_DMA(ch,n)      (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch,n))
 172 #define RBTX4938_IRQ_IRC_PIO    (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
 173 #define RBTX4938_IRQ_IRC_PDMAC  (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
 174 #define RBTX4938_IRQ_IRC_PCIC   (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
 175 #define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
 176 #define RBTX4938_IRQ_IRC_NDFMC  (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
 177 #define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
 178 #define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
 179 #define RBTX4938_IRQ_IRC_ACLC   (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
 180 #define RBTX4938_IRQ_IRC_ACLCPME        (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
 181 #define RBTX4938_IRQ_IRC_PCIC1  (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
 182 #define RBTX4938_IRQ_IRC_SPI    (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
 183 #define RBTX4938_IRQ_IOC_PCID   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
 184 #define RBTX4938_IRQ_IOC_PCIC   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
 185 #define RBTX4938_IRQ_IOC_PCIB   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
 186 #define RBTX4938_IRQ_IOC_PCIA   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
 187 #define RBTX4938_IRQ_IOC_RTC    (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
 188 #define RBTX4938_IRQ_IOC_ATA    (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
 189 #define RBTX4938_IRQ_IOC_MODEM  (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
 190 #define RBTX4938_IRQ_IOC_SWINT  (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
 191
 192
 193 /* IOC (PCI, etc) */
 194 #define RBTX4938_IRQ_IOCINT     (TX4938_IRQ_NEST_EXT_ON_PIC)
 195 /* Onboard 10M Ether */
 196 #define RBTX4938_IRQ_ETHER      (TX4938_IRQ_NEST_EXT_ON_PIC + 1)
 197
 198 #define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
 199 #define RBTX4938_RTL_8019_IRQ  (RBTX4938_IRQ_ETHER)
 200
 201 /* IRCR : Int. Control */
 202 #define TX4938_IRCR_LOW  0x00000000
 203 #define TX4938_IRCR_HIGH 0x00000001
 204 #define TX4938_IRCR_DOWN 0x00000002
 205 #define TX4938_IRCR_UP   0x00000003
 206
 207 #endif /* __ASM_TX_BOARDS_RBTX4938_H */