arch/i386/pci/mmconfig.c

   1 /*
   2  * Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
   3  * Copyright (C) 2004 Intel Corp.
   4  *
   5  * This code is released under the GNU General Public License version 2.
   6  */
   7
   8 /*
   9  * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
  10  */
  11
  12 #include <linux/pci.h>
  13 #include <linux/init.h>
  14 #include <linux/acpi.h>
  15 #include <asm/e820.h>
  16 #include "pci.h"
  17
  18 /* aperture is up to 256MB but BIOS may reserve less */
  19 #define MMCONFIG_APER_MIN       (2 * 1024*1024)
  20 #define MMCONFIG_APER_MAX       (256 * 1024*1024)
  21
  22 /* Assume systems with more busses have correct MCFG */
  23 #define MAX_CHECK_BUS 16
  24
  25 #define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
  26
  27 /* The base address of the last MMCONFIG device accessed */
  28 static u32 mmcfg_last_accessed_device;
  29
  30 static DECLARE_BITMAP(fallback_slots, MAX_CHECK_BUS*32);
  31
  32 /*
  33  * Functions for accessing PCI configuration space with MMCONFIG accesses
  34  */
  35 static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
  36 {
  37         int cfg_num = -1;
  38         struct acpi_table_mcfg_config *cfg;
  39
  40         if (seg == 0 && bus < MAX_CHECK_BUS &&
  41             test_bit(PCI_SLOT(devfn) + 32*bus, fallback_slots))
  42                 return 0;
  43
  44         while (1) {
  45                 ++cfg_num;
  46                 if (cfg_num >= pci_mmcfg_config_num) {
  47                         break;
  48                 }
  49                 cfg = &pci_mmcfg_config[cfg_num];
  50                 if (cfg->pci_segment_group_number != seg)
  51                         continue;
  52                 if ((cfg->start_bus_number <= bus) &&
  53                     (cfg->end_bus_number >= bus))
  54                         return cfg->base_address;
  55         }
  56
  57         /* Handle more broken MCFG tables on Asus etc.
  58            They only contain a single entry for bus 0-0. Assume
  59            this applies to all busses. */
  60         cfg = &pci_mmcfg_config[0];
  61         if (pci_mmcfg_config_num == 1 &&
  62                 cfg->pci_segment_group_number == 0 &&
  63                 (cfg->start_bus_number | cfg->end_bus_number) == 0)
  64                 return cfg->base_address;
  65
  66         /* Fall back to type 0 */
  67         return 0;
  68 }
  69
  70 /*
  71  * This is always called under pci_config_lock
  72  */
  73 static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
  74 {
  75         u32 dev_base = base | (bus << 20) | (devfn << 12);
  76         if (dev_base != mmcfg_last_accessed_device) {
  77                 mmcfg_last_accessed_device = dev_base;
  78                 set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
  79         }
  80 }
  81
  82 static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
  83                           unsigned int devfn, int reg, int len, u32 *value)
  84 {
  85         unsigned long flags;
  86         u32 base;
  87
  88         if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
  89                 *value = -1;
  90                 return -EINVAL;
  91         }
  92
  93         base = get_base_addr(seg, bus, devfn);
  94         if (!base)
  95                 return pci_conf1_read(seg,bus,devfn,reg,len,value);
  96
  97         spin_lock_irqsave(&pci_config_lock, flags);
  98
  99         pci_exp_set_dev_base(base, bus, devfn);
 100
 101         switch (len) {
 102         case 1:
 103                 *value = readb(mmcfg_virt_addr + reg);
 104                 break;
 105         case 2:
 106                 *value = readw(mmcfg_virt_addr + reg);
 107                 break;
 108         case 4:
 109                 *value = readl(mmcfg_virt_addr + reg);
 110                 break;
 111         }
 112
 113         spin_unlock_irqrestore(&pci_config_lock, flags);
 114
 115         return 0;
 116 }
 117
 118 static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
 119                            unsigned int devfn, int reg, int len, u32 value)
 120 {
 121         unsigned long flags;
 122         u32 base;
 123
 124         if ((bus > 255) || (devfn > 255) || (reg > 4095))
 125                 return -EINVAL;
 126
 127         base = get_base_addr(seg, bus, devfn);
 128         if (!base)
 129                 return pci_conf1_write(seg,bus,devfn,reg,len,value);
 130
 131         spin_lock_irqsave(&pci_config_lock, flags);
 132
 133         pci_exp_set_dev_base(base, bus, devfn);
 134
 135         switch (len) {
 136         case 1:
 137                 writeb(value, mmcfg_virt_addr + reg);
 138                 break;
 139         case 2:
 140                 writew(value, mmcfg_virt_addr + reg);
 141                 break;
 142         case 4:
 143                 writel(value, mmcfg_virt_addr + reg);
 144                 break;
 145         }
 146
 147         spin_unlock_irqrestore(&pci_config_lock, flags);
 148
 149         return 0;
 150 }
 151
 152 static struct pci_raw_ops pci_mmcfg = {
 153         .read =         pci_mmcfg_read,
 154         .write =        pci_mmcfg_write,
 155 };
 156
 157 /* K8 systems have some devices (typically in the builtin northbridge)
 158    that are only accessible using type1
 159    Normally this can be expressed in the MCFG by not listing them
 160    and assigning suitable _SEGs, but this isn't implemented in some BIOS.
 161    Instead try to discover all devices on bus 0 that are unreachable using MM
 162    and fallback for them. */
 163 static __init void unreachable_devices(void)
 164 {
 165         int i, k;
 166         unsigned long flags;
 167
 168         for (k = 0; k < MAX_CHECK_BUS; k++) {
 169                 for (i = 0; i < 32; i++) {
 170                         u32 val1;
 171                         u32 addr;
 172
 173                         pci_conf1_read(0, k, PCI_DEVFN(i, 0), 0, 4, &val1);
 174                         if (val1 == 0xffffffff)
 175                                 continue;
 176
 177                         /* Locking probably not needed, but safer */
 178                         spin_lock_irqsave(&pci_config_lock, flags);
 179                         addr = get_base_addr(0, k, PCI_DEVFN(i, 0));
 180                         if (addr != 0)
 181                                 pci_exp_set_dev_base(addr, k, PCI_DEVFN(i, 0));
 182                         if (addr == 0 ||
 183                             readl((u32 __iomem *)mmcfg_virt_addr) != val1) {
 184                                 set_bit(i + 32*k, fallback_slots);
 185                                 printk(KERN_NOTICE
 186                         "PCI: No mmconfig possible on %x:%x\n", k, i);
 187                         }
 188                         spin_unlock_irqrestore(&pci_config_lock, flags);
 189                 }
 190         }
 191 }
 192
 193 void __init pci_mmcfg_init(int type)
 194 {
 195         if ((pci_probe & PCI_PROBE_MMCONF) == 0)
 196                 return;
 197
 198         acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
 199         if ((pci_mmcfg_config_num == 0) ||
 200             (pci_mmcfg_config == NULL) ||
 201             (pci_mmcfg_config[0].base_address == 0))
 202                 return;
 203
 204         /* Only do this check when type 1 works. If it doesn't work
 205            assume we run on a Mac and always use MCFG */
 206         if (type == 1 && !e820_all_mapped(pci_mmcfg_config[0].base_address,
 207                         pci_mmcfg_config[0].base_address + MMCONFIG_APER_MIN,
 208                         E820_RESERVED)) {
 209                 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %x is not E820-reserved\n",
 210                                 pci_mmcfg_config[0].base_address);
 211                 printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
 212                 return;
 213         }
 214
 215         printk(KERN_INFO "PCI: Using MMCONFIG\n");
 216         raw_pci_ops = &pci_mmcfg;
 217         pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
 218
 219         unreachable_devices();
 220 }