arch/arm/common/gic.c

   1 /*
   2  *  linux/arch/arm/common/gic.c
   3  *
   4  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Interrupt architecture for the GIC:
  11  *
  12  * o There is one Interrupt Distributor, which receives interrupts
  13  *   from system devices and sends them to the Interrupt Controllers.
  14  *
  15  * o There is one CPU Interface per CPU, which sends interrupts sent
  16  *   by the Distributor, and interrupts generated locally, to the
  17  *   associated CPU.
  18  *
  19  * Note that IRQs 0-31 are special - they are local to each CPU.
  20  * As such, the enable set/clear, pending set/clear and active bit
  21  * registers are banked per-cpu for these sources.
  22  */
  23 #include <linux/init.h>
  24 #include <linux/kernel.h>
  25 #include <linux/list.h>
  26 #include <linux/smp.h>
  27 #include <linux/cpumask.h>
  28
  29 #include <asm/irq.h>
  30 #include <asm/io.h>
  31 #include <asm/mach/irq.h>
  32 #include <asm/hardware/gic.h>
  33
  34 static void __iomem *gic_dist_base;
  35 static void __iomem *gic_cpu_base;
  36 static DEFINE_SPINLOCK(irq_controller_lock);
  37
  38 /*
  39  * Routines to acknowledge, disable and enable interrupts
  40  *
  41  * Linux assumes that when we're done with an interrupt we need to
  42  * unmask it, in the same way we need to unmask an interrupt when
  43  * we first enable it.
  44  *
  45  * The GIC has a seperate notion of "end of interrupt" to re-enable
  46  * an interrupt after handling, in order to support hardware
  47  * prioritisation.
  48  *
  49  * We can make the GIC behave in the way that Linux expects by making
  50  * our "acknowledge" routine disable the interrupt, then mark it as
  51  * complete.
  52  */
  53 static void gic_ack_irq(unsigned int irq)
  54 {
  55         u32 mask = 1 << (irq % 32);
  56
  57         spin_lock(&irq_controller_lock);
  58         writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
  59         writel(irq, gic_cpu_base + GIC_CPU_EOI);
  60         spin_unlock(&irq_controller_lock);
  61 }
  62
  63 static void gic_mask_irq(unsigned int irq)
  64 {
  65         u32 mask = 1 << (irq % 32);
  66
  67         spin_lock(&irq_controller_lock);
  68         writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
  69         spin_unlock(&irq_controller_lock);
  70 }
  71
  72 static void gic_unmask_irq(unsigned int irq)
  73 {
  74         u32 mask = 1 << (irq % 32);
  75
  76         spin_lock(&irq_controller_lock);
  77         writel(mask, gic_dist_base + GIC_DIST_ENABLE_SET + (irq / 32) * 4);
  78         spin_unlock(&irq_controller_lock);
  79 }
  80
  81 #ifdef CONFIG_SMP
  82 static void gic_set_cpu(unsigned int irq, cpumask_t mask_val)
  83 {
  84         void __iomem *reg = gic_dist_base + GIC_DIST_TARGET + (irq & ~3);
  85         unsigned int shift = (irq % 4) * 8;
  86         unsigned int cpu = first_cpu(mask_val);
  87         u32 val;
  88
  89         spin_lock(&irq_controller_lock);
  90         irq_desc[irq].cpu = cpu;
  91         val = readl(reg) & ~(0xff << shift);
  92         val |= 1 << (cpu + shift);
  93         writel(val, reg);
  94         spin_unlock(&irq_controller_lock);
  95 }
  96 #endif
  97
  98 static struct irq_chip gic_chip = {
  99         .name           = "GIC",
 100         .ack            = gic_ack_irq,
 101         .mask           = gic_mask_irq,
 102         .unmask         = gic_unmask_irq,
 103 #ifdef CONFIG_SMP
 104         .set_affinity   = gic_set_cpu,
 105 #endif
 106 };
 107
 108 void __init gic_dist_init(void __iomem *base)
 109 {
 110         unsigned int max_irq, i;
 111         u32 cpumask = 1 << smp_processor_id();
 112
 113         cpumask |= cpumask << 8;
 114         cpumask |= cpumask << 16;
 115
 116         gic_dist_base = base;
 117
 118         writel(0, base + GIC_DIST_CTRL);
 119
 120         /*
 121          * Find out how many interrupts are supported.
 122          */
 123         max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
 124         max_irq = (max_irq + 1) * 32;
 125
 126         /*
 127          * The GIC only supports up to 1020 interrupt sources.
 128          * Limit this to either the architected maximum, or the
 129          * platform maximum.
 130          */
 131         if (max_irq > max(1020, NR_IRQS))
 132                 max_irq = max(1020, NR_IRQS);
 133
 134         /*
 135          * Set all global interrupts to be level triggered, active low.
 136          */
 137         for (i = 32; i < max_irq; i += 16)
 138                 writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
 139
 140         /*
 141          * Set all global interrupts to this CPU only.
 142          */
 143         for (i = 32; i < max_irq; i += 4)
 144                 writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
 145
 146         /*
 147          * Set priority on all interrupts.
 148          */
 149         for (i = 0; i < max_irq; i += 4)
 150                 writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
 151
 152         /*
 153          * Disable all interrupts.
 154          */
 155         for (i = 0; i < max_irq; i += 32)
 156                 writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
 157
 158         /*
 159          * Setup the Linux IRQ subsystem.
 160          */
 161         for (i = 29; i < max_irq; i++) {
 162                 set_irq_chip(i, &gic_chip);
 163                 set_irq_handler(i, do_level_IRQ);
 164                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 165         }
 166
 167         writel(1, base + GIC_DIST_CTRL);
 168 }
 169
 170 void __cpuinit gic_cpu_init(void __iomem *base)
 171 {
 172         gic_cpu_base = base;
 173         writel(0xf0, base + GIC_CPU_PRIMASK);
 174         writel(1, base + GIC_CPU_CTRL);
 175 }
 176
 177 #ifdef CONFIG_SMP
 178 void gic_raise_softirq(cpumask_t cpumask, unsigned int irq)
 179 {
 180         unsigned long map = *cpus_addr(cpumask);
 181
 182         writel(map << 16 | irq, gic_dist_base + GIC_DIST_SOFTINT);
 183 }
 184 #endif