?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sync hh.org
[hh.org.git] / arch / arm / plat-omap / dma.c
blobbb045e5ddbd837e3906a90415e5800b383c6dd08
1 /*
2 * linux/arch/arm/plat-omap/dma.c
3 *
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2 support Copyright (C) 2004-2005 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
13 * Support functions for the OMAP internal DMA channels.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 *
19 */
20
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28
29 #include <asm/system.h>
30 #include <asm/hardware.h>
31 #include <asm/dma.h>
32 #include <asm/io.h>
33
34 #include <asm/arch/tc.h>
35
36 #define DEBUG_PRINTS
37 #undef DEBUG_PRINTS
38 #ifdef DEBUG_PRINTS
39 #define debug_printk(x) printk x
40 #else
41 #define debug_printk(x)
42 #endif
43
44 #define OMAP_DMA_ACTIVE 0x01
45 #define OMAP_DMA_CCR_EN (1 << 7)
46 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
47
48 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
49
50 static int enable_1510_mode = 0;
51
52 struct omap_dma_lch {
53 int next_lch;
54 int dev_id;
55 u16 saved_csr;
56 u16 enabled_irqs;
57 const char *dev_name;
58 void (* callback)(int lch, u16 ch_status, void *data);
59 void *data;
60 long flags;
61 };
62
63 static int dma_chan_count;
64
65 static spinlock_t dma_chan_lock;
66 static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT];
67
68 static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = {
69 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
70 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
71 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
72 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
73 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
74 };
75
76 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
77 __FUNCTION__);
78
79 #ifdef CONFIG_ARCH_OMAP15XX
80 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
81 int omap_dma_in_1510_mode(void)
82 {
83 return enable_1510_mode;
84 }
85 #else
86 #define omap_dma_in_1510_mode() 0
87 #endif
88
89 #ifdef CONFIG_ARCH_OMAP1
90 static inline int get_gdma_dev(int req)
91 {
92 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
93 int shift = ((req - 1) % 5) * 6;
94
95 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
96 }
97
98 static inline void set_gdma_dev(int req, int dev)
99 {
100 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
101 int shift = ((req - 1) % 5) * 6;
102 u32 l;
103
104 l = omap_readl(reg);
105 l &= ~(0x3f << shift);
106 l |= (dev - 1) << shift;
107 omap_writel(l, reg);
108 }
109 #else
110 #define set_gdma_dev(req, dev) do {} while (0)
111 #endif
112
113 static void clear_lch_regs(int lch)
114 {
115 int i;
116 u32 lch_base = OMAP_DMA_BASE + lch * 0x40;
117
118 for (i = 0; i < 0x2c; i += 2)
119 omap_writew(0, lch_base + i);
120 }
121
122 void omap_set_dma_priority(int lch, int dst_port, int priority)
123 {
124 unsigned long reg;
125 u32 l;
126
127 if (cpu_class_is_omap1()) {
128 switch (dst_port) {
129 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
130 reg = OMAP_TC_OCPT1_PRIOR;
131 break;
132 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
133 reg = OMAP_TC_OCPT2_PRIOR;
134 break;
135 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
136 reg = OMAP_TC_EMIFF_PRIOR;
137 break;
138 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
139 reg = OMAP_TC_EMIFS_PRIOR;
140 break;
141 default:
142 BUG();
143 return;
144 }
145 l = omap_readl(reg);
146 l &= ~(0xf << 8);
147 l |= (priority & 0xf) << 8;
148 omap_writel(l, reg);
149 }
150
151 if (cpu_is_omap24xx()) {
152 if (priority)
153 OMAP_DMA_CCR_REG(lch) |= (1 << 6);
154 else
155 OMAP_DMA_CCR_REG(lch) &= ~(1 << 6);
156 }
157 }
158
159 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
160 int frame_count, int sync_mode,
161 int dma_trigger, int src_or_dst_synch)
162 {
163 OMAP_DMA_CSDP_REG(lch) &= ~0x03;
164 OMAP_DMA_CSDP_REG(lch) |= data_type;
165
166 if (cpu_class_is_omap1()) {
167 OMAP_DMA_CCR_REG(lch) &= ~(1 << 5);
168 if (sync_mode == OMAP_DMA_SYNC_FRAME)
169 OMAP_DMA_CCR_REG(lch) |= 1 << 5;
170
171 OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2);
172 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
173 OMAP1_DMA_CCR2_REG(lch) |= 1 << 2;
174 }
175
176 if (cpu_is_omap24xx() && dma_trigger) {
177 u32 val = OMAP_DMA_CCR_REG(lch);
178
179 val &= ~(3 << 19);
180 if (dma_trigger > 63)
181 val |= 1 << 20;
182 if (dma_trigger > 31)
183 val |= 1 << 19;
184
185 val &= ~(0x1f);
186 val |= (dma_trigger & 0x1f);
187
188 if (sync_mode & OMAP_DMA_SYNC_FRAME)
189 val |= 1 << 5;
190 else
191 val &= ~(1 << 5);
192
193 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
194 val |= 1 << 18;
195 else
196 val &= ~(1 << 18);
197
198 if (src_or_dst_synch)
199 val |= 1 << 24; /* source synch */
200 else
201 val &= ~(1 << 24); /* dest synch */
202
203 OMAP_DMA_CCR_REG(lch) = val;
204 }
205
206 OMAP_DMA_CEN_REG(lch) = elem_count;
207 OMAP_DMA_CFN_REG(lch) = frame_count;
208 }
209
210 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
211 {
212 u16 w;
213
214 BUG_ON(omap_dma_in_1510_mode());
215
216 if (cpu_is_omap24xx()) {
217 REVISIT_24XX();
218 return;
219 }
220
221 w = OMAP1_DMA_CCR2_REG(lch) & ~0x03;
222 switch (mode) {
223 case OMAP_DMA_CONSTANT_FILL:
224 w |= 0x01;
225 break;
226 case OMAP_DMA_TRANSPARENT_COPY:
227 w |= 0x02;
228 break;
229 case OMAP_DMA_COLOR_DIS:
230 break;
231 default:
232 BUG();
233 }
234 OMAP1_DMA_CCR2_REG(lch) = w;
235
236 w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f;
237 /* Default is channel type 2D */
238 if (mode) {
239 OMAP1_DMA_COLOR_L_REG(lch) = (u16)color;
240 OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16);
241 w |= 1; /* Channel type G */
242 }
243 OMAP1_DMA_LCH_CTRL_REG(lch) = w;
244 }
245
246 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
247 {
248 if (cpu_is_omap24xx()) {
249 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16);
250 OMAP_DMA_CSDP_REG(lch) |= (mode << 16);
251 }
252 }
253
254 /* Note that src_port is only for omap1 */
255 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
256 unsigned long src_start,
257 int src_ei, int src_fi)
258 {
259 if (cpu_class_is_omap1()) {
260 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2);
261 OMAP_DMA_CSDP_REG(lch) |= src_port << 2;
262 }
263
264 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12);
265 OMAP_DMA_CCR_REG(lch) |= src_amode << 12;
266
267 if (cpu_class_is_omap1()) {
268 OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16;
269 OMAP1_DMA_CSSA_L_REG(lch) = src_start;
270 }
271
272 if (cpu_is_omap24xx())
273 OMAP2_DMA_CSSA_REG(lch) = src_start;
274
275 OMAP_DMA_CSEI_REG(lch) = src_ei;
276 OMAP_DMA_CSFI_REG(lch) = src_fi;
277 }
278
279 void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
280 {
281 omap_set_dma_transfer_params(lch, params->data_type,
282 params->elem_count, params->frame_count,
283 params->sync_mode, params->trigger,
284 params->src_or_dst_synch);
285 omap_set_dma_src_params(lch, params->src_port,
286 params->src_amode, params->src_start,
287 params->src_ei, params->src_fi);
288
289 omap_set_dma_dest_params(lch, params->dst_port,
290 params->dst_amode, params->dst_start,
291 params->dst_ei, params->dst_fi);
292 }
293
294 void omap_set_dma_src_index(int lch, int eidx, int fidx)
295 {
296 if (cpu_is_omap24xx()) {
297 REVISIT_24XX();
298 return;
299 }
300 OMAP_DMA_CSEI_REG(lch) = eidx;
301 OMAP_DMA_CSFI_REG(lch) = fidx;
302 }
303
304 void omap_set_dma_src_data_pack(int lch, int enable)
305 {
306 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6);
307 if (enable)
308 OMAP_DMA_CSDP_REG(lch) |= (1 << 6);
309 }
310
311 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
312 {
313 unsigned int burst = 0;
314 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7);
315
316 switch (burst_mode) {
317 case OMAP_DMA_DATA_BURST_DIS:
318 break;
319 case OMAP_DMA_DATA_BURST_4:
320 if (cpu_is_omap24xx())
321 burst = 0x1;
322 else
323 burst = 0x2;
324 break;
325 case OMAP_DMA_DATA_BURST_8:
326 if (cpu_is_omap24xx()) {
327 burst = 0x2;
328 break;
329 }
330 /* not supported by current hardware on OMAP1
331 * w |= (0x03 << 7);
332 * fall through
333 */
334 case OMAP_DMA_DATA_BURST_16:
335 if (cpu_is_omap24xx()) {
336 burst = 0x3;
337 break;
338 }
339 /* OMAP1 don't support burst 16
340 * fall through
341 */
342 default:
343 BUG();
344 }
345 OMAP_DMA_CSDP_REG(lch) |= (burst << 7);
346 }
347
348 /* Note that dest_port is only for OMAP1 */
349 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
350 unsigned long dest_start,
351 int dst_ei, int dst_fi)
352 {
353 if (cpu_class_is_omap1()) {
354 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9);
355 OMAP_DMA_CSDP_REG(lch) |= dest_port << 9;
356 }
357
358 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14);
359 OMAP_DMA_CCR_REG(lch) |= dest_amode << 14;
360
361 if (cpu_class_is_omap1()) {
362 OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16;
363 OMAP1_DMA_CDSA_L_REG(lch) = dest_start;
364 }
365
366 if (cpu_is_omap24xx())
367 OMAP2_DMA_CDSA_REG(lch) = dest_start;
368
369 OMAP_DMA_CDEI_REG(lch) = dst_ei;
370 OMAP_DMA_CDFI_REG(lch) = dst_fi;
371 }
372
373 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
374 {
375 if (cpu_is_omap24xx()) {
376 REVISIT_24XX();
377 return;
378 }
379 OMAP_DMA_CDEI_REG(lch) = eidx;
380 OMAP_DMA_CDFI_REG(lch) = fidx;
381 }
382
383 void omap_set_dma_dest_data_pack(int lch, int enable)
384 {
385 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13);
386 if (enable)
387 OMAP_DMA_CSDP_REG(lch) |= 1 << 13;
388 }
389
390 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
391 {
392 unsigned int burst = 0;
393 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14);
394
395 switch (burst_mode) {
396 case OMAP_DMA_DATA_BURST_DIS:
397 break;
398 case OMAP_DMA_DATA_BURST_4:
399 if (cpu_is_omap24xx())
400 burst = 0x1;
401 else
402 burst = 0x2;
403 break;
404 case OMAP_DMA_DATA_BURST_8:
405 if (cpu_is_omap24xx())
406 burst = 0x2;
407 else
408 burst = 0x3;
409 break;
410 case OMAP_DMA_DATA_BURST_16:
411 if (cpu_is_omap24xx()) {
412 burst = 0x3;
413 break;
414 }
415 /* OMAP1 don't support burst 16
416 * fall through
417 */
418 default:
419 printk(KERN_ERR "Invalid DMA burst mode\n");
420 BUG();
421 return;
422 }
423 OMAP_DMA_CSDP_REG(lch) |= (burst << 14);
424 }
425
426 static inline void omap_enable_channel_irq(int lch)
427 {
428 u32 status;
429
430 /* Clear CSR */
431 if (cpu_class_is_omap1())
432 status = OMAP_DMA_CSR_REG(lch);
433 else if (cpu_is_omap24xx())
434 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
435
436 /* Enable some nice interrupts. */
437 OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
438
439 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
440 }
441
442 static void omap_disable_channel_irq(int lch)
443 {
444 if (cpu_is_omap24xx())
445 OMAP_DMA_CICR_REG(lch) = 0;
446 }
447
448 void omap_enable_dma_irq(int lch, u16 bits)
449 {
450 dma_chan[lch].enabled_irqs |= bits;
451 }
452
453 void omap_disable_dma_irq(int lch, u16 bits)
454 {
455 dma_chan[lch].enabled_irqs &= ~bits;
456 }
457
458 static inline void enable_lnk(int lch)
459 {
460 if (cpu_class_is_omap1())
461 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14);
462
463 /* Set the ENABLE_LNK bits */
464 if (dma_chan[lch].next_lch != -1)
465 OMAP_DMA_CLNK_CTRL_REG(lch) =
466 dma_chan[lch].next_lch | (1 << 15);
467 }
468
469 static inline void disable_lnk(int lch)
470 {
471 /* Disable interrupts */
472 if (cpu_class_is_omap1()) {
473 OMAP_DMA_CICR_REG(lch) = 0;
474 /* Set the STOP_LNK bit */
475 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14;
476 }
477
478 if (cpu_is_omap24xx()) {
479 omap_disable_channel_irq(lch);
480 /* Clear the ENABLE_LNK bit */
481 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15);
482 }
483
484 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
485 }
486
487 static inline void omap2_enable_irq_lch(int lch)
488 {
489 u32 val;
490
491 if (!cpu_is_omap24xx())
492 return;
493
494 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
495 val |= 1 << lch;
496 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
497 }
498
499 int omap_request_dma(int dev_id, const char *dev_name,
500 void (* callback)(int lch, u16 ch_status, void *data),
501 void *data, int *dma_ch_out)
502 {
503 int ch, free_ch = -1;
504 unsigned long flags;
505 struct omap_dma_lch *chan;
506
507 spin_lock_irqsave(&dma_chan_lock, flags);
508 for (ch = 0; ch < dma_chan_count; ch++) {
509 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
510 free_ch = ch;
511 if (dev_id == 0)
512 break;
513 }
514 }
515 if (free_ch == -1) {
516 spin_unlock_irqrestore(&dma_chan_lock, flags);
517 return -EBUSY;
518 }
519 chan = dma_chan + free_ch;
520 chan->dev_id = dev_id;
521
522 if (cpu_class_is_omap1())
523 clear_lch_regs(free_ch);
524
525 if (cpu_is_omap24xx())
526 omap_clear_dma(free_ch);
527
528 spin_unlock_irqrestore(&dma_chan_lock, flags);
529
530 chan->dev_name = dev_name;
531 chan->callback = callback;
532 chan->data = data;
533 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
534
535 if (cpu_class_is_omap1())
536 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
537 else if (cpu_is_omap24xx())
538 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
539 OMAP2_DMA_TRANS_ERR_IRQ;
540
541 if (cpu_is_omap16xx()) {
542 /* If the sync device is set, configure it dynamically. */
543 if (dev_id != 0) {
544 set_gdma_dev(free_ch + 1, dev_id);
545 dev_id = free_ch + 1;
546 }
547 /* Disable the 1510 compatibility mode and set the sync device
548 * id. */
549 OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10);
550 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
551 OMAP_DMA_CCR_REG(free_ch) = dev_id;
552 }
553
554 if (cpu_is_omap24xx()) {
555 omap2_enable_irq_lch(free_ch);
556
557 omap_enable_channel_irq(free_ch);
558 /* Clear the CSR register and IRQ status register */
559 OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK;
560 omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0);
561 }
562
563 *dma_ch_out = free_ch;
564
565 return 0;
566 }
567
568 void omap_free_dma(int lch)
569 {
570 unsigned long flags;
571
572 spin_lock_irqsave(&dma_chan_lock, flags);
573 if (dma_chan[lch].dev_id == -1) {
574 printk("omap_dma: trying to free nonallocated DMA channel %d\n",
575 lch);
576 spin_unlock_irqrestore(&dma_chan_lock, flags);
577 return;
578 }
579 dma_chan[lch].dev_id = -1;
580 dma_chan[lch].next_lch = -1;
581 dma_chan[lch].callback = NULL;
582 spin_unlock_irqrestore(&dma_chan_lock, flags);
583
584 if (cpu_class_is_omap1()) {
585 /* Disable all DMA interrupts for the channel. */
586 OMAP_DMA_CICR_REG(lch) = 0;
587 /* Make sure the DMA transfer is stopped. */
588 OMAP_DMA_CCR_REG(lch) = 0;
589 }
590
591 if (cpu_is_omap24xx()) {
592 u32 val;
593 /* Disable interrupts */
594 val = omap_readl(OMAP_DMA4_IRQENABLE_L0);
595 val &= ~(1 << lch);
596 omap_writel(val, OMAP_DMA4_IRQENABLE_L0);
597
598 /* Clear the CSR register and IRQ status register */
599 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
600
601 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
602 val |= 1 << lch;
603 omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
604
605 /* Disable all DMA interrupts for the channel. */
606 OMAP_DMA_CICR_REG(lch) = 0;
607
608 /* Make sure the DMA transfer is stopped. */
609 OMAP_DMA_CCR_REG(lch) = 0;
610 omap_clear_dma(lch);
611 }
612 }
613
614 /*
615 * Clears any DMA state so the DMA engine is ready to restart with new buffers
616 * through omap_start_dma(). Any buffers in flight are discarded.
617 */
618 void omap_clear_dma(int lch)
619 {
620 unsigned long flags;
621
622 local_irq_save(flags);
623
624 if (cpu_class_is_omap1()) {
625 int status;
626 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
627
628 /* Clear pending interrupts */
629 status = OMAP_DMA_CSR_REG(lch);
630 }
631
632 if (cpu_is_omap24xx()) {
633 int i;
634 u32 lch_base = OMAP24XX_DMA_BASE + lch * 0x60 + 0x80;
635 for (i = 0; i < 0x44; i += 4)
636 omap_writel(0, lch_base + i);
637 }
638
639 local_irq_restore(flags);
640 }
641
642 void omap_start_dma(int lch)
643 {
644 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
645 int next_lch, cur_lch;
646 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
647
648 dma_chan_link_map[lch] = 1;
649 /* Set the link register of the first channel */
650 enable_lnk(lch);
651
652 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
653 cur_lch = dma_chan[lch].next_lch;
654 do {
655 next_lch = dma_chan[cur_lch].next_lch;
656
657 /* The loop case: we've been here already */
658 if (dma_chan_link_map[cur_lch])
659 break;
660 /* Mark the current channel */
661 dma_chan_link_map[cur_lch] = 1;
662
663 enable_lnk(cur_lch);
664 omap_enable_channel_irq(cur_lch);
665
666 cur_lch = next_lch;
667 } while (next_lch != -1);
668 } else if (cpu_is_omap24xx()) {
669 /* Errata: Need to write lch even if not using chaining */
670 OMAP_DMA_CLNK_CTRL_REG(lch) = lch;
671 }
672
673 omap_enable_channel_irq(lch);
674
675 /* Errata: On ES2.0 BUFFERING disable must be set.
676 * This will always fail on ES1.0 */
677 if (cpu_is_omap24xx()) {
678 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
679 }
680
681 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
682
683 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
684 }
685
686 void omap_stop_dma(int lch)
687 {
688 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
689 int next_lch, cur_lch = lch;
690 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT];
691
692 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
693 do {
694 /* The loop case: we've been here already */
695 if (dma_chan_link_map[cur_lch])
696 break;
697 /* Mark the current channel */
698 dma_chan_link_map[cur_lch] = 1;
699
700 disable_lnk(cur_lch);
701
702 next_lch = dma_chan[cur_lch].next_lch;
703 cur_lch = next_lch;
704 } while (next_lch != -1);
705
706 return;
707 }
708
709 /* Disable all interrupts on the channel */
710 if (cpu_class_is_omap1())
711 OMAP_DMA_CICR_REG(lch) = 0;
712
713 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
714 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
715 }
716
717 /*
718 * Allows changing the DMA callback function or data. This may be needed if
719 * the driver shares a single DMA channel for multiple dma triggers.
720 */
721 int omap_set_dma_callback(int lch,
722 void (* callback)(int lch, u16 ch_status, void *data),
723 void *data)
724 {
725 unsigned long flags;
726
727 if (lch < 0)
728 return -ENODEV;
729
730 spin_lock_irqsave(&dma_chan_lock, flags);
731 if (dma_chan[lch].dev_id == -1) {
732 printk(KERN_ERR "DMA callback for not set for free channel\n");
733 spin_unlock_irqrestore(&dma_chan_lock, flags);
734 return -EINVAL;
735 }
736 dma_chan[lch].callback = callback;
737 dma_chan[lch].data = data;
738 spin_unlock_irqrestore(&dma_chan_lock, flags);
739
740 return 0;
741 }
742
743 /*
744 * Returns current physical source address for the given DMA channel.
745 * If the channel is running the caller must disable interrupts prior calling
746 * this function and process the returned value before re-enabling interrupt to
747 * prevent races with the interrupt handler. Note that in continuous mode there
748 * is a chance for CSSA_L register overflow inbetween the two reads resulting
749 * in incorrect return value.
750 */
751 dma_addr_t omap_get_dma_src_pos(int lch)
752 {
753 dma_addr_t offset;
754
755 if (cpu_class_is_omap1())
756 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) |
757 (OMAP1_DMA_CSSA_U_REG(lch) << 16));
758
759 if (cpu_is_omap24xx())
760 offset = OMAP_DMA_CSAC_REG(lch);
761
762 return offset;
763 }
764
765 /*
766 * Returns current physical destination address for the given DMA channel.
767 * If the channel is running the caller must disable interrupts prior calling
768 * this function and process the returned value before re-enabling interrupt to
769 * prevent races with the interrupt handler. Note that in continuous mode there
770 * is a chance for CDSA_L register overflow inbetween the two reads resulting
771 * in incorrect return value.
772 */
773 dma_addr_t omap_get_dma_dst_pos(int lch)
774 {
775 dma_addr_t offset;
776
777 if (cpu_class_is_omap1())
778 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) |
779 (OMAP1_DMA_CDSA_U_REG(lch) << 16));
780
781 if (cpu_is_omap24xx())
782 offset = OMAP2_DMA_CDSA_REG(lch);
783
784 return offset;
785 }
786
787 /*
788 * Returns current source transfer counting for the given DMA channel.
789 * Can be used to monitor the progress of a transfer inside a block.
790 * It must be called with disabled interrupts.
791 */
792 int omap_get_dma_src_addr_counter(int lch)
793 {
794 return (dma_addr_t) OMAP_DMA_CSAC_REG(lch);
795 }
796
797 int omap_dma_running(void)
798 {
799 int lch;
800
801 /* Check if LCD DMA is running */
802 if (cpu_is_omap16xx())
803 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
804 return 1;
805
806 for (lch = 0; lch < dma_chan_count; lch++)
807 if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN)
808 return 1;
809
810 return 0;
811 }
812
813 /*
814 * lch_queue DMA will start right after lch_head one is finished.
815 * For this DMA link to start, you still need to start (see omap_start_dma)
816 * the first one. That will fire up the entire queue.
817 */
818 void omap_dma_link_lch (int lch_head, int lch_queue)
819 {
820 if (omap_dma_in_1510_mode()) {
821 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
822 BUG();
823 return;
824 }
825
826 if ((dma_chan[lch_head].dev_id == -1) ||
827 (dma_chan[lch_queue].dev_id == -1)) {
828 printk(KERN_ERR "omap_dma: trying to link "
829 "non requested channels\n");
830 dump_stack();
831 }
832
833 dma_chan[lch_head].next_lch = lch_queue;
834 }
835
836 /*
837 * Once the DMA queue is stopped, we can destroy it.
838 */
839 void omap_dma_unlink_lch (int lch_head, int lch_queue)
840 {
841 if (omap_dma_in_1510_mode()) {
842 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
843 BUG();
844 return;
845 }
846
847 if (dma_chan[lch_head].next_lch != lch_queue ||
848 dma_chan[lch_head].next_lch == -1) {
849 printk(KERN_ERR "omap_dma: trying to unlink "
850 "non linked channels\n");
851 dump_stack();
852 }
853
854
855 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
856 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
857 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
858 "before unlinking\n");
859 dump_stack();
860 }
861
862 dma_chan[lch_head].next_lch = -1;
863 }
864
865 /*----------------------------------------------------------------------------*/
866
867 #ifdef CONFIG_ARCH_OMAP1
868
869 static int omap1_dma_handle_ch(int ch)
870 {
871 u16 csr;
872
873 if (enable_1510_mode && ch >= 6) {
874 csr = dma_chan[ch].saved_csr;
875 dma_chan[ch].saved_csr = 0;
876 } else
877 csr = OMAP_DMA_CSR_REG(ch);
878 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
879 dma_chan[ch + 6].saved_csr = csr >> 7;
880 csr &= 0x7f;
881 }
882 if ((csr & 0x3f) == 0)
883 return 0;
884 if (unlikely(dma_chan[ch].dev_id == -1)) {
885 printk(KERN_WARNING "Spurious interrupt from DMA channel "
886 "%d (CSR %04x)\n", ch, csr);
887 return 0;
888 }
889 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
890 printk(KERN_WARNING "DMA timeout with device %d\n",
891 dma_chan[ch].dev_id);
892 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
893 printk(KERN_WARNING "DMA synchronization event drop occurred "
894 "with device %d\n", dma_chan[ch].dev_id);
895 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
896 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
897 if (likely(dma_chan[ch].callback != NULL))
898 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
899 return 1;
900 }
901
902 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
903 {
904 int ch = ((int) dev_id) - 1;
905 int handled = 0;
906
907 for (;;) {
908 int handled_now = 0;
909
910 handled_now += omap1_dma_handle_ch(ch);
911 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
912 handled_now += omap1_dma_handle_ch(ch + 6);
913 if (!handled_now)
914 break;
915 handled += handled_now;
916 }
917
918 return handled ? IRQ_HANDLED : IRQ_NONE;
919 }
920
921 #else
922 #define omap1_dma_irq_handler NULL
923 #endif
924
925 #ifdef CONFIG_ARCH_OMAP2
926
927 static int omap2_dma_handle_ch(int ch)
928 {
929 u32 status = OMAP_DMA_CSR_REG(ch);
930 u32 val;
931
932 if (!status)
933 return 0;
934 if (unlikely(dma_chan[ch].dev_id == -1))
935 return 0;
936 if (unlikely(status & OMAP_DMA_DROP_IRQ))
937 printk(KERN_INFO
938 "DMA synchronization event drop occurred with device "
939 "%d\n", dma_chan[ch].dev_id);
940 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
941 printk(KERN_INFO "DMA transaction error with device %d\n",
942 dma_chan[ch].dev_id);
943 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
944 printk(KERN_INFO "DMA secure error with device %d\n",
945 dma_chan[ch].dev_id);
946 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
947 printk(KERN_INFO "DMA misaligned error with device %d\n",
948 dma_chan[ch].dev_id);
949
950 OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
951
952 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
953 /* ch in this function is from 0-31 while in register it is 1-32 */
954 val = 1 << (ch);
955 omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
956
957 if (likely(dma_chan[ch].callback != NULL))
958 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
959
960 return 0;
961 }
962
963 /* STATUS register count is from 1-32 while our is 0-31 */
964 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
965 {
966 u32 val;
967 int i;
968
969 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
970
971 for (i = 1; i <= OMAP_LOGICAL_DMA_CH_COUNT; i++) {
972 int active = val & (1 << (i - 1));
973 if (active)
974 omap2_dma_handle_ch(i - 1);
975 }
976
977 return IRQ_HANDLED;
978 }
979
980 static struct irqaction omap24xx_dma_irq = {
981 .name = "DMA",
982 .handler = omap2_dma_irq_handler,
983 .flags = IRQF_DISABLED
984 };
985
986 #else
987 static struct irqaction omap24xx_dma_irq;
988 #endif
989
990 /*----------------------------------------------------------------------------*/
991
992 static struct lcd_dma_info {
993 spinlock_t lock;
994 int reserved;
995 void (* callback)(u16 status, void *data);
996 void *cb_data;
997
998 int active;
999 unsigned long addr, size;
1000 int rotate, data_type, xres, yres;
1001 int vxres;
1002 int mirror;
1003 int xscale, yscale;
1004 int ext_ctrl;
1005 int src_port;
1006 int single_transfer;
1007 } lcd_dma;
1008
1009 void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1010 int data_type)
1011 {
1012 lcd_dma.addr = addr;
1013 lcd_dma.data_type = data_type;
1014 lcd_dma.xres = fb_xres;
1015 lcd_dma.yres = fb_yres;
1016 }
1017
1018 void omap_set_lcd_dma_src_port(int port)
1019 {
1020 lcd_dma.src_port = port;
1021 }
1022
1023 void omap_set_lcd_dma_ext_controller(int external)
1024 {
1025 lcd_dma.ext_ctrl = external;
1026 }
1027
1028 void omap_set_lcd_dma_single_transfer(int single)
1029 {
1030 lcd_dma.single_transfer = single;
1031 }
1032
1033
1034 void omap_set_lcd_dma_b1_rotation(int rotate)
1035 {
1036 if (omap_dma_in_1510_mode()) {
1037 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
1038 BUG();
1039 return;
1040 }
1041 lcd_dma.rotate = rotate;
1042 }
1043
1044 void omap_set_lcd_dma_b1_mirror(int mirror)
1045 {
1046 if (omap_dma_in_1510_mode()) {
1047 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
1048 BUG();
1049 }
1050 lcd_dma.mirror = mirror;
1051 }
1052
1053 void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1054 {
1055 if (omap_dma_in_1510_mode()) {
1056 printk(KERN_ERR "DMA virtual resulotion is not supported "
1057 "in 1510 mode\n");
1058 BUG();
1059 }
1060 lcd_dma.vxres = vxres;
1061 }
1062
1063 void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1064 {
1065 if (omap_dma_in_1510_mode()) {
1066 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
1067 BUG();
1068 }
1069 lcd_dma.xscale = xscale;
1070 lcd_dma.yscale = yscale;
1071 }
1072
1073 static void set_b1_regs(void)
1074 {
1075 unsigned long top, bottom;
1076 int es;
1077 u16 w;
1078 unsigned long en, fn;
1079 long ei, fi;
1080 unsigned long vxres;
1081 unsigned int xscale, yscale;
1082
1083 switch (lcd_dma.data_type) {
1084 case OMAP_DMA_DATA_TYPE_S8:
1085 es = 1;
1086 break;
1087 case OMAP_DMA_DATA_TYPE_S16:
1088 es = 2;
1089 break;
1090 case OMAP_DMA_DATA_TYPE_S32:
1091 es = 4;
1092 break;
1093 default:
1094 BUG();
1095 return;
1096 }
1097
1098 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
1099 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
1100 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
1101 BUG_ON(vxres < lcd_dma.xres);
1102 #define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
1103 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
1104 switch (lcd_dma.rotate) {
1105 case 0:
1106 if (!lcd_dma.mirror) {
1107 top = PIXADDR(0, 0);
1108 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1109 /* 1510 DMA requires the bottom address to be 2 more
1110 * than the actual last memory access location. */
1111 if (omap_dma_in_1510_mode() &&
1112 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
1113 bottom += 2;
1114 ei = PIXSTEP(0, 0, 1, 0);
1115 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
1116 } else {
1117 top = PIXADDR(lcd_dma.xres - 1, 0);
1118 bottom = PIXADDR(0, lcd_dma.yres - 1);
1119 ei = PIXSTEP(1, 0, 0, 0);
1120 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
1121 }
1122 en = lcd_dma.xres;
1123 fn = lcd_dma.yres;
1124 break;
1125 case 90:
1126 if (!lcd_dma.mirror) {
1127 top = PIXADDR(0, lcd_dma.yres - 1);
1128 bottom = PIXADDR(lcd_dma.xres - 1, 0);
1129 ei = PIXSTEP(0, 1, 0, 0);
1130 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
1131 } else {
1132 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1133 bottom = PIXADDR(0, 0);
1134 ei = PIXSTEP(0, 1, 0, 0);
1135 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
1136 }
1137 en = lcd_dma.yres;
1138 fn = lcd_dma.xres;
1139 break;
1140 case 180:
1141 if (!lcd_dma.mirror) {
1142 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1143 bottom = PIXADDR(0, 0);
1144 ei = PIXSTEP(1, 0, 0, 0);
1145 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
1146 } else {
1147 top = PIXADDR(0, lcd_dma.yres - 1);
1148 bottom = PIXADDR(lcd_dma.xres - 1, 0);
1149 ei = PIXSTEP(0, 0, 1, 0);
1150 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
1151 }
1152 en = lcd_dma.xres;
1153 fn = lcd_dma.yres;
1154 break;
1155 case 270:
1156 if (!lcd_dma.mirror) {
1157 top = PIXADDR(lcd_dma.xres - 1, 0);
1158 bottom = PIXADDR(0, lcd_dma.yres - 1);
1159 ei = PIXSTEP(0, 0, 0, 1);
1160 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
1161 } else {
1162 top = PIXADDR(0, 0);
1163 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
1164 ei = PIXSTEP(0, 0, 0, 1);
1165 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
1166 }
1167 en = lcd_dma.yres;
1168 fn = lcd_dma.xres;
1169 break;
1170 default:
1171 BUG();
1172 return; /* Supress warning about uninitialized vars */
1173 }
1174
1175 if (omap_dma_in_1510_mode()) {
1176 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
1177 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
1178 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
1179 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
1180
1181 return;
1182 }
1183
1184 /* 1610 regs */
1185 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
1186 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
1187 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
1188 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
1189
1190 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
1191 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
1192
1193 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
1194 w &= ~0x03;
1195 w |= lcd_dma.data_type;
1196 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
1197
1198 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1199 /* Always set the source port as SDRAM for now*/
1200 w &= ~(0x03 << 6);
1201 if (lcd_dma.callback != NULL)
1202 w |= 1 << 1; /* Block interrupt enable */
1203 else
1204 w &= ~(1 << 1);
1205 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1206
1207 if (!(lcd_dma.rotate || lcd_dma.mirror ||
1208 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
1209 return;
1210
1211 w = omap_readw(OMAP1610_DMA_LCD_CCR);
1212 /* Set the double-indexed addressing mode */
1213 w |= (0x03 << 12);
1214 omap_writew(w, OMAP1610_DMA_LCD_CCR);
1215
1216 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
1217 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
1218 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
1219 }
1220
1221 static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
1222 {
1223 u16 w;
1224
1225 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1226 if (unlikely(!(w & (1 << 3)))) {
1227 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
1228 return IRQ_NONE;
1229 }
1230 /* Ack the IRQ */
1231 w |= (1 << 3);
1232 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1233 lcd_dma.active = 0;
1234 if (lcd_dma.callback != NULL)
1235 lcd_dma.callback(w, lcd_dma.cb_data);
1236
1237 return IRQ_HANDLED;
1238 }
1239
1240 int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
1241 void *data)
1242 {
1243 spin_lock_irq(&lcd_dma.lock);
1244 if (lcd_dma.reserved) {
1245 spin_unlock_irq(&lcd_dma.lock);
1246 printk(KERN_ERR "LCD DMA channel already reserved\n");
1247 BUG();
1248 return -EBUSY;
1249 }
1250 lcd_dma.reserved = 1;
1251 spin_unlock_irq(&lcd_dma.lock);
1252 lcd_dma.callback = callback;
1253 lcd_dma.cb_data = data;
1254 lcd_dma.active = 0;
1255 lcd_dma.single_transfer = 0;
1256 lcd_dma.rotate = 0;
1257 lcd_dma.vxres = 0;
1258 lcd_dma.mirror = 0;
1259 lcd_dma.xscale = 0;
1260 lcd_dma.yscale = 0;
1261 lcd_dma.ext_ctrl = 0;
1262 lcd_dma.src_port = 0;
1263
1264 return 0;
1265 }
1266
1267 void omap_free_lcd_dma(void)
1268 {
1269 spin_lock(&lcd_dma.lock);
1270 if (!lcd_dma.reserved) {
1271 spin_unlock(&lcd_dma.lock);
1272 printk(KERN_ERR "LCD DMA is not reserved\n");
1273 BUG();
1274 return;
1275 }
1276 if (!enable_1510_mode)
1277 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
1278 OMAP1610_DMA_LCD_CCR);
1279 lcd_dma.reserved = 0;
1280 spin_unlock(&lcd_dma.lock);
1281 }
1282
1283 void omap_enable_lcd_dma(void)
1284 {
1285 u16 w;
1286
1287 /* Set the Enable bit only if an external controller is
1288 * connected. Otherwise the OMAP internal controller will
1289 * start the transfer when it gets enabled.
1290 */
1291 if (enable_1510_mode || !lcd_dma.ext_ctrl)
1292 return;
1293
1294 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1295 w |= 1 << 8;
1296 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1297
1298 lcd_dma.active = 1;
1299
1300 w = omap_readw(OMAP1610_DMA_LCD_CCR);
1301 w |= 1 << 7;
1302 omap_writew(w, OMAP1610_DMA_LCD_CCR);
1303 }
1304
1305 void omap_setup_lcd_dma(void)
1306 {
1307 BUG_ON(lcd_dma.active);
1308 if (!enable_1510_mode) {
1309 /* Set some reasonable defaults */
1310 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
1311 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
1312 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
1313 }
1314 set_b1_regs();
1315 if (!enable_1510_mode) {
1316 u16 w;
1317
1318 w = omap_readw(OMAP1610_DMA_LCD_CCR);
1319 /* If DMA was already active set the end_prog bit to have
1320 * the programmed register set loaded into the active
1321 * register set.
1322 */
1323 w |= 1 << 11; /* End_prog */
1324 if (!lcd_dma.single_transfer)
1325 w |= (3 << 8); /* Auto_init, repeat */
1326 omap_writew(w, OMAP1610_DMA_LCD_CCR);
1327 }
1328 }
1329
1330 void omap_stop_lcd_dma(void)
1331 {
1332 u16 w;
1333
1334 lcd_dma.active = 0;
1335 if (enable_1510_mode || !lcd_dma.ext_ctrl)
1336 return;
1337
1338 w = omap_readw(OMAP1610_DMA_LCD_CCR);
1339 w &= ~(1 << 7);
1340 omap_writew(w, OMAP1610_DMA_LCD_CCR);
1341
1342 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1343 w &= ~(1 << 8);
1344 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1345 }
1346
1347 int omap_lcd_dma_ext_running(void)
1348 {
1349 return lcd_dma.ext_ctrl && lcd_dma.active;
1350 }
1351
1352 /*----------------------------------------------------------------------------*/
1353
1354 static int __init omap_init_dma(void)
1355 {
1356 int ch, r;
1357
1358 if (cpu_is_omap15xx()) {
1359 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
1360 dma_chan_count = 9;
1361 enable_1510_mode = 1;
1362 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
1363 printk(KERN_INFO "OMAP DMA hardware version %d\n",
1364 omap_readw(OMAP_DMA_HW_ID));
1365 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
1366 (omap_readw(OMAP_DMA_CAPS_0_U) << 16) |
1367 omap_readw(OMAP_DMA_CAPS_0_L),
1368 (omap_readw(OMAP_DMA_CAPS_1_U) << 16) |
1369 omap_readw(OMAP_DMA_CAPS_1_L),
1370 omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3),
1371 omap_readw(OMAP_DMA_CAPS_4));
1372 if (!enable_1510_mode) {
1373 u16 w;
1374
1375 /* Disable OMAP 3.0/3.1 compatibility mode. */
1376 w = omap_readw(OMAP_DMA_GSCR);
1377 w |= 1 << 3;
1378 omap_writew(w, OMAP_DMA_GSCR);
1379 dma_chan_count = 16;
1380 } else
1381 dma_chan_count = 9;
1382 if (cpu_is_omap16xx()) {
1383 u16 w;
1384
1385 /* this would prevent OMAP sleep */
1386 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1387 w &= ~(1 << 8);
1388 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1389 }
1390 } else if (cpu_is_omap24xx()) {
1391 u8 revision = omap_readb(OMAP_DMA4_REVISION);
1392 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
1393 revision >> 4, revision & 0xf);
1394 dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT;
1395 } else {
1396 dma_chan_count = 0;
1397 return 0;
1398 }
1399
1400 memset(&lcd_dma, 0, sizeof(lcd_dma));
1401 spin_lock_init(&lcd_dma.lock);
1402 spin_lock_init(&dma_chan_lock);
1403 memset(&dma_chan, 0, sizeof(dma_chan));
1404
1405 for (ch = 0; ch < dma_chan_count; ch++) {
1406 omap_clear_dma(ch);
1407 dma_chan[ch].dev_id = -1;
1408 dma_chan[ch].next_lch = -1;
1409
1410 if (ch >= 6 && enable_1510_mode)
1411 continue;
1412
1413 if (cpu_class_is_omap1()) {
1414 /* request_irq() doesn't like dev_id (ie. ch) being
1415 * zero, so we have to kludge around this. */
1416 r = request_irq(omap1_dma_irq[ch],
1417 omap1_dma_irq_handler, 0, "DMA",
1418 (void *) (ch + 1));
1419 if (r != 0) {
1420 int i;
1421
1422 printk(KERN_ERR "unable to request IRQ %d "
1423 "for DMA (error %d)\n",
1424 omap1_dma_irq[ch], r);
1425 for (i = 0; i < ch; i++)
1426 free_irq(omap1_dma_irq[i],
1427 (void *) (i + 1));
1428 return r;
1429 }
1430 }
1431 }
1432
1433 if (cpu_is_omap24xx())
1434 setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
1435
1436 /* FIXME: Update LCD DMA to work on 24xx */
1437 if (cpu_class_is_omap1()) {
1438 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
1439 "LCD DMA", NULL);
1440 if (r != 0) {
1441 int i;
1442
1443 printk(KERN_ERR "unable to request IRQ for LCD DMA "
1444 "(error %d)\n", r);
1445 for (i = 0; i < dma_chan_count; i++)
1446 free_irq(omap1_dma_irq[i], (void *) (i + 1));
1447 return r;
1448 }
1449 }
1450
1451 return 0;
1452 }
1453
1454 arch_initcall(omap_init_dma);
1455
1456 EXPORT_SYMBOL(omap_get_dma_src_pos);
1457 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1458 EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
1459 EXPORT_SYMBOL(omap_clear_dma);
1460 EXPORT_SYMBOL(omap_set_dma_priority);
1461 EXPORT_SYMBOL(omap_request_dma);
1462 EXPORT_SYMBOL(omap_free_dma);
1463 EXPORT_SYMBOL(omap_start_dma);
1464 EXPORT_SYMBOL(omap_stop_dma);
1465 EXPORT_SYMBOL(omap_set_dma_callback);
1466 EXPORT_SYMBOL(omap_enable_dma_irq);
1467 EXPORT_SYMBOL(omap_disable_dma_irq);
1468
1469 EXPORT_SYMBOL(omap_set_dma_transfer_params);
1470 EXPORT_SYMBOL(omap_set_dma_color_mode);
1471 EXPORT_SYMBOL(omap_set_dma_write_mode);
1472
1473 EXPORT_SYMBOL(omap_set_dma_src_params);
1474 EXPORT_SYMBOL(omap_set_dma_src_index);
1475 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
1476 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
1477
1478 EXPORT_SYMBOL(omap_set_dma_dest_params);
1479 EXPORT_SYMBOL(omap_set_dma_dest_index);
1480 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
1481 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
1482
1483 EXPORT_SYMBOL(omap_set_dma_params);
1484
1485 EXPORT_SYMBOL(omap_dma_link_lch);
1486 EXPORT_SYMBOL(omap_dma_unlink_lch);
1487
1488 EXPORT_SYMBOL(omap_request_lcd_dma);
1489 EXPORT_SYMBOL(omap_free_lcd_dma);
1490 EXPORT_SYMBOL(omap_enable_lcd_dma);
1491 EXPORT_SYMBOL(omap_setup_lcd_dma);
1492 EXPORT_SYMBOL(omap_stop_lcd_dma);
1493 EXPORT_SYMBOL(omap_lcd_dma_ext_running);
1494 EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1495 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1496 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1497 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1498 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
1499 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
1500 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
1501
hh.org GIT migration