arch/avr32/mach-at32ap/extint.c

   1 /*
   2  * External interrupt handling for AT32AP CPUs
   3  *
   4  * Copyright (C) 2006 Atmel Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/errno.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/irq.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/random.h>
  17
  18 #include <asm/io.h>
  19
  20 #include <asm/arch/sm.h>
  21
  22 #include "sm.h"
  23
  24 static void eim_ack_irq(unsigned int irq)
  25 {
  26         struct at32_sm *sm = get_irq_chip_data(irq);
  27         sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
  28 }
  29
  30 static void eim_mask_irq(unsigned int irq)
  31 {
  32         struct at32_sm *sm = get_irq_chip_data(irq);
  33         sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
  34 }
  35
  36 static void eim_mask_ack_irq(unsigned int irq)
  37 {
  38         struct at32_sm *sm = get_irq_chip_data(irq);
  39         sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
  40         sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
  41 }
  42
  43 static void eim_unmask_irq(unsigned int irq)
  44 {
  45         struct at32_sm *sm = get_irq_chip_data(irq);
  46         sm_writel(sm, EIM_IER, 1 << (irq - sm->eim_first_irq));
  47 }
  48
  49 static int eim_set_irq_type(unsigned int irq, unsigned int flow_type)
  50 {
  51         struct at32_sm *sm = get_irq_chip_data(irq);
  52         unsigned int i = irq - sm->eim_first_irq;
  53         u32 mode, edge, level;
  54         unsigned long flags;
  55         int ret = 0;
  56
  57         flow_type &= IRQ_TYPE_SENSE_MASK;
  58
  59         spin_lock_irqsave(&sm->lock, flags);
  60
  61         mode = sm_readl(sm, EIM_MODE);
  62         edge = sm_readl(sm, EIM_EDGE);
  63         level = sm_readl(sm, EIM_LEVEL);
  64
  65         switch (flow_type) {
  66         case IRQ_TYPE_LEVEL_LOW:
  67                 mode |= 1 << i;
  68                 level &= ~(1 << i);
  69                 break;
  70         case IRQ_TYPE_LEVEL_HIGH:
  71                 mode |= 1 << i;
  72                 level |= 1 << i;
  73                 break;
  74         case IRQ_TYPE_EDGE_RISING:
  75                 mode &= ~(1 << i);
  76                 edge |= 1 << i;
  77                 break;
  78         case IRQ_TYPE_EDGE_FALLING:
  79                 mode &= ~(1 << i);
  80                 edge &= ~(1 << i);
  81                 break;
  82         default:
  83                 ret = -EINVAL;
  84                 break;
  85         }
  86
  87         sm_writel(sm, EIM_MODE, mode);
  88         sm_writel(sm, EIM_EDGE, edge);
  89         sm_writel(sm, EIM_LEVEL, level);
  90
  91         spin_unlock_irqrestore(&sm->lock, flags);
  92
  93         return ret;
  94 }
  95
  96 struct irq_chip eim_chip = {
  97         .name           = "eim",
  98         .ack            = eim_ack_irq,
  99         .mask           = eim_mask_irq,
 100         .mask_ack       = eim_mask_ack_irq,
 101         .unmask         = eim_unmask_irq,
 102         .set_type       = eim_set_irq_type,
 103 };
 104
 105 static void demux_eim_irq(unsigned int irq, struct irq_desc *desc)
 106 {
 107         struct at32_sm *sm = desc->handler_data;
 108         struct irq_desc *ext_desc;
 109         unsigned long status, pending;
 110         unsigned int i, ext_irq;
 111
 112         spin_lock(&sm->lock);
 113
 114         status = sm_readl(sm, EIM_ISR);
 115         pending = status & sm_readl(sm, EIM_IMR);
 116
 117         while (pending) {
 118                 i = fls(pending) - 1;
 119                 pending &= ~(1 << i);
 120
 121                 ext_irq = i + sm->eim_first_irq;
 122                 ext_desc = irq_desc + ext_irq;
 123                 ext_desc->handle_irq(ext_irq, ext_desc);
 124         }
 125
 126         spin_unlock(&sm->lock);
 127 }
 128
 129 static int __init eim_init(void)
 130 {
 131         struct at32_sm *sm = &system_manager;
 132         unsigned int i;
 133         unsigned int nr_irqs;
 134         unsigned int int_irq;
 135         u32 pattern;
 136
 137         /*
 138          * The EIM is really the same module as SM, so register
 139          * mapping, etc. has been taken care of already.
 140          */
 141
 142         /*
 143          * Find out how many interrupt lines that are actually
 144          * implemented in hardware.
 145          */
 146         sm_writel(sm, EIM_IDR, ~0UL);
 147         sm_writel(sm, EIM_MODE, ~0UL);
 148         pattern = sm_readl(sm, EIM_MODE);
 149         nr_irqs = fls(pattern);
 150
 151         sm->eim_chip = &eim_chip;
 152
 153         for (i = 0; i < nr_irqs; i++) {
 154                 set_irq_chip(sm->eim_first_irq + i, &eim_chip);
 155                 set_irq_chip_data(sm->eim_first_irq + i, sm);
 156         }
 157
 158         int_irq = platform_get_irq_byname(sm->pdev, "eim");
 159
 160         set_irq_chained_handler(int_irq, demux_eim_irq);
 161         set_irq_data(int_irq, sm);
 162
 163         printk("EIM: External Interrupt Module at 0x%p, IRQ %u\n",
 164                sm->regs, int_irq);
 165         printk("EIM: Handling %u external IRQs, starting with IRQ %u\n",
 166                nr_irqs, sm->eim_first_irq);
 167
 168         return 0;
 169 }
 170 arch_initcall(eim_init);