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1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/pci.h>
35 #include <linux/msi.h>
36 #include <linux/htirq.h>
38 #include <asm/io.h>
39 #include <asm/smp.h>
40 #include <asm/desc.h>
41 #include <asm/timer.h>
42 #include <asm/i8259.h>
43 #include <asm/nmi.h>
44 #include <asm/msidef.h>
45 #include <asm/hypertransport.h>
47 #include <mach_apic.h>
48 #include <mach_apicdef.h>
50 #include "io_ports.h"
52 int (*ioapic_renumber_irq)(int ioapic, int irq);
53 atomic_t irq_mis_count;
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58 static DEFINE_SPINLOCK(ioapic_lock);
59 static DEFINE_SPINLOCK(vector_lock);
61 int timer_over_8254 __initdata = 1;
64 * Is the SiS APIC rmw bug present ?
65 * -1 = don't know, 0 = no, 1 = yes
67 int sis_apic_bug = -1;
70 * # of IRQ routing registers
72 int nr_ioapic_registers[MAX_IO_APICS];
74 static int disable_timer_pin_1 __initdata;
77 * Rough estimation of how many shared IRQs there are, can
78 * be changed anytime.
80 #define MAX_PLUS_SHARED_IRQS NR_IRQS
81 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
84 * This is performance-critical, we want to do it O(1)
86 * the indexing order of this array favors 1:1 mappings
87 * between pins and IRQs.
90 static struct irq_pin_list {
91 int apic, pin, next;
92 } irq_2_pin[PIN_MAP_SIZE];
94 struct io_apic {
95 unsigned int index;
96 unsigned int unused[3];
97 unsigned int data;
100 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
102 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
103 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
106 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
108 struct io_apic __iomem *io_apic = io_apic_base(apic);
109 writel(reg, &io_apic->index);
110 return readl(&io_apic->data);
113 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
115 struct io_apic __iomem *io_apic = io_apic_base(apic);
116 writel(reg, &io_apic->index);
117 writel(value, &io_apic->data);
121 * Re-write a value: to be used for read-modify-write
122 * cycles where the read already set up the index register.
124 * Older SiS APIC requires we rewrite the index register
126 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
128 volatile struct io_apic *io_apic = io_apic_base(apic);
129 if (sis_apic_bug)
130 writel(reg, &io_apic->index);
131 writel(value, &io_apic->data);
134 union entry_union {
135 struct { u32 w1, w2; };
136 struct IO_APIC_route_entry entry;
139 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
141 union entry_union eu;
142 unsigned long flags;
143 spin_lock_irqsave(&ioapic_lock, flags);
144 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
145 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
146 spin_unlock_irqrestore(&ioapic_lock, flags);
147 return eu.entry;
151 * When we write a new IO APIC routing entry, we need to write the high
152 * word first! If the mask bit in the low word is clear, we will enable
153 * the interrupt, and we need to make sure the entry is fully populated
154 * before that happens.
156 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
158 unsigned long flags;
159 union entry_union eu;
160 eu.entry = e;
161 spin_lock_irqsave(&ioapic_lock, flags);
162 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
163 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
164 spin_unlock_irqrestore(&ioapic_lock, flags);
168 * When we mask an IO APIC routing entry, we need to write the low
169 * word first, in order to set the mask bit before we change the
170 * high bits!
172 static void ioapic_mask_entry(int apic, int pin)
174 unsigned long flags;
175 union entry_union eu = { .entry.mask = 1 };
177 spin_lock_irqsave(&ioapic_lock, flags);
178 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
179 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
180 spin_unlock_irqrestore(&ioapic_lock, flags);
184 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
185 * shared ISA-space IRQs, so we have to support them. We are super
186 * fast in the common case, and fast for shared ISA-space IRQs.
188 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
190 static int first_free_entry = NR_IRQS;
191 struct irq_pin_list *entry = irq_2_pin + irq;
193 while (entry->next)
194 entry = irq_2_pin + entry->next;
196 if (entry->pin != -1) {
197 entry->next = first_free_entry;
198 entry = irq_2_pin + entry->next;
199 if (++first_free_entry >= PIN_MAP_SIZE)
200 panic("io_apic.c: whoops");
202 entry->apic = apic;
203 entry->pin = pin;
207 * Reroute an IRQ to a different pin.
209 static void __init replace_pin_at_irq(unsigned int irq,
210 int oldapic, int oldpin,
211 int newapic, int newpin)
213 struct irq_pin_list *entry = irq_2_pin + irq;
215 while (1) {
216 if (entry->apic == oldapic && entry->pin == oldpin) {
217 entry->apic = newapic;
218 entry->pin = newpin;
220 if (!entry->next)
221 break;
222 entry = irq_2_pin + entry->next;
226 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
228 struct irq_pin_list *entry = irq_2_pin + irq;
229 unsigned int pin, reg;
231 for (;;) {
232 pin = entry->pin;
233 if (pin == -1)
234 break;
235 reg = io_apic_read(entry->apic, 0x10 + pin*2);
236 reg &= ~disable;
237 reg |= enable;
238 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
239 if (!entry->next)
240 break;
241 entry = irq_2_pin + entry->next;
245 /* mask = 1 */
246 static void __mask_IO_APIC_irq (unsigned int irq)
248 __modify_IO_APIC_irq(irq, 0x00010000, 0);
251 /* mask = 0 */
252 static void __unmask_IO_APIC_irq (unsigned int irq)
254 __modify_IO_APIC_irq(irq, 0, 0x00010000);
257 /* mask = 1, trigger = 0 */
258 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
260 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
263 /* mask = 0, trigger = 1 */
264 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
266 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
269 static void mask_IO_APIC_irq (unsigned int irq)
271 unsigned long flags;
273 spin_lock_irqsave(&ioapic_lock, flags);
274 __mask_IO_APIC_irq(irq);
275 spin_unlock_irqrestore(&ioapic_lock, flags);
278 static void unmask_IO_APIC_irq (unsigned int irq)
280 unsigned long flags;
282 spin_lock_irqsave(&ioapic_lock, flags);
283 __unmask_IO_APIC_irq(irq);
284 spin_unlock_irqrestore(&ioapic_lock, flags);
287 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
289 struct IO_APIC_route_entry entry;
291 /* Check delivery_mode to be sure we're not clearing an SMI pin */
292 entry = ioapic_read_entry(apic, pin);
293 if (entry.delivery_mode == dest_SMI)
294 return;
297 * Disable it in the IO-APIC irq-routing table:
299 ioapic_mask_entry(apic, pin);
302 static void clear_IO_APIC (void)
304 int apic, pin;
306 for (apic = 0; apic < nr_ioapics; apic++)
307 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
308 clear_IO_APIC_pin(apic, pin);
311 #ifdef CONFIG_SMP
312 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
314 unsigned long flags;
315 int pin;
316 struct irq_pin_list *entry = irq_2_pin + irq;
317 unsigned int apicid_value;
318 cpumask_t tmp;
320 cpus_and(tmp, cpumask, cpu_online_map);
321 if (cpus_empty(tmp))
322 tmp = TARGET_CPUS;
324 cpus_and(cpumask, tmp, CPU_MASK_ALL);
326 apicid_value = cpu_mask_to_apicid(cpumask);
327 /* Prepare to do the io_apic_write */
328 apicid_value = apicid_value << 24;
329 spin_lock_irqsave(&ioapic_lock, flags);
330 for (;;) {
331 pin = entry->pin;
332 if (pin == -1)
333 break;
334 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
335 if (!entry->next)
336 break;
337 entry = irq_2_pin + entry->next;
339 set_native_irq_info(irq, cpumask);
340 spin_unlock_irqrestore(&ioapic_lock, flags);
343 #if defined(CONFIG_IRQBALANCE)
344 # include <asm/processor.h> /* kernel_thread() */
345 # include <linux/kernel_stat.h> /* kstat */
346 # include <linux/slab.h> /* kmalloc() */
347 # include <linux/timer.h> /* time_after() */
349 #ifdef CONFIG_BALANCED_IRQ_DEBUG
350 # define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
351 # define Dprintk(x...) do { TDprintk(x); } while (0)
352 # else
353 # define TDprintk(x...)
354 # define Dprintk(x...)
355 # endif
357 #define IRQBALANCE_CHECK_ARCH -999
358 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
359 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
360 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
361 #define BALANCED_IRQ_LESS_DELTA (HZ)
363 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
364 static int physical_balance __read_mostly;
365 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
367 static struct irq_cpu_info {
368 unsigned long * last_irq;
369 unsigned long * irq_delta;
370 unsigned long irq;
371 } irq_cpu_data[NR_CPUS];
373 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
374 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
375 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
377 #define IDLE_ENOUGH(cpu,now) \
378 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
380 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
382 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
384 static cpumask_t balance_irq_affinity[NR_IRQS] = {
385 [0 ... NR_IRQS-1] = CPU_MASK_ALL
388 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
390 balance_irq_affinity[irq] = mask;
393 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
394 unsigned long now, int direction)
396 int search_idle = 1;
397 int cpu = curr_cpu;
399 goto inside;
401 do {
402 if (unlikely(cpu == curr_cpu))
403 search_idle = 0;
404 inside:
405 if (direction == 1) {
406 cpu++;
407 if (cpu >= NR_CPUS)
408 cpu = 0;
409 } else {
410 cpu--;
411 if (cpu == -1)
412 cpu = NR_CPUS-1;
414 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
415 (search_idle && !IDLE_ENOUGH(cpu,now)));
417 return cpu;
420 static inline void balance_irq(int cpu, int irq)
422 unsigned long now = jiffies;
423 cpumask_t allowed_mask;
424 unsigned int new_cpu;
426 if (irqbalance_disabled)
427 return;
429 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
430 new_cpu = move(cpu, allowed_mask, now, 1);
431 if (cpu != new_cpu) {
432 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
436 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
438 int i, j;
439 Dprintk("Rotating IRQs among CPUs.\n");
440 for_each_online_cpu(i) {
441 for (j = 0; j < NR_IRQS; j++) {
442 if (!irq_desc[j].action)
443 continue;
444 /* Is it a significant load ? */
445 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
446 useful_load_threshold)
447 continue;
448 balance_irq(i, j);
451 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
452 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
453 return;
456 static void do_irq_balance(void)
458 int i, j;
459 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
460 unsigned long move_this_load = 0;
461 int max_loaded = 0, min_loaded = 0;
462 int load;
463 unsigned long useful_load_threshold = balanced_irq_interval + 10;
464 int selected_irq;
465 int tmp_loaded, first_attempt = 1;
466 unsigned long tmp_cpu_irq;
467 unsigned long imbalance = 0;
468 cpumask_t allowed_mask, target_cpu_mask, tmp;
470 for_each_possible_cpu(i) {
471 int package_index;
472 CPU_IRQ(i) = 0;
473 if (!cpu_online(i))
474 continue;
475 package_index = CPU_TO_PACKAGEINDEX(i);
476 for (j = 0; j < NR_IRQS; j++) {
477 unsigned long value_now, delta;
478 /* Is this an active IRQ? */
479 if (!irq_desc[j].action)
480 continue;
481 if ( package_index == i )
482 IRQ_DELTA(package_index,j) = 0;
483 /* Determine the total count per processor per IRQ */
484 value_now = (unsigned long) kstat_cpu(i).irqs[j];
486 /* Determine the activity per processor per IRQ */
487 delta = value_now - LAST_CPU_IRQ(i,j);
489 /* Update last_cpu_irq[][] for the next time */
490 LAST_CPU_IRQ(i,j) = value_now;
492 /* Ignore IRQs whose rate is less than the clock */
493 if (delta < useful_load_threshold)
494 continue;
495 /* update the load for the processor or package total */
496 IRQ_DELTA(package_index,j) += delta;
498 /* Keep track of the higher numbered sibling as well */
499 if (i != package_index)
500 CPU_IRQ(i) += delta;
502 * We have sibling A and sibling B in the package
504 * cpu_irq[A] = load for cpu A + load for cpu B
505 * cpu_irq[B] = load for cpu B
507 CPU_IRQ(package_index) += delta;
510 /* Find the least loaded processor package */
511 for_each_online_cpu(i) {
512 if (i != CPU_TO_PACKAGEINDEX(i))
513 continue;
514 if (min_cpu_irq > CPU_IRQ(i)) {
515 min_cpu_irq = CPU_IRQ(i);
516 min_loaded = i;
519 max_cpu_irq = ULONG_MAX;
521 tryanothercpu:
522 /* Look for heaviest loaded processor.
523 * We may come back to get the next heaviest loaded processor.
524 * Skip processors with trivial loads.
526 tmp_cpu_irq = 0;
527 tmp_loaded = -1;
528 for_each_online_cpu(i) {
529 if (i != CPU_TO_PACKAGEINDEX(i))
530 continue;
531 if (max_cpu_irq <= CPU_IRQ(i))
532 continue;
533 if (tmp_cpu_irq < CPU_IRQ(i)) {
534 tmp_cpu_irq = CPU_IRQ(i);
535 tmp_loaded = i;
539 if (tmp_loaded == -1) {
540 /* In the case of small number of heavy interrupt sources,
541 * loading some of the cpus too much. We use Ingo's original
542 * approach to rotate them around.
544 if (!first_attempt && imbalance >= useful_load_threshold) {
545 rotate_irqs_among_cpus(useful_load_threshold);
546 return;
548 goto not_worth_the_effort;
551 first_attempt = 0; /* heaviest search */
552 max_cpu_irq = tmp_cpu_irq; /* load */
553 max_loaded = tmp_loaded; /* processor */
554 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
556 Dprintk("max_loaded cpu = %d\n", max_loaded);
557 Dprintk("min_loaded cpu = %d\n", min_loaded);
558 Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
559 Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
560 Dprintk("load imbalance = %lu\n", imbalance);
562 /* if imbalance is less than approx 10% of max load, then
563 * observe diminishing returns action. - quit
565 if (imbalance < (max_cpu_irq >> 3)) {
566 Dprintk("Imbalance too trivial\n");
567 goto not_worth_the_effort;
570 tryanotherirq:
571 /* if we select an IRQ to move that can't go where we want, then
572 * see if there is another one to try.
574 move_this_load = 0;
575 selected_irq = -1;
576 for (j = 0; j < NR_IRQS; j++) {
577 /* Is this an active IRQ? */
578 if (!irq_desc[j].action)
579 continue;
580 if (imbalance <= IRQ_DELTA(max_loaded,j))
581 continue;
582 /* Try to find the IRQ that is closest to the imbalance
583 * without going over.
585 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
586 move_this_load = IRQ_DELTA(max_loaded,j);
587 selected_irq = j;
590 if (selected_irq == -1) {
591 goto tryanothercpu;
594 imbalance = move_this_load;
596 /* For physical_balance case, we accumlated both load
597 * values in the one of the siblings cpu_irq[],
598 * to use the same code for physical and logical processors
599 * as much as possible.
601 * NOTE: the cpu_irq[] array holds the sum of the load for
602 * sibling A and sibling B in the slot for the lowest numbered
603 * sibling (A), _AND_ the load for sibling B in the slot for
604 * the higher numbered sibling.
606 * We seek the least loaded sibling by making the comparison
607 * (A+B)/2 vs B
609 load = CPU_IRQ(min_loaded) >> 1;
610 for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
611 if (load > CPU_IRQ(j)) {
612 /* This won't change cpu_sibling_map[min_loaded] */
613 load = CPU_IRQ(j);
614 min_loaded = j;
618 cpus_and(allowed_mask,
619 cpu_online_map,
620 balance_irq_affinity[selected_irq]);
621 target_cpu_mask = cpumask_of_cpu(min_loaded);
622 cpus_and(tmp, target_cpu_mask, allowed_mask);
624 if (!cpus_empty(tmp)) {
626 Dprintk("irq = %d moved to cpu = %d\n",
627 selected_irq, min_loaded);
628 /* mark for change destination */
629 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
631 /* Since we made a change, come back sooner to
632 * check for more variation.
634 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
635 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
636 return;
638 goto tryanotherirq;
640 not_worth_the_effort:
642 * if we did not find an IRQ to move, then adjust the time interval
643 * upward
645 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
646 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
647 Dprintk("IRQ worth rotating not found\n");
648 return;
651 static int balanced_irq(void *unused)
653 int i;
654 unsigned long prev_balance_time = jiffies;
655 long time_remaining = balanced_irq_interval;
657 daemonize("kirqd");
659 /* push everything to CPU 0 to give us a starting point. */
660 for (i = 0 ; i < NR_IRQS ; i++) {
661 irq_desc[i].pending_mask = cpumask_of_cpu(0);
662 set_pending_irq(i, cpumask_of_cpu(0));
665 for ( ; ; ) {
666 time_remaining = schedule_timeout_interruptible(time_remaining);
667 try_to_freeze();
668 if (time_after(jiffies,
669 prev_balance_time+balanced_irq_interval)) {
670 preempt_disable();
671 do_irq_balance();
672 prev_balance_time = jiffies;
673 time_remaining = balanced_irq_interval;
674 preempt_enable();
677 return 0;
680 static int __init balanced_irq_init(void)
682 int i;
683 struct cpuinfo_x86 *c;
684 cpumask_t tmp;
686 cpus_shift_right(tmp, cpu_online_map, 2);
687 c = &boot_cpu_data;
688 /* When not overwritten by the command line ask subarchitecture. */
689 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
690 irqbalance_disabled = NO_BALANCE_IRQ;
691 if (irqbalance_disabled)
692 return 0;
694 /* disable irqbalance completely if there is only one processor online */
695 if (num_online_cpus() < 2) {
696 irqbalance_disabled = 1;
697 return 0;
700 * Enable physical balance only if more than 1 physical processor
701 * is present
703 if (smp_num_siblings > 1 && !cpus_empty(tmp))
704 physical_balance = 1;
706 for_each_online_cpu(i) {
707 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
708 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
709 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
710 printk(KERN_ERR "balanced_irq_init: out of memory");
711 goto failed;
713 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
714 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
717 printk(KERN_INFO "Starting balanced_irq\n");
718 if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
719 return 0;
720 else
721 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
722 failed:
723 for_each_possible_cpu(i) {
724 kfree(irq_cpu_data[i].irq_delta);
725 irq_cpu_data[i].irq_delta = NULL;
726 kfree(irq_cpu_data[i].last_irq);
727 irq_cpu_data[i].last_irq = NULL;
729 return 0;
732 int __init irqbalance_disable(char *str)
734 irqbalance_disabled = 1;
735 return 1;
738 __setup("noirqbalance", irqbalance_disable);
740 late_initcall(balanced_irq_init);
741 #endif /* CONFIG_IRQBALANCE */
742 #endif /* CONFIG_SMP */
744 #ifndef CONFIG_SMP
745 void fastcall send_IPI_self(int vector)
747 unsigned int cfg;
750 * Wait for idle.
752 apic_wait_icr_idle();
753 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
755 * Send the IPI. The write to APIC_ICR fires this off.
757 apic_write_around(APIC_ICR, cfg);
759 #endif /* !CONFIG_SMP */
763 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
764 * specific CPU-side IRQs.
767 #define MAX_PIRQS 8
768 static int pirq_entries [MAX_PIRQS];
769 static int pirqs_enabled;
770 int skip_ioapic_setup;
772 static int __init ioapic_setup(char *str)
774 skip_ioapic_setup = 1;
775 return 1;
778 __setup("noapic", ioapic_setup);
780 static int __init ioapic_pirq_setup(char *str)
782 int i, max;
783 int ints[MAX_PIRQS+1];
785 get_options(str, ARRAY_SIZE(ints), ints);
787 for (i = 0; i < MAX_PIRQS; i++)
788 pirq_entries[i] = -1;
790 pirqs_enabled = 1;
791 apic_printk(APIC_VERBOSE, KERN_INFO
792 "PIRQ redirection, working around broken MP-BIOS.\n");
793 max = MAX_PIRQS;
794 if (ints[0] < MAX_PIRQS)
795 max = ints[0];
797 for (i = 0; i < max; i++) {
798 apic_printk(APIC_VERBOSE, KERN_DEBUG
799 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
801 * PIRQs are mapped upside down, usually.
803 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
805 return 1;
808 __setup("pirq=", ioapic_pirq_setup);
811 * Find the IRQ entry number of a certain pin.
813 static int find_irq_entry(int apic, int pin, int type)
815 int i;
817 for (i = 0; i < mp_irq_entries; i++)
818 if (mp_irqs[i].mpc_irqtype == type &&
819 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
820 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
821 mp_irqs[i].mpc_dstirq == pin)
822 return i;
824 return -1;
828 * Find the pin to which IRQ[irq] (ISA) is connected
830 static int __init find_isa_irq_pin(int irq, int type)
832 int i;
834 for (i = 0; i < mp_irq_entries; i++) {
835 int lbus = mp_irqs[i].mpc_srcbus;
837 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
838 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
839 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
840 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
841 ) &&
842 (mp_irqs[i].mpc_irqtype == type) &&
843 (mp_irqs[i].mpc_srcbusirq == irq))
845 return mp_irqs[i].mpc_dstirq;
847 return -1;
850 static int __init find_isa_irq_apic(int irq, int type)
852 int i;
854 for (i = 0; i < mp_irq_entries; i++) {
855 int lbus = mp_irqs[i].mpc_srcbus;
857 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
858 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
859 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
860 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
861 ) &&
862 (mp_irqs[i].mpc_irqtype == type) &&
863 (mp_irqs[i].mpc_srcbusirq == irq))
864 break;
866 if (i < mp_irq_entries) {
867 int apic;
868 for(apic = 0; apic < nr_ioapics; apic++) {
869 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
870 return apic;
874 return -1;
878 * Find a specific PCI IRQ entry.
879 * Not an __init, possibly needed by modules
881 static int pin_2_irq(int idx, int apic, int pin);
883 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
885 int apic, i, best_guess = -1;
887 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
888 "slot:%d, pin:%d.\n", bus, slot, pin);
889 if (mp_bus_id_to_pci_bus[bus] == -1) {
890 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
891 return -1;
893 for (i = 0; i < mp_irq_entries; i++) {
894 int lbus = mp_irqs[i].mpc_srcbus;
896 for (apic = 0; apic < nr_ioapics; apic++)
897 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
898 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
899 break;
901 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
902 !mp_irqs[i].mpc_irqtype &&
903 (bus == lbus) &&
904 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
905 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
907 if (!(apic || IO_APIC_IRQ(irq)))
908 continue;
910 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
911 return irq;
913 * Use the first all-but-pin matching entry as a
914 * best-guess fuzzy result for broken mptables.
916 if (best_guess < 0)
917 best_guess = irq;
920 return best_guess;
922 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
925 * This function currently is only a helper for the i386 smp boot process where
926 * we need to reprogram the ioredtbls to cater for the cpus which have come online
927 * so mask in all cases should simply be TARGET_CPUS
929 #ifdef CONFIG_SMP
930 void __init setup_ioapic_dest(void)
932 int pin, ioapic, irq, irq_entry;
934 if (skip_ioapic_setup == 1)
935 return;
937 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
938 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
939 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
940 if (irq_entry == -1)
941 continue;
942 irq = pin_2_irq(irq_entry, ioapic, pin);
943 set_ioapic_affinity_irq(irq, TARGET_CPUS);
948 #endif
951 * EISA Edge/Level control register, ELCR
953 static int EISA_ELCR(unsigned int irq)
955 if (irq < 16) {
956 unsigned int port = 0x4d0 + (irq >> 3);
957 return (inb(port) >> (irq & 7)) & 1;
959 apic_printk(APIC_VERBOSE, KERN_INFO
960 "Broken MPtable reports ISA irq %d\n", irq);
961 return 0;
964 /* EISA interrupts are always polarity zero and can be edge or level
965 * trigger depending on the ELCR value. If an interrupt is listed as
966 * EISA conforming in the MP table, that means its trigger type must
967 * be read in from the ELCR */
969 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
970 #define default_EISA_polarity(idx) (0)
972 /* ISA interrupts are always polarity zero edge triggered,
973 * when listed as conforming in the MP table. */
975 #define default_ISA_trigger(idx) (0)
976 #define default_ISA_polarity(idx) (0)
978 /* PCI interrupts are always polarity one level triggered,
979 * when listed as conforming in the MP table. */
981 #define default_PCI_trigger(idx) (1)
982 #define default_PCI_polarity(idx) (1)
984 /* MCA interrupts are always polarity zero level triggered,
985 * when listed as conforming in the MP table. */
987 #define default_MCA_trigger(idx) (1)
988 #define default_MCA_polarity(idx) (0)
990 /* NEC98 interrupts are always polarity zero edge triggered,
991 * when listed as conforming in the MP table. */
993 #define default_NEC98_trigger(idx) (0)
994 #define default_NEC98_polarity(idx) (0)
996 static int __init MPBIOS_polarity(int idx)
998 int bus = mp_irqs[idx].mpc_srcbus;
999 int polarity;
1002 * Determine IRQ line polarity (high active or low active):
1004 switch (mp_irqs[idx].mpc_irqflag & 3)
1006 case 0: /* conforms, ie. bus-type dependent polarity */
1008 switch (mp_bus_id_to_type[bus])
1010 case MP_BUS_ISA: /* ISA pin */
1012 polarity = default_ISA_polarity(idx);
1013 break;
1015 case MP_BUS_EISA: /* EISA pin */
1017 polarity = default_EISA_polarity(idx);
1018 break;
1020 case MP_BUS_PCI: /* PCI pin */
1022 polarity = default_PCI_polarity(idx);
1023 break;
1025 case MP_BUS_MCA: /* MCA pin */
1027 polarity = default_MCA_polarity(idx);
1028 break;
1030 case MP_BUS_NEC98: /* NEC 98 pin */
1032 polarity = default_NEC98_polarity(idx);
1033 break;
1035 default:
1037 printk(KERN_WARNING "broken BIOS!!\n");
1038 polarity = 1;
1039 break;
1042 break;
1044 case 1: /* high active */
1046 polarity = 0;
1047 break;
1049 case 2: /* reserved */
1051 printk(KERN_WARNING "broken BIOS!!\n");
1052 polarity = 1;
1053 break;
1055 case 3: /* low active */
1057 polarity = 1;
1058 break;
1060 default: /* invalid */
1062 printk(KERN_WARNING "broken BIOS!!\n");
1063 polarity = 1;
1064 break;
1067 return polarity;
1070 static int MPBIOS_trigger(int idx)
1072 int bus = mp_irqs[idx].mpc_srcbus;
1073 int trigger;
1076 * Determine IRQ trigger mode (edge or level sensitive):
1078 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1080 case 0: /* conforms, ie. bus-type dependent */
1082 switch (mp_bus_id_to_type[bus])
1084 case MP_BUS_ISA: /* ISA pin */
1086 trigger = default_ISA_trigger(idx);
1087 break;
1089 case MP_BUS_EISA: /* EISA pin */
1091 trigger = default_EISA_trigger(idx);
1092 break;
1094 case MP_BUS_PCI: /* PCI pin */
1096 trigger = default_PCI_trigger(idx);
1097 break;
1099 case MP_BUS_MCA: /* MCA pin */
1101 trigger = default_MCA_trigger(idx);
1102 break;
1104 case MP_BUS_NEC98: /* NEC 98 pin */
1106 trigger = default_NEC98_trigger(idx);
1107 break;
1109 default:
1111 printk(KERN_WARNING "broken BIOS!!\n");
1112 trigger = 1;
1113 break;
1116 break;
1118 case 1: /* edge */
1120 trigger = 0;
1121 break;
1123 case 2: /* reserved */
1125 printk(KERN_WARNING "broken BIOS!!\n");
1126 trigger = 1;
1127 break;
1129 case 3: /* level */
1131 trigger = 1;
1132 break;
1134 default: /* invalid */
1136 printk(KERN_WARNING "broken BIOS!!\n");
1137 trigger = 0;
1138 break;
1141 return trigger;
1144 static inline int irq_polarity(int idx)
1146 return MPBIOS_polarity(idx);
1149 static inline int irq_trigger(int idx)
1151 return MPBIOS_trigger(idx);
1154 static int pin_2_irq(int idx, int apic, int pin)
1156 int irq, i;
1157 int bus = mp_irqs[idx].mpc_srcbus;
1160 * Debugging check, we are in big trouble if this message pops up!
1162 if (mp_irqs[idx].mpc_dstirq != pin)
1163 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1165 switch (mp_bus_id_to_type[bus])
1167 case MP_BUS_ISA: /* ISA pin */
1168 case MP_BUS_EISA:
1169 case MP_BUS_MCA:
1170 case MP_BUS_NEC98:
1172 irq = mp_irqs[idx].mpc_srcbusirq;
1173 break;
1175 case MP_BUS_PCI: /* PCI pin */
1178 * PCI IRQs are mapped in order
1180 i = irq = 0;
1181 while (i < apic)
1182 irq += nr_ioapic_registers[i++];
1183 irq += pin;
1186 * For MPS mode, so far only needed by ES7000 platform
1188 if (ioapic_renumber_irq)
1189 irq = ioapic_renumber_irq(apic, irq);
1191 break;
1193 default:
1195 printk(KERN_ERR "unknown bus type %d.\n",bus);
1196 irq = 0;
1197 break;
1202 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1204 if ((pin >= 16) && (pin <= 23)) {
1205 if (pirq_entries[pin-16] != -1) {
1206 if (!pirq_entries[pin-16]) {
1207 apic_printk(APIC_VERBOSE, KERN_DEBUG
1208 "disabling PIRQ%d\n", pin-16);
1209 } else {
1210 irq = pirq_entries[pin-16];
1211 apic_printk(APIC_VERBOSE, KERN_DEBUG
1212 "using PIRQ%d -> IRQ %d\n",
1213 pin-16, irq);
1217 return irq;
1220 static inline int IO_APIC_irq_trigger(int irq)
1222 int apic, idx, pin;
1224 for (apic = 0; apic < nr_ioapics; apic++) {
1225 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1226 idx = find_irq_entry(apic,pin,mp_INT);
1227 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1228 return irq_trigger(idx);
1232 * nonexistent IRQs are edge default
1234 return 0;
1237 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1238 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1240 static int __assign_irq_vector(int irq)
1242 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1243 int vector;
1245 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1247 if (irq_vector[irq] > 0)
1248 return irq_vector[irq];
1250 current_vector += 8;
1251 if (current_vector == SYSCALL_VECTOR)
1252 current_vector += 8;
1254 if (current_vector >= FIRST_SYSTEM_VECTOR) {
1255 offset++;
1256 if (!(offset % 8))
1257 return -ENOSPC;
1258 current_vector = FIRST_DEVICE_VECTOR + offset;
1261 vector = current_vector;
1262 irq_vector[irq] = vector;
1264 return vector;
1267 static int assign_irq_vector(int irq)
1269 unsigned long flags;
1270 int vector;
1272 spin_lock_irqsave(&vector_lock, flags);
1273 vector = __assign_irq_vector(irq);
1274 spin_unlock_irqrestore(&vector_lock, flags);
1276 return vector;
1278 static struct irq_chip ioapic_chip;
1280 #define IOAPIC_AUTO -1
1281 #define IOAPIC_EDGE 0
1282 #define IOAPIC_LEVEL 1
1284 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1286 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1287 trigger == IOAPIC_LEVEL)
1288 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1289 handle_fasteoi_irq, "fasteoi");
1290 else {
1291 irq_desc[irq].status |= IRQ_DELAYED_DISABLE;
1292 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1293 handle_edge_irq, "edge");
1295 set_intr_gate(vector, interrupt[irq]);
1298 static void __init setup_IO_APIC_irqs(void)
1300 struct IO_APIC_route_entry entry;
1301 int apic, pin, idx, irq, first_notcon = 1, vector;
1302 unsigned long flags;
1304 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1306 for (apic = 0; apic < nr_ioapics; apic++) {
1307 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1310 * add it to the IO-APIC irq-routing table:
1312 memset(&entry,0,sizeof(entry));
1314 entry.delivery_mode = INT_DELIVERY_MODE;
1315 entry.dest_mode = INT_DEST_MODE;
1316 entry.mask = 0; /* enable IRQ */
1317 entry.dest.logical.logical_dest =
1318 cpu_mask_to_apicid(TARGET_CPUS);
1320 idx = find_irq_entry(apic,pin,mp_INT);
1321 if (idx == -1) {
1322 if (first_notcon) {
1323 apic_printk(APIC_VERBOSE, KERN_DEBUG
1324 " IO-APIC (apicid-pin) %d-%d",
1325 mp_ioapics[apic].mpc_apicid,
1326 pin);
1327 first_notcon = 0;
1328 } else
1329 apic_printk(APIC_VERBOSE, ", %d-%d",
1330 mp_ioapics[apic].mpc_apicid, pin);
1331 continue;
1334 entry.trigger = irq_trigger(idx);
1335 entry.polarity = irq_polarity(idx);
1337 if (irq_trigger(idx)) {
1338 entry.trigger = 1;
1339 entry.mask = 1;
1342 irq = pin_2_irq(idx, apic, pin);
1344 * skip adding the timer int on secondary nodes, which causes
1345 * a small but painful rift in the time-space continuum
1347 if (multi_timer_check(apic, irq))
1348 continue;
1349 else
1350 add_pin_to_irq(irq, apic, pin);
1352 if (!apic && !IO_APIC_IRQ(irq))
1353 continue;
1355 if (IO_APIC_IRQ(irq)) {
1356 vector = assign_irq_vector(irq);
1357 entry.vector = vector;
1358 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1360 if (!apic && (irq < 16))
1361 disable_8259A_irq(irq);
1363 ioapic_write_entry(apic, pin, entry);
1364 spin_lock_irqsave(&ioapic_lock, flags);
1365 set_native_irq_info(irq, TARGET_CPUS);
1366 spin_unlock_irqrestore(&ioapic_lock, flags);
1370 if (!first_notcon)
1371 apic_printk(APIC_VERBOSE, " not connected.\n");
1375 * Set up the 8259A-master output pin:
1377 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1379 struct IO_APIC_route_entry entry;
1381 memset(&entry,0,sizeof(entry));
1383 disable_8259A_irq(0);
1385 /* mask LVT0 */
1386 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1389 * We use logical delivery to get the timer IRQ
1390 * to the first CPU.
1392 entry.dest_mode = INT_DEST_MODE;
1393 entry.mask = 0; /* unmask IRQ now */
1394 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1395 entry.delivery_mode = INT_DELIVERY_MODE;
1396 entry.polarity = 0;
1397 entry.trigger = 0;
1398 entry.vector = vector;
1401 * The timer IRQ doesn't have to know that behind the
1402 * scene we have a 8259A-master in AEOI mode ...
1404 irq_desc[0].chip = &ioapic_chip;
1405 set_irq_handler(0, handle_edge_irq);
1408 * Add it to the IO-APIC irq-routing table:
1410 ioapic_write_entry(apic, pin, entry);
1412 enable_8259A_irq(0);
1415 static inline void UNEXPECTED_IO_APIC(void)
1419 void __init print_IO_APIC(void)
1421 int apic, i;
1422 union IO_APIC_reg_00 reg_00;
1423 union IO_APIC_reg_01 reg_01;
1424 union IO_APIC_reg_02 reg_02;
1425 union IO_APIC_reg_03 reg_03;
1426 unsigned long flags;
1428 if (apic_verbosity == APIC_QUIET)
1429 return;
1431 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1432 for (i = 0; i < nr_ioapics; i++)
1433 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1434 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1437 * We are a bit conservative about what we expect. We have to
1438 * know about every hardware change ASAP.
1440 printk(KERN_INFO "testing the IO APIC.......................\n");
1442 for (apic = 0; apic < nr_ioapics; apic++) {
1444 spin_lock_irqsave(&ioapic_lock, flags);
1445 reg_00.raw = io_apic_read(apic, 0);
1446 reg_01.raw = io_apic_read(apic, 1);
1447 if (reg_01.bits.version >= 0x10)
1448 reg_02.raw = io_apic_read(apic, 2);
1449 if (reg_01.bits.version >= 0x20)
1450 reg_03.raw = io_apic_read(apic, 3);
1451 spin_unlock_irqrestore(&ioapic_lock, flags);
1453 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1454 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1455 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1456 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1457 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1458 if (reg_00.bits.ID >= get_physical_broadcast())
1459 UNEXPECTED_IO_APIC();
1460 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1461 UNEXPECTED_IO_APIC();
1463 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1464 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1465 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1466 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1467 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1468 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1469 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1470 (reg_01.bits.entries != 0x2E) &&
1471 (reg_01.bits.entries != 0x3F)
1473 UNEXPECTED_IO_APIC();
1475 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1476 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1477 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1478 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1479 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1480 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1481 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
1483 UNEXPECTED_IO_APIC();
1484 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1485 UNEXPECTED_IO_APIC();
1488 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1489 * but the value of reg_02 is read as the previous read register
1490 * value, so ignore it if reg_02 == reg_01.
1492 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1493 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1494 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1495 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1496 UNEXPECTED_IO_APIC();
1500 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1501 * or reg_03, but the value of reg_0[23] is read as the previous read
1502 * register value, so ignore it if reg_03 == reg_0[12].
1504 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1505 reg_03.raw != reg_01.raw) {
1506 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1507 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1508 if (reg_03.bits.__reserved_1)
1509 UNEXPECTED_IO_APIC();
1512 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1514 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1515 " Stat Dest Deli Vect: \n");
1517 for (i = 0; i <= reg_01.bits.entries; i++) {
1518 struct IO_APIC_route_entry entry;
1520 entry = ioapic_read_entry(apic, i);
1522 printk(KERN_DEBUG " %02x %03X %02X ",
1524 entry.dest.logical.logical_dest,
1525 entry.dest.physical.physical_dest
1528 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1529 entry.mask,
1530 entry.trigger,
1531 entry.irr,
1532 entry.polarity,
1533 entry.delivery_status,
1534 entry.dest_mode,
1535 entry.delivery_mode,
1536 entry.vector
1540 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1541 for (i = 0; i < NR_IRQS; i++) {
1542 struct irq_pin_list *entry = irq_2_pin + i;
1543 if (entry->pin < 0)
1544 continue;
1545 printk(KERN_DEBUG "IRQ%d ", i);
1546 for (;;) {
1547 printk("-> %d:%d", entry->apic, entry->pin);
1548 if (!entry->next)
1549 break;
1550 entry = irq_2_pin + entry->next;
1552 printk("\n");
1555 printk(KERN_INFO ".................................... done.\n");
1557 return;
1560 #if 0
1562 static void print_APIC_bitfield (int base)
1564 unsigned int v;
1565 int i, j;
1567 if (apic_verbosity == APIC_QUIET)
1568 return;
1570 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1571 for (i = 0; i < 8; i++) {
1572 v = apic_read(base + i*0x10);
1573 for (j = 0; j < 32; j++) {
1574 if (v & (1<<j))
1575 printk("1");
1576 else
1577 printk("0");
1579 printk("\n");
1583 void /*__init*/ print_local_APIC(void * dummy)
1585 unsigned int v, ver, maxlvt;
1587 if (apic_verbosity == APIC_QUIET)
1588 return;
1590 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1591 smp_processor_id(), hard_smp_processor_id());
1592 v = apic_read(APIC_ID);
1593 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
1594 v = apic_read(APIC_LVR);
1595 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1596 ver = GET_APIC_VERSION(v);
1597 maxlvt = get_maxlvt();
1599 v = apic_read(APIC_TASKPRI);
1600 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1602 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1603 v = apic_read(APIC_ARBPRI);
1604 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1605 v & APIC_ARBPRI_MASK);
1606 v = apic_read(APIC_PROCPRI);
1607 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1610 v = apic_read(APIC_EOI);
1611 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1612 v = apic_read(APIC_RRR);
1613 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1614 v = apic_read(APIC_LDR);
1615 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1616 v = apic_read(APIC_DFR);
1617 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1618 v = apic_read(APIC_SPIV);
1619 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1621 printk(KERN_DEBUG "... APIC ISR field:\n");
1622 print_APIC_bitfield(APIC_ISR);
1623 printk(KERN_DEBUG "... APIC TMR field:\n");
1624 print_APIC_bitfield(APIC_TMR);
1625 printk(KERN_DEBUG "... APIC IRR field:\n");
1626 print_APIC_bitfield(APIC_IRR);
1628 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1629 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1630 apic_write(APIC_ESR, 0);
1631 v = apic_read(APIC_ESR);
1632 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1635 v = apic_read(APIC_ICR);
1636 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1637 v = apic_read(APIC_ICR2);
1638 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1640 v = apic_read(APIC_LVTT);
1641 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1643 if (maxlvt > 3) { /* PC is LVT#4. */
1644 v = apic_read(APIC_LVTPC);
1645 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1647 v = apic_read(APIC_LVT0);
1648 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1649 v = apic_read(APIC_LVT1);
1650 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1652 if (maxlvt > 2) { /* ERR is LVT#3. */
1653 v = apic_read(APIC_LVTERR);
1654 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1657 v = apic_read(APIC_TMICT);
1658 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1659 v = apic_read(APIC_TMCCT);
1660 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1661 v = apic_read(APIC_TDCR);
1662 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1663 printk("\n");
1666 void print_all_local_APICs (void)
1668 on_each_cpu(print_local_APIC, NULL, 1, 1);
1671 void /*__init*/ print_PIC(void)
1673 unsigned int v;
1674 unsigned long flags;
1676 if (apic_verbosity == APIC_QUIET)
1677 return;
1679 printk(KERN_DEBUG "\nprinting PIC contents\n");
1681 spin_lock_irqsave(&i8259A_lock, flags);
1683 v = inb(0xa1) << 8 | inb(0x21);
1684 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1686 v = inb(0xa0) << 8 | inb(0x20);
1687 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1689 outb(0x0b,0xa0);
1690 outb(0x0b,0x20);
1691 v = inb(0xa0) << 8 | inb(0x20);
1692 outb(0x0a,0xa0);
1693 outb(0x0a,0x20);
1695 spin_unlock_irqrestore(&i8259A_lock, flags);
1697 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1699 v = inb(0x4d1) << 8 | inb(0x4d0);
1700 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1703 #endif /* 0 */
1705 static void __init enable_IO_APIC(void)
1707 union IO_APIC_reg_01 reg_01;
1708 int i8259_apic, i8259_pin;
1709 int i, apic;
1710 unsigned long flags;
1712 for (i = 0; i < PIN_MAP_SIZE; i++) {
1713 irq_2_pin[i].pin = -1;
1714 irq_2_pin[i].next = 0;
1716 if (!pirqs_enabled)
1717 for (i = 0; i < MAX_PIRQS; i++)
1718 pirq_entries[i] = -1;
1721 * The number of IO-APIC IRQ registers (== #pins):
1723 for (apic = 0; apic < nr_ioapics; apic++) {
1724 spin_lock_irqsave(&ioapic_lock, flags);
1725 reg_01.raw = io_apic_read(apic, 1);
1726 spin_unlock_irqrestore(&ioapic_lock, flags);
1727 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1729 for(apic = 0; apic < nr_ioapics; apic++) {
1730 int pin;
1731 /* See if any of the pins is in ExtINT mode */
1732 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1733 struct IO_APIC_route_entry entry;
1734 entry = ioapic_read_entry(apic, pin);
1737 /* If the interrupt line is enabled and in ExtInt mode
1738 * I have found the pin where the i8259 is connected.
1740 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1741 ioapic_i8259.apic = apic;
1742 ioapic_i8259.pin = pin;
1743 goto found_i8259;
1747 found_i8259:
1748 /* Look to see what if the MP table has reported the ExtINT */
1749 /* If we could not find the appropriate pin by looking at the ioapic
1750 * the i8259 probably is not connected the ioapic but give the
1751 * mptable a chance anyway.
1753 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1754 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1755 /* Trust the MP table if nothing is setup in the hardware */
1756 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1757 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1758 ioapic_i8259.pin = i8259_pin;
1759 ioapic_i8259.apic = i8259_apic;
1761 /* Complain if the MP table and the hardware disagree */
1762 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1763 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1765 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1769 * Do not trust the IO-APIC being empty at bootup
1771 clear_IO_APIC();
1775 * Not an __init, needed by the reboot code
1777 void disable_IO_APIC(void)
1780 * Clear the IO-APIC before rebooting:
1782 clear_IO_APIC();
1785 * If the i8259 is routed through an IOAPIC
1786 * Put that IOAPIC in virtual wire mode
1787 * so legacy interrupts can be delivered.
1789 if (ioapic_i8259.pin != -1) {
1790 struct IO_APIC_route_entry entry;
1792 memset(&entry, 0, sizeof(entry));
1793 entry.mask = 0; /* Enabled */
1794 entry.trigger = 0; /* Edge */
1795 entry.irr = 0;
1796 entry.polarity = 0; /* High */
1797 entry.delivery_status = 0;
1798 entry.dest_mode = 0; /* Physical */
1799 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1800 entry.vector = 0;
1801 entry.dest.physical.physical_dest =
1802 GET_APIC_ID(apic_read(APIC_ID));
1805 * Add it to the IO-APIC irq-routing table:
1807 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1809 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1813 * function to set the IO-APIC physical IDs based on the
1814 * values stored in the MPC table.
1816 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1819 #ifndef CONFIG_X86_NUMAQ
1820 static void __init setup_ioapic_ids_from_mpc(void)
1822 union IO_APIC_reg_00 reg_00;
1823 physid_mask_t phys_id_present_map;
1824 int apic;
1825 int i;
1826 unsigned char old_id;
1827 unsigned long flags;
1830 * Don't check I/O APIC IDs for xAPIC systems. They have
1831 * no meaning without the serial APIC bus.
1833 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1834 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1835 return;
1837 * This is broken; anything with a real cpu count has to
1838 * circumvent this idiocy regardless.
1840 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1843 * Set the IOAPIC ID to the value stored in the MPC table.
1845 for (apic = 0; apic < nr_ioapics; apic++) {
1847 /* Read the register 0 value */
1848 spin_lock_irqsave(&ioapic_lock, flags);
1849 reg_00.raw = io_apic_read(apic, 0);
1850 spin_unlock_irqrestore(&ioapic_lock, flags);
1852 old_id = mp_ioapics[apic].mpc_apicid;
1854 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1855 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1856 apic, mp_ioapics[apic].mpc_apicid);
1857 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1858 reg_00.bits.ID);
1859 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1863 * Sanity check, is the ID really free? Every APIC in a
1864 * system must have a unique ID or we get lots of nice
1865 * 'stuck on smp_invalidate_needed IPI wait' messages.
1867 if (check_apicid_used(phys_id_present_map,
1868 mp_ioapics[apic].mpc_apicid)) {
1869 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1870 apic, mp_ioapics[apic].mpc_apicid);
1871 for (i = 0; i < get_physical_broadcast(); i++)
1872 if (!physid_isset(i, phys_id_present_map))
1873 break;
1874 if (i >= get_physical_broadcast())
1875 panic("Max APIC ID exceeded!\n");
1876 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1878 physid_set(i, phys_id_present_map);
1879 mp_ioapics[apic].mpc_apicid = i;
1880 } else {
1881 physid_mask_t tmp;
1882 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1883 apic_printk(APIC_VERBOSE, "Setting %d in the "
1884 "phys_id_present_map\n",
1885 mp_ioapics[apic].mpc_apicid);
1886 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1891 * We need to adjust the IRQ routing table
1892 * if the ID changed.
1894 if (old_id != mp_ioapics[apic].mpc_apicid)
1895 for (i = 0; i < mp_irq_entries; i++)
1896 if (mp_irqs[i].mpc_dstapic == old_id)
1897 mp_irqs[i].mpc_dstapic
1898 = mp_ioapics[apic].mpc_apicid;
1901 * Read the right value from the MPC table and
1902 * write it into the ID register.
1904 apic_printk(APIC_VERBOSE, KERN_INFO
1905 "...changing IO-APIC physical APIC ID to %d ...",
1906 mp_ioapics[apic].mpc_apicid);
1908 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1909 spin_lock_irqsave(&ioapic_lock, flags);
1910 io_apic_write(apic, 0, reg_00.raw);
1911 spin_unlock_irqrestore(&ioapic_lock, flags);
1914 * Sanity check
1916 spin_lock_irqsave(&ioapic_lock, flags);
1917 reg_00.raw = io_apic_read(apic, 0);
1918 spin_unlock_irqrestore(&ioapic_lock, flags);
1919 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1920 printk("could not set ID!\n");
1921 else
1922 apic_printk(APIC_VERBOSE, " ok.\n");
1925 #else
1926 static void __init setup_ioapic_ids_from_mpc(void) { }
1927 #endif
1930 * There is a nasty bug in some older SMP boards, their mptable lies
1931 * about the timer IRQ. We do the following to work around the situation:
1933 * - timer IRQ defaults to IO-APIC IRQ
1934 * - if this function detects that timer IRQs are defunct, then we fall
1935 * back to ISA timer IRQs
1937 static int __init timer_irq_works(void)
1939 unsigned long t1 = jiffies;
1941 local_irq_enable();
1942 /* Let ten ticks pass... */
1943 mdelay((10 * 1000) / HZ);
1946 * Expect a few ticks at least, to be sure some possible
1947 * glue logic does not lock up after one or two first
1948 * ticks in a non-ExtINT mode. Also the local APIC
1949 * might have cached one ExtINT interrupt. Finally, at
1950 * least one tick may be lost due to delays.
1952 if (jiffies - t1 > 4)
1953 return 1;
1955 return 0;
1959 * In the SMP+IOAPIC case it might happen that there are an unspecified
1960 * number of pending IRQ events unhandled. These cases are very rare,
1961 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1962 * better to do it this way as thus we do not have to be aware of
1963 * 'pending' interrupts in the IRQ path, except at this point.
1966 * Edge triggered needs to resend any interrupt
1967 * that was delayed but this is now handled in the device
1968 * independent code.
1972 * Startup quirk:
1974 * Starting up a edge-triggered IO-APIC interrupt is
1975 * nasty - we need to make sure that we get the edge.
1976 * If it is already asserted for some reason, we need
1977 * return 1 to indicate that is was pending.
1979 * This is not complete - we should be able to fake
1980 * an edge even if it isn't on the 8259A...
1982 * (We do this for level-triggered IRQs too - it cannot hurt.)
1984 static unsigned int startup_ioapic_irq(unsigned int irq)
1986 int was_pending = 0;
1987 unsigned long flags;
1989 spin_lock_irqsave(&ioapic_lock, flags);
1990 if (irq < 16) {
1991 disable_8259A_irq(irq);
1992 if (i8259A_irq_pending(irq))
1993 was_pending = 1;
1995 __unmask_IO_APIC_irq(irq);
1996 spin_unlock_irqrestore(&ioapic_lock, flags);
1998 return was_pending;
2001 static void ack_ioapic_irq(unsigned int irq)
2003 move_native_irq(irq);
2004 ack_APIC_irq();
2007 static void ack_ioapic_quirk_irq(unsigned int irq)
2009 unsigned long v;
2010 int i;
2012 move_native_irq(irq);
2014 * It appears there is an erratum which affects at least version 0x11
2015 * of I/O APIC (that's the 82093AA and cores integrated into various
2016 * chipsets). Under certain conditions a level-triggered interrupt is
2017 * erroneously delivered as edge-triggered one but the respective IRR
2018 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2019 * message but it will never arrive and further interrupts are blocked
2020 * from the source. The exact reason is so far unknown, but the
2021 * phenomenon was observed when two consecutive interrupt requests
2022 * from a given source get delivered to the same CPU and the source is
2023 * temporarily disabled in between.
2025 * A workaround is to simulate an EOI message manually. We achieve it
2026 * by setting the trigger mode to edge and then to level when the edge
2027 * trigger mode gets detected in the TMR of a local APIC for a
2028 * level-triggered interrupt. We mask the source for the time of the
2029 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2030 * The idea is from Manfred Spraul. --macro
2032 i = irq_vector[irq];
2034 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2036 ack_APIC_irq();
2038 if (!(v & (1 << (i & 0x1f)))) {
2039 atomic_inc(&irq_mis_count);
2040 spin_lock(&ioapic_lock);
2041 __mask_and_edge_IO_APIC_irq(irq);
2042 __unmask_and_level_IO_APIC_irq(irq);
2043 spin_unlock(&ioapic_lock);
2047 static int ioapic_retrigger_irq(unsigned int irq)
2049 send_IPI_self(irq_vector[irq]);
2051 return 1;
2054 static struct irq_chip ioapic_chip __read_mostly = {
2055 .name = "IO-APIC",
2056 .startup = startup_ioapic_irq,
2057 .mask = mask_IO_APIC_irq,
2058 .unmask = unmask_IO_APIC_irq,
2059 .ack = ack_ioapic_irq,
2060 .eoi = ack_ioapic_quirk_irq,
2061 #ifdef CONFIG_SMP
2062 .set_affinity = set_ioapic_affinity_irq,
2063 #endif
2064 .retrigger = ioapic_retrigger_irq,
2068 static inline void init_IO_APIC_traps(void)
2070 int irq;
2073 * NOTE! The local APIC isn't very good at handling
2074 * multiple interrupts at the same interrupt level.
2075 * As the interrupt level is determined by taking the
2076 * vector number and shifting that right by 4, we
2077 * want to spread these out a bit so that they don't
2078 * all fall in the same interrupt level.
2080 * Also, we've got to be careful not to trash gate
2081 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2083 for (irq = 0; irq < NR_IRQS ; irq++) {
2084 int tmp = irq;
2085 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2087 * Hmm.. We don't have an entry for this,
2088 * so default to an old-fashioned 8259
2089 * interrupt if we can..
2091 if (irq < 16)
2092 make_8259A_irq(irq);
2093 else
2094 /* Strange. Oh, well.. */
2095 irq_desc[irq].chip = &no_irq_chip;
2101 * The local APIC irq-chip implementation:
2104 static void ack_apic(unsigned int irq)
2106 ack_APIC_irq();
2109 static void mask_lapic_irq (unsigned int irq)
2111 unsigned long v;
2113 v = apic_read(APIC_LVT0);
2114 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2117 static void unmask_lapic_irq (unsigned int irq)
2119 unsigned long v;
2121 v = apic_read(APIC_LVT0);
2122 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2125 static struct irq_chip lapic_chip __read_mostly = {
2126 .name = "local-APIC-edge",
2127 .mask = mask_lapic_irq,
2128 .unmask = unmask_lapic_irq,
2129 .eoi = ack_apic,
2132 static void setup_nmi (void)
2135 * Dirty trick to enable the NMI watchdog ...
2136 * We put the 8259A master into AEOI mode and
2137 * unmask on all local APICs LVT0 as NMI.
2139 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2140 * is from Maciej W. Rozycki - so we do not have to EOI from
2141 * the NMI handler or the timer interrupt.
2143 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2145 on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2147 apic_printk(APIC_VERBOSE, " done.\n");
2151 * This looks a bit hackish but it's about the only one way of sending
2152 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2153 * not support the ExtINT mode, unfortunately. We need to send these
2154 * cycles as some i82489DX-based boards have glue logic that keeps the
2155 * 8259A interrupt line asserted until INTA. --macro
2157 static inline void unlock_ExtINT_logic(void)
2159 int apic, pin, i;
2160 struct IO_APIC_route_entry entry0, entry1;
2161 unsigned char save_control, save_freq_select;
2163 pin = find_isa_irq_pin(8, mp_INT);
2164 apic = find_isa_irq_apic(8, mp_INT);
2165 if (pin == -1)
2166 return;
2168 entry0 = ioapic_read_entry(apic, pin);
2169 clear_IO_APIC_pin(apic, pin);
2171 memset(&entry1, 0, sizeof(entry1));
2173 entry1.dest_mode = 0; /* physical delivery */
2174 entry1.mask = 0; /* unmask IRQ now */
2175 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2176 entry1.delivery_mode = dest_ExtINT;
2177 entry1.polarity = entry0.polarity;
2178 entry1.trigger = 0;
2179 entry1.vector = 0;
2181 ioapic_write_entry(apic, pin, entry1);
2183 save_control = CMOS_READ(RTC_CONTROL);
2184 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2185 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2186 RTC_FREQ_SELECT);
2187 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2189 i = 100;
2190 while (i-- > 0) {
2191 mdelay(10);
2192 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2193 i -= 10;
2196 CMOS_WRITE(save_control, RTC_CONTROL);
2197 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2198 clear_IO_APIC_pin(apic, pin);
2200 ioapic_write_entry(apic, pin, entry0);
2203 int timer_uses_ioapic_pin_0;
2206 * This code may look a bit paranoid, but it's supposed to cooperate with
2207 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2208 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2209 * fanatically on his truly buggy board.
2211 static inline void check_timer(void)
2213 int apic1, pin1, apic2, pin2;
2214 int vector;
2217 * get/set the timer IRQ vector:
2219 disable_8259A_irq(0);
2220 vector = assign_irq_vector(0);
2221 set_intr_gate(vector, interrupt[0]);
2224 * Subtle, code in do_timer_interrupt() expects an AEOI
2225 * mode for the 8259A whenever interrupts are routed
2226 * through I/O APICs. Also IRQ0 has to be enabled in
2227 * the 8259A which implies the virtual wire has to be
2228 * disabled in the local APIC.
2230 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2231 init_8259A(1);
2232 timer_ack = 1;
2233 if (timer_over_8254 > 0)
2234 enable_8259A_irq(0);
2236 pin1 = find_isa_irq_pin(0, mp_INT);
2237 apic1 = find_isa_irq_apic(0, mp_INT);
2238 pin2 = ioapic_i8259.pin;
2239 apic2 = ioapic_i8259.apic;
2241 if (pin1 == 0)
2242 timer_uses_ioapic_pin_0 = 1;
2244 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2245 vector, apic1, pin1, apic2, pin2);
2247 if (pin1 != -1) {
2249 * Ok, does IRQ0 through the IOAPIC work?
2251 unmask_IO_APIC_irq(0);
2252 if (timer_irq_works()) {
2253 if (nmi_watchdog == NMI_IO_APIC) {
2254 disable_8259A_irq(0);
2255 setup_nmi();
2256 enable_8259A_irq(0);
2258 if (disable_timer_pin_1 > 0)
2259 clear_IO_APIC_pin(0, pin1);
2260 return;
2262 clear_IO_APIC_pin(apic1, pin1);
2263 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2264 "IO-APIC\n");
2267 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2268 if (pin2 != -1) {
2269 printk("\n..... (found pin %d) ...", pin2);
2271 * legacy devices should be connected to IO APIC #0
2273 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2274 if (timer_irq_works()) {
2275 printk("works.\n");
2276 if (pin1 != -1)
2277 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2278 else
2279 add_pin_to_irq(0, apic2, pin2);
2280 if (nmi_watchdog == NMI_IO_APIC) {
2281 setup_nmi();
2283 return;
2286 * Cleanup, just in case ...
2288 clear_IO_APIC_pin(apic2, pin2);
2290 printk(" failed.\n");
2292 if (nmi_watchdog == NMI_IO_APIC) {
2293 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2294 nmi_watchdog = 0;
2297 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2299 disable_8259A_irq(0);
2300 set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2301 "fasteio");
2302 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2303 enable_8259A_irq(0);
2305 if (timer_irq_works()) {
2306 printk(" works.\n");
2307 return;
2309 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2310 printk(" failed.\n");
2312 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2314 timer_ack = 0;
2315 init_8259A(0);
2316 make_8259A_irq(0);
2317 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2319 unlock_ExtINT_logic();
2321 if (timer_irq_works()) {
2322 printk(" works.\n");
2323 return;
2325 printk(" failed :(.\n");
2326 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2327 "report. Then try booting with the 'noapic' option");
2332 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2333 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2334 * Linux doesn't really care, as it's not actually used
2335 * for any interrupt handling anyway.
2337 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2339 void __init setup_IO_APIC(void)
2341 enable_IO_APIC();
2343 if (acpi_ioapic)
2344 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
2345 else
2346 io_apic_irqs = ~PIC_IRQS;
2348 printk("ENABLING IO-APIC IRQs\n");
2351 * Set up IO-APIC IRQ routing.
2353 if (!acpi_ioapic)
2354 setup_ioapic_ids_from_mpc();
2355 sync_Arb_IDs();
2356 setup_IO_APIC_irqs();
2357 init_IO_APIC_traps();
2358 check_timer();
2359 if (!acpi_ioapic)
2360 print_IO_APIC();
2363 static int __init setup_disable_8254_timer(char *s)
2365 timer_over_8254 = -1;
2366 return 1;
2368 static int __init setup_enable_8254_timer(char *s)
2370 timer_over_8254 = 2;
2371 return 1;
2374 __setup("disable_8254_timer", setup_disable_8254_timer);
2375 __setup("enable_8254_timer", setup_enable_8254_timer);
2378 * Called after all the initialization is done. If we didnt find any
2379 * APIC bugs then we can allow the modify fast path
2382 static int __init io_apic_bug_finalize(void)
2384 if(sis_apic_bug == -1)
2385 sis_apic_bug = 0;
2386 return 0;
2389 late_initcall(io_apic_bug_finalize);
2391 struct sysfs_ioapic_data {
2392 struct sys_device dev;
2393 struct IO_APIC_route_entry entry[0];
2395 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2397 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2399 struct IO_APIC_route_entry *entry;
2400 struct sysfs_ioapic_data *data;
2401 int i;
2403 data = container_of(dev, struct sysfs_ioapic_data, dev);
2404 entry = data->entry;
2405 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2406 entry[i] = ioapic_read_entry(dev->id, i);
2408 return 0;
2411 static int ioapic_resume(struct sys_device *dev)
2413 struct IO_APIC_route_entry *entry;
2414 struct sysfs_ioapic_data *data;
2415 unsigned long flags;
2416 union IO_APIC_reg_00 reg_00;
2417 int i;
2419 data = container_of(dev, struct sysfs_ioapic_data, dev);
2420 entry = data->entry;
2422 spin_lock_irqsave(&ioapic_lock, flags);
2423 reg_00.raw = io_apic_read(dev->id, 0);
2424 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2425 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2426 io_apic_write(dev->id, 0, reg_00.raw);
2428 spin_unlock_irqrestore(&ioapic_lock, flags);
2429 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2430 ioapic_write_entry(dev->id, i, entry[i]);
2432 return 0;
2435 static struct sysdev_class ioapic_sysdev_class = {
2436 set_kset_name("ioapic"),
2437 .suspend = ioapic_suspend,
2438 .resume = ioapic_resume,
2441 static int __init ioapic_init_sysfs(void)
2443 struct sys_device * dev;
2444 int i, size, error = 0;
2446 error = sysdev_class_register(&ioapic_sysdev_class);
2447 if (error)
2448 return error;
2450 for (i = 0; i < nr_ioapics; i++ ) {
2451 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2452 * sizeof(struct IO_APIC_route_entry);
2453 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2454 if (!mp_ioapic_data[i]) {
2455 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2456 continue;
2458 memset(mp_ioapic_data[i], 0, size);
2459 dev = &mp_ioapic_data[i]->dev;
2460 dev->id = i;
2461 dev->cls = &ioapic_sysdev_class;
2462 error = sysdev_register(dev);
2463 if (error) {
2464 kfree(mp_ioapic_data[i]);
2465 mp_ioapic_data[i] = NULL;
2466 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2467 continue;
2471 return 0;
2474 device_initcall(ioapic_init_sysfs);
2477 * Dynamic irq allocate and deallocation
2479 int create_irq(void)
2481 /* Allocate an unused irq */
2482 int irq, new, vector;
2483 unsigned long flags;
2485 irq = -ENOSPC;
2486 spin_lock_irqsave(&vector_lock, flags);
2487 for (new = (NR_IRQS - 1); new >= 0; new--) {
2488 if (platform_legacy_irq(new))
2489 continue;
2490 if (irq_vector[new] != 0)
2491 continue;
2492 vector = __assign_irq_vector(new);
2493 if (likely(vector > 0))
2494 irq = new;
2495 break;
2497 spin_unlock_irqrestore(&vector_lock, flags);
2499 if (irq >= 0) {
2500 set_intr_gate(vector, interrupt[irq]);
2501 dynamic_irq_init(irq);
2503 return irq;
2506 void destroy_irq(unsigned int irq)
2508 unsigned long flags;
2510 dynamic_irq_cleanup(irq);
2512 spin_lock_irqsave(&vector_lock, flags);
2513 irq_vector[irq] = 0;
2514 spin_unlock_irqrestore(&vector_lock, flags);
2518 * MSI mesage composition
2520 #ifdef CONFIG_PCI_MSI
2521 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2523 int vector;
2524 unsigned dest;
2526 vector = assign_irq_vector(irq);
2527 if (vector >= 0) {
2528 dest = cpu_mask_to_apicid(TARGET_CPUS);
2530 msg->address_hi = MSI_ADDR_BASE_HI;
2531 msg->address_lo =
2532 MSI_ADDR_BASE_LO |
2533 ((INT_DEST_MODE == 0) ?
2534 MSI_ADDR_DEST_MODE_PHYSICAL:
2535 MSI_ADDR_DEST_MODE_LOGICAL) |
2536 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2537 MSI_ADDR_REDIRECTION_CPU:
2538 MSI_ADDR_REDIRECTION_LOWPRI) |
2539 MSI_ADDR_DEST_ID(dest);
2541 msg->data =
2542 MSI_DATA_TRIGGER_EDGE |
2543 MSI_DATA_LEVEL_ASSERT |
2544 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2545 MSI_DATA_DELIVERY_FIXED:
2546 MSI_DATA_DELIVERY_LOWPRI) |
2547 MSI_DATA_VECTOR(vector);
2549 return vector;
2552 #ifdef CONFIG_SMP
2553 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2555 struct msi_msg msg;
2556 unsigned int dest;
2557 cpumask_t tmp;
2558 int vector;
2560 cpus_and(tmp, mask, cpu_online_map);
2561 if (cpus_empty(tmp))
2562 tmp = TARGET_CPUS;
2564 vector = assign_irq_vector(irq);
2565 if (vector < 0)
2566 return;
2568 dest = cpu_mask_to_apicid(mask);
2570 read_msi_msg(irq, &msg);
2572 msg.data &= ~MSI_DATA_VECTOR_MASK;
2573 msg.data |= MSI_DATA_VECTOR(vector);
2574 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2575 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2577 write_msi_msg(irq, &msg);
2578 set_native_irq_info(irq, mask);
2580 #endif /* CONFIG_SMP */
2583 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2584 * which implement the MSI or MSI-X Capability Structure.
2586 static struct irq_chip msi_chip = {
2587 .name = "PCI-MSI",
2588 .unmask = unmask_msi_irq,
2589 .mask = mask_msi_irq,
2590 .ack = ack_ioapic_irq,
2591 #ifdef CONFIG_SMP
2592 .set_affinity = set_msi_irq_affinity,
2593 #endif
2594 .retrigger = ioapic_retrigger_irq,
2597 int arch_setup_msi_irq(unsigned int irq, struct pci_dev *dev)
2599 struct msi_msg msg;
2600 int ret;
2601 ret = msi_compose_msg(dev, irq, &msg);
2602 if (ret < 0)
2603 return ret;
2605 write_msi_msg(irq, &msg);
2607 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2608 "edge");
2610 return 0;
2613 void arch_teardown_msi_irq(unsigned int irq)
2615 return;
2618 #endif /* CONFIG_PCI_MSI */
2621 * Hypertransport interrupt support
2623 #ifdef CONFIG_HT_IRQ
2625 #ifdef CONFIG_SMP
2627 static void target_ht_irq(unsigned int irq, unsigned int dest)
2629 struct ht_irq_msg msg;
2630 fetch_ht_irq_msg(irq, &msg);
2632 msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2633 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2635 msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2636 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2638 write_ht_irq_msg(irq, &msg);
2641 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2643 unsigned int dest;
2644 cpumask_t tmp;
2646 cpus_and(tmp, mask, cpu_online_map);
2647 if (cpus_empty(tmp))
2648 tmp = TARGET_CPUS;
2650 cpus_and(mask, tmp, CPU_MASK_ALL);
2652 dest = cpu_mask_to_apicid(mask);
2654 target_ht_irq(irq, dest);
2655 set_native_irq_info(irq, mask);
2657 #endif
2659 static struct irq_chip ht_irq_chip = {
2660 .name = "PCI-HT",
2661 .mask = mask_ht_irq,
2662 .unmask = unmask_ht_irq,
2663 .ack = ack_ioapic_irq,
2664 #ifdef CONFIG_SMP
2665 .set_affinity = set_ht_irq_affinity,
2666 #endif
2667 .retrigger = ioapic_retrigger_irq,
2670 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2672 int vector;
2674 vector = assign_irq_vector(irq);
2675 if (vector >= 0) {
2676 struct ht_irq_msg msg;
2677 unsigned dest;
2678 cpumask_t tmp;
2680 cpus_clear(tmp);
2681 cpu_set(vector >> 8, tmp);
2682 dest = cpu_mask_to_apicid(tmp);
2684 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2686 msg.address_lo =
2687 HT_IRQ_LOW_BASE |
2688 HT_IRQ_LOW_DEST_ID(dest) |
2689 HT_IRQ_LOW_VECTOR(vector) |
2690 ((INT_DEST_MODE == 0) ?
2691 HT_IRQ_LOW_DM_PHYSICAL :
2692 HT_IRQ_LOW_DM_LOGICAL) |
2693 HT_IRQ_LOW_RQEOI_EDGE |
2694 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2695 HT_IRQ_LOW_MT_FIXED :
2696 HT_IRQ_LOW_MT_ARBITRATED) |
2697 HT_IRQ_LOW_IRQ_MASKED;
2699 write_ht_irq_msg(irq, &msg);
2701 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2702 handle_edge_irq, "edge");
2704 return vector;
2706 #endif /* CONFIG_HT_IRQ */
2708 /* --------------------------------------------------------------------------
2709 ACPI-based IOAPIC Configuration
2710 -------------------------------------------------------------------------- */
2712 #ifdef CONFIG_ACPI
2714 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2716 union IO_APIC_reg_00 reg_00;
2717 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2718 physid_mask_t tmp;
2719 unsigned long flags;
2720 int i = 0;
2723 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2724 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2725 * supports up to 16 on one shared APIC bus.
2727 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2728 * advantage of new APIC bus architecture.
2731 if (physids_empty(apic_id_map))
2732 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2734 spin_lock_irqsave(&ioapic_lock, flags);
2735 reg_00.raw = io_apic_read(ioapic, 0);
2736 spin_unlock_irqrestore(&ioapic_lock, flags);
2738 if (apic_id >= get_physical_broadcast()) {
2739 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2740 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2741 apic_id = reg_00.bits.ID;
2745 * Every APIC in a system must have a unique ID or we get lots of nice
2746 * 'stuck on smp_invalidate_needed IPI wait' messages.
2748 if (check_apicid_used(apic_id_map, apic_id)) {
2750 for (i = 0; i < get_physical_broadcast(); i++) {
2751 if (!check_apicid_used(apic_id_map, i))
2752 break;
2755 if (i == get_physical_broadcast())
2756 panic("Max apic_id exceeded!\n");
2758 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2759 "trying %d\n", ioapic, apic_id, i);
2761 apic_id = i;
2764 tmp = apicid_to_cpu_present(apic_id);
2765 physids_or(apic_id_map, apic_id_map, tmp);
2767 if (reg_00.bits.ID != apic_id) {
2768 reg_00.bits.ID = apic_id;
2770 spin_lock_irqsave(&ioapic_lock, flags);
2771 io_apic_write(ioapic, 0, reg_00.raw);
2772 reg_00.raw = io_apic_read(ioapic, 0);
2773 spin_unlock_irqrestore(&ioapic_lock, flags);
2775 /* Sanity check */
2776 if (reg_00.bits.ID != apic_id) {
2777 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2778 return -1;
2782 apic_printk(APIC_VERBOSE, KERN_INFO
2783 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2785 return apic_id;
2789 int __init io_apic_get_version (int ioapic)
2791 union IO_APIC_reg_01 reg_01;
2792 unsigned long flags;
2794 spin_lock_irqsave(&ioapic_lock, flags);
2795 reg_01.raw = io_apic_read(ioapic, 1);
2796 spin_unlock_irqrestore(&ioapic_lock, flags);
2798 return reg_01.bits.version;
2802 int __init io_apic_get_redir_entries (int ioapic)
2804 union IO_APIC_reg_01 reg_01;
2805 unsigned long flags;
2807 spin_lock_irqsave(&ioapic_lock, flags);
2808 reg_01.raw = io_apic_read(ioapic, 1);
2809 spin_unlock_irqrestore(&ioapic_lock, flags);
2811 return reg_01.bits.entries;
2815 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2817 struct IO_APIC_route_entry entry;
2818 unsigned long flags;
2820 if (!IO_APIC_IRQ(irq)) {
2821 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2822 ioapic);
2823 return -EINVAL;
2827 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2828 * Note that we mask (disable) IRQs now -- these get enabled when the
2829 * corresponding device driver registers for this IRQ.
2832 memset(&entry,0,sizeof(entry));
2834 entry.delivery_mode = INT_DELIVERY_MODE;
2835 entry.dest_mode = INT_DEST_MODE;
2836 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2837 entry.trigger = edge_level;
2838 entry.polarity = active_high_low;
2839 entry.mask = 1;
2842 * IRQs < 16 are already in the irq_2_pin[] map
2844 if (irq >= 16)
2845 add_pin_to_irq(irq, ioapic, pin);
2847 entry.vector = assign_irq_vector(irq);
2849 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2850 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2851 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2852 edge_level, active_high_low);
2854 ioapic_register_intr(irq, entry.vector, edge_level);
2856 if (!ioapic && (irq < 16))
2857 disable_8259A_irq(irq);
2859 ioapic_write_entry(ioapic, pin, entry);
2860 spin_lock_irqsave(&ioapic_lock, flags);
2861 set_native_irq_info(irq, TARGET_CPUS);
2862 spin_unlock_irqrestore(&ioapic_lock, flags);
2864 return 0;
2867 #endif /* CONFIG_ACPI */
2869 static int __init parse_disable_timer_pin_1(char *arg)
2871 disable_timer_pin_1 = 1;
2872 return 0;
2874 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2876 static int __init parse_enable_timer_pin_1(char *arg)
2878 disable_timer_pin_1 = -1;
2879 return 0;
2881 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2883 static int __init parse_noapic(char *arg)
2885 /* disable IO-APIC */
2886 disable_ioapic_setup();
2887 return 0;
2889 early_param("noapic", parse_noapic);