?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
sync hh.org
[hh.org.git] / arch / mips / tx4938 / toshiba_rbtx4938 / setup.c
blob66163ba452c809b31a25338271a1bbed15cd4f30
1 /*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/setup.c
3 *
4 * Setup pointers to hardware-dependent routines.
5 * Copyright (C) 2000-2001 Toshiba Corporation
6 *
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/ioport.h>
17 #include <linux/proc_fs.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/console.h>
21 #include <linux/pci.h>
22 #include <linux/pm.h>
23
24 #include <asm/wbflush.h>
25 #include <asm/reboot.h>
26 #include <asm/irq.h>
27 #include <asm/time.h>
28 #include <asm/uaccess.h>
29 #include <asm/io.h>
30 #include <asm/bootinfo.h>
31 #include <asm/tx4938/rbtx4938.h>
32 #ifdef CONFIG_SERIAL_TXX9
33 #include <linux/tty.h>
34 #include <linux/serial.h>
35 #include <linux/serial_core.h>
36 #endif
37
38 extern void rbtx4938_time_init(void) __init;
39 extern char * __init prom_getcmdline(void);
40 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
41
42 /* These functions are used for rebooting or halting the machine*/
43 extern void rbtx4938_machine_restart(char *command);
44 extern void rbtx4938_machine_halt(void);
45 extern void rbtx4938_machine_power_off(void);
46
47 /* clocks */
48 unsigned int txx9_master_clock;
49 unsigned int txx9_cpu_clock;
50 unsigned int txx9_gbus_clock;
51
52 unsigned long rbtx4938_ce_base[8];
53 unsigned long rbtx4938_ce_size[8];
54 int txboard_pci66_mode;
55 static int tx4938_pcic_trdyto; /* default: disabled */
56 static int tx4938_pcic_retryto; /* default: disabled */
57 static int tx4938_ccfg_toeon = 1;
58
59 struct tx4938_pcic_reg *pcicptrs[4] = {
60 tx4938_pcicptr /* default setting for TX4938 */
61 };
62
63 static struct {
64 unsigned long base;
65 unsigned long size;
66 } phys_regions[16] __initdata;
67 static int num_phys_regions __initdata;
68
69 #define PHYS_REGION_MINSIZE 0x10000
70
71 void rbtx4938_machine_halt(void)
72 {
73 printk(KERN_NOTICE "System Halted\n");
74 local_irq_disable();
75
76 while (1)
77 __asm__(".set\tmips3\n\t"
78 "wait\n\t"
79 ".set\tmips0");
80 }
81
82 void rbtx4938_machine_power_off(void)
83 {
84 rbtx4938_machine_halt();
85 /* no return */
86 }
87
88 void rbtx4938_machine_restart(char *command)
89 {
90 local_irq_disable();
91
92 printk("Rebooting...");
93 *rbtx4938_softresetlock_ptr = 1;
94 *rbtx4938_sfvol_ptr = 1;
95 *rbtx4938_softreset_ptr = 1;
96 wbflush();
97
98 while(1);
99 }
100
101 void __init
102 txboard_add_phys_region(unsigned long base, unsigned long size)
103 {
104 if (num_phys_regions >= ARRAY_SIZE(phys_regions)) {
105 printk("phys_region overflow\n");
106 return;
107 }
108 phys_regions[num_phys_regions].base = base;
109 phys_regions[num_phys_regions].size = size;
110 num_phys_regions++;
111 }
112 unsigned long __init
113 txboard_find_free_phys_region(unsigned long begin, unsigned long end,
114 unsigned long size)
115 {
116 unsigned long base;
117 int i;
118
119 for (base = begin / size * size; base < end; base += size) {
120 for (i = 0; i < num_phys_regions; i++) {
121 if (phys_regions[i].size &&
122 base <= phys_regions[i].base + (phys_regions[i].size - 1) &&
123 base + (size - 1) >= phys_regions[i].base)
124 break;
125 }
126 if (i == num_phys_regions)
127 return base;
128 }
129 return 0;
130 }
131 unsigned long __init
132 txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end,
133 unsigned long *size)
134 {
135 unsigned long sz, base;
136 for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) {
137 base = txboard_find_free_phys_region(begin, end, sz);
138 if (base) {
139 *size = sz;
140 return base;
141 }
142 }
143 return 0;
144 }
145 unsigned long __init
146 txboard_request_phys_region_range(unsigned long begin, unsigned long end,
147 unsigned long size)
148 {
149 unsigned long base;
150 base = txboard_find_free_phys_region(begin, end, size);
151 if (base)
152 txboard_add_phys_region(base, size);
153 return base;
154 }
155 unsigned long __init
156 txboard_request_phys_region(unsigned long size)
157 {
158 unsigned long base;
159 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
160 base = txboard_find_free_phys_region(begin, end, size);
161 if (base)
162 txboard_add_phys_region(base, size);
163 return base;
164 }
165 unsigned long __init
166 txboard_request_phys_region_shrink(unsigned long *size)
167 {
168 unsigned long base;
169 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
170 base = txboard_find_free_phys_region_shrink(begin, end, size);
171 if (base)
172 txboard_add_phys_region(base, *size);
173 return base;
174 }
175
176 #ifdef CONFIG_PCI
177 void __init
178 tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr,
179 struct pci_controller *channel,
180 unsigned long pci_io_base,
181 int extarb)
182 {
183 int i;
184
185 /* Disable All Initiator Space */
186 pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)|
187 TX4938_PCIC_PCICCFG_G2PMEN(1)|
188 TX4938_PCIC_PCICCFG_G2PMEN(2)|
189 TX4938_PCIC_PCICCFG_G2PIOEN);
190
191 /* GB->PCI mappings */
192 pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4;
193 pcicptr->g2piogbase = pci_io_base |
194 #ifdef __BIG_ENDIAN
195 TX4938_PCIC_G2PIOGBASE_ECHG
196 #else
197 TX4938_PCIC_G2PIOGBASE_BSDIS
198 #endif
199 ;
200 pcicptr->g2piopbase = 0;
201 for (i = 0; i < 3; i++) {
202 pcicptr->g2pmmask[i] = 0;
203 pcicptr->g2pmgbase[i] = 0;
204 pcicptr->g2pmpbase[i] = 0;
205 }
206 if (channel->mem_resource->end) {
207 pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4;
208 pcicptr->g2pmgbase[0] = channel->mem_resource->start |
209 #ifdef __BIG_ENDIAN
210 TX4938_PCIC_G2PMnGBASE_ECHG
211 #else
212 TX4938_PCIC_G2PMnGBASE_BSDIS
213 #endif
214 ;
215 pcicptr->g2pmpbase[0] = channel->mem_resource->start;
216 }
217 /* PCI->GB mappings (I/O 256B) */
218 pcicptr->p2giopbase = 0; /* 256B */
219 pcicptr->p2giogbase = 0;
220 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
221 pcicptr->p2gm0plbase = 0;
222 pcicptr->p2gm0pubase = 0;
223 pcicptr->p2gmgbase[0] = 0 |
224 TX4938_PCIC_P2GMnGBASE_TMEMEN |
225 #ifdef __BIG_ENDIAN
226 TX4938_PCIC_P2GMnGBASE_TECHG
227 #else
228 TX4938_PCIC_P2GMnGBASE_TBSDIS
229 #endif
230 ;
231 /* PCI->GB mappings (MEM 16MB) */
232 pcicptr->p2gm1plbase = 0xffffffff;
233 pcicptr->p2gm1pubase = 0xffffffff;
234 pcicptr->p2gmgbase[1] = 0;
235 /* PCI->GB mappings (MEM 1MB) */
236 pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */
237 pcicptr->p2gmgbase[2] = 0;
238
239 pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK;
240 /* Enable Initiator Memory Space */
241 if (channel->mem_resource->end)
242 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0);
243 /* Enable Initiator I/O Space */
244 if (channel->io_resource->end)
245 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN;
246 /* Enable Initiator Config */
247 pcicptr->pciccfg |=
248 TX4938_PCIC_PCICCFG_ICAEN |
249 TX4938_PCIC_PCICCFG_TCAR;
250
251 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
252 pcicptr->pcicfg1 = 0;
253
254 pcicptr->g2ptocnt &= ~0xffff;
255
256 if (tx4938_pcic_trdyto >= 0) {
257 pcicptr->g2ptocnt &= ~0xff;
258 pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff);
259 }
260
261 if (tx4938_pcic_retryto >= 0) {
262 pcicptr->g2ptocnt &= ~0xff00;
263 pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00);
264 }
265
266 /* Clear All Local Bus Status */
267 pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL;
268 /* Enable All Local Bus Interrupts */
269 pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL;
270 /* Clear All Initiator Status */
271 pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL;
272 /* Enable All Initiator Interrupts */
273 pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL;
274 /* Clear All PCI Status Error */
275 pcicptr->pcistatus =
276 (pcicptr->pcistatus & 0x0000ffff) |
277 (TX4938_PCIC_PCISTATUS_ALL << 16);
278 /* Enable All PCI Status Error Interrupts */
279 pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL;
280
281 if (!extarb) {
282 /* Reset Bus Arbiter */
283 pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA;
284 pcicptr->pbabm = 0;
285 /* Enable Bus Arbiter */
286 pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN;
287 }
288
289 /* PCIC Int => IRC IRQ16 */
290 pcicptr->pcicfg2 =
291 (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC;
292
293 pcicptr->pcistatus = PCI_COMMAND_MASTER |
294 PCI_COMMAND_MEMORY |
295 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
296 }
297
298 int __init
299 tx4938_report_pciclk(void)
300 {
301 unsigned long pcode = TX4938_REV_PCODE();
302 int pciclk = 0;
303 printk("TX%lx PCIC --%s PCICLK:",
304 pcode,
305 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : "");
306 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
307
308 switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) {
309 case TX4938_CCFG_PCIDIVMODE_4:
310 pciclk = txx9_cpu_clock / 4; break;
311 case TX4938_CCFG_PCIDIVMODE_4_5:
312 pciclk = txx9_cpu_clock * 2 / 9; break;
313 case TX4938_CCFG_PCIDIVMODE_5:
314 pciclk = txx9_cpu_clock / 5; break;
315 case TX4938_CCFG_PCIDIVMODE_5_5:
316 pciclk = txx9_cpu_clock * 2 / 11; break;
317 case TX4938_CCFG_PCIDIVMODE_8:
318 pciclk = txx9_cpu_clock / 8; break;
319 case TX4938_CCFG_PCIDIVMODE_9:
320 pciclk = txx9_cpu_clock / 9; break;
321 case TX4938_CCFG_PCIDIVMODE_10:
322 pciclk = txx9_cpu_clock / 10; break;
323 case TX4938_CCFG_PCIDIVMODE_11:
324 pciclk = txx9_cpu_clock / 11; break;
325 }
326 printk("Internal(%dMHz)", pciclk / 1000000);
327 } else {
328 printk("External");
329 pciclk = -1;
330 }
331 printk("\n");
332 return pciclk;
333 }
334
335 void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr)
336 {
337 pcicptrs[ch] = pcicptr;
338 }
339
340 struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch)
341 {
342 return pcicptrs[ch];
343 }
344
345 static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
346 int top_bus, int busnr, int devfn)
347 {
348 static struct pci_dev dev;
349 static struct pci_bus bus;
350
351 dev.sysdata = (void *)hose;
352 dev.devfn = devfn;
353 bus.number = busnr;
354 bus.ops = hose->pci_ops;
355 bus.parent = NULL;
356 dev.bus = &bus;
357
358 return &dev;
359 }
360
361 #define EARLY_PCI_OP(rw, size, type) \
362 static int early_##rw##_config_##size(struct pci_controller *hose, \
363 int top_bus, int bus, int devfn, int offset, type value) \
364 { \
365 return pci_##rw##_config_##size( \
366 fake_pci_dev(hose, top_bus, bus, devfn), \
367 offset, value); \
368 }
369
370 EARLY_PCI_OP(read, word, u16 *)
371
372 int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus)
373 {
374 u32 pci_devfn;
375 unsigned short vid;
376 int devfn_start = 0;
377 int devfn_stop = 0xff;
378 int cap66 = -1;
379 u16 stat;
380
381 printk("PCI: Checking 66MHz capabilities...\n");
382
383 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
384 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
385 PCI_VENDOR_ID, &vid);
386
387 if (vid == 0xffff) continue;
388
389 /* check 66MHz capability */
390 if (cap66 < 0)
391 cap66 = 1;
392 if (cap66) {
393 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
394 PCI_STATUS, &stat);
395 if (!(stat & PCI_STATUS_66MHZ)) {
396 printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n",
397 current_bus, pci_devfn);
398 cap66 = 0;
399 break;
400 }
401 }
402 }
403 return cap66 > 0;
404 }
405
406 int __init
407 tx4938_pciclk66_setup(void)
408 {
409 int pciclk;
410
411 /* Assert M66EN */
412 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66;
413 /* Double PCICLK (if possible) */
414 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
415 unsigned int pcidivmode =
416 tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK;
417 switch (pcidivmode) {
418 case TX4938_CCFG_PCIDIVMODE_8:
419 case TX4938_CCFG_PCIDIVMODE_4:
420 pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
421 pciclk = txx9_cpu_clock / 4;
422 break;
423 case TX4938_CCFG_PCIDIVMODE_9:
424 case TX4938_CCFG_PCIDIVMODE_4_5:
425 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
426 pciclk = txx9_cpu_clock * 2 / 9;
427 break;
428 case TX4938_CCFG_PCIDIVMODE_10:
429 case TX4938_CCFG_PCIDIVMODE_5:
430 pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
431 pciclk = txx9_cpu_clock / 5;
432 break;
433 case TX4938_CCFG_PCIDIVMODE_11:
434 case TX4938_CCFG_PCIDIVMODE_5_5:
435 default:
436 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
437 pciclk = txx9_cpu_clock * 2 / 11;
438 break;
439 }
440 tx4938_ccfgptr->ccfg =
441 (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK)
442 | pcidivmode;
443 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
444 (unsigned long)tx4938_ccfgptr->ccfg);
445 } else {
446 pciclk = -1;
447 }
448 return pciclk;
449 }
450
451 extern struct pci_controller tx4938_pci_controller[];
452 static int __init tx4938_pcibios_init(void)
453 {
454 unsigned long mem_base[2];
455 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
456 unsigned long io_base[2];
457 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
458 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
459 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
460
461 PCIBIOS_MIN_IO = 0x00001000UL;
462 PCIBIOS_MIN_MEM = 0x01000000UL;
463
464 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
465 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
466
467 printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
468 (unsigned short)(tx4938_pcicptr->pciid >> 16),
469 (unsigned short)(tx4938_pcicptr->pciid & 0xffff),
470 (unsigned short)(tx4938_pcicptr->pciccrev & 0xff),
471 extarb ? "External" : "Internal");
472
473 /* setup PCI area */
474 tx4938_pci_controller[0].io_resource->start = io_base[0];
475 tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1;
476 tx4938_pci_controller[0].mem_resource->start = mem_base[0];
477 tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1;
478
479 set_tx4938_pcicptr(0, tx4938_pcicptr);
480
481 register_pci_controller(&tx4938_pci_controller[0]);
482
483 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) {
484 printk("TX4938_CCFG_PCI66 already configured\n");
485 txboard_pci66_mode = -1; /* already configured */
486 }
487
488 /* Reset PCI Bus */
489 *rbtx4938_pcireset_ptr = 0;
490 /* Reset PCIC */
491 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
492 if (txboard_pci66_mode > 0)
493 tx4938_pciclk66_setup();
494 mdelay(10);
495 /* clear PCIC reset */
496 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
497 *rbtx4938_pcireset_ptr = 1;
498 wbflush();
499 tx4938_report_pcic_status1(tx4938_pcicptr);
500
501 tx4938_report_pciclk();
502 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
503 if (txboard_pci66_mode == 0 &&
504 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) {
505 /* Reset PCI Bus */
506 *rbtx4938_pcireset_ptr = 0;
507 /* Reset PCIC */
508 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST;
509 tx4938_pciclk66_setup();
510 mdelay(10);
511 /* clear PCIC reset */
512 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST;
513 *rbtx4938_pcireset_ptr = 1;
514 wbflush();
515 /* Reinitialize PCIC */
516 tx4938_report_pciclk();
517 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb);
518 }
519
520 mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]);
521 io_base[1] = txboard_request_phys_region_shrink(&io_size[1]);
522 /* Reset PCIC1 */
523 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST;
524 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
525 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD))
526 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66;
527 else
528 tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66;
529 mdelay(10);
530 /* clear PCIC1 reset */
531 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
532 tx4938_report_pcic_status1(tx4938_pcic1ptr);
533
534 printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x",
535 (unsigned short)(tx4938_pcic1ptr->pciid >> 16),
536 (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff),
537 (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff));
538 printk("%s PCICLK:%dMHz\n",
539 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "",
540 txx9_gbus_clock /
541 ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) /
542 1000000);
543
544 /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */
545 tx4938_pci_controller[1].io_resource->start =
546 io_base[1] - io_base[0];
547 tx4938_pci_controller[1].io_resource->end =
548 io_base[1] - io_base[0] + io_size[1] - 1;
549 tx4938_pci_controller[1].mem_resource->start = mem_base[1];
550 tx4938_pci_controller[1].mem_resource->end =
551 mem_base[1] + mem_size[1] - 1;
552 set_tx4938_pcicptr(1, tx4938_pcic1ptr);
553
554 register_pci_controller(&tx4938_pci_controller[1]);
555
556 tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb);
557
558 /* map ioport 0 to PCI I/O space address 0 */
559 set_io_port_base(KSEG1 + io_base[0]);
560
561 return 0;
562 }
563
564 arch_initcall(tx4938_pcibios_init);
565
566 #endif /* CONFIG_PCI */
567
568 /* SPI support */
569
570 /* chip select for SPI devices */
571 #define SEEPROM1_CS 7 /* PIO7 */
572 #define SEEPROM2_CS 0 /* IOC */
573 #define SEEPROM3_CS 1 /* IOC */
574 #define SRTC_CS 2 /* IOC */
575
576 static int rbtx4938_spi_cs_func(int chipid, int on)
577 {
578 unsigned char bit;
579 switch (chipid) {
580 case RBTX4938_SEEPROM1_CHIPID:
581 if (on)
582 tx4938_pioptr->dout &= ~(1 << SEEPROM1_CS);
583 else
584 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
585 return 0;
586 break;
587 case RBTX4938_SEEPROM2_CHIPID:
588 bit = (1 << SEEPROM2_CS);
589 break;
590 case RBTX4938_SEEPROM3_CHIPID:
591 bit = (1 << SEEPROM3_CS);
592 break;
593 case RBTX4938_SRTC_CHIPID:
594 bit = (1 << SRTC_CS);
595 break;
596 default:
597 return -ENODEV;
598 }
599 /* bit1,2,4 are low active, bit3 is high active */
600 *rbtx4938_spics_ptr =
601 (*rbtx4938_spics_ptr & ~bit) |
602 ((on ? (bit ^ 0x0b) : ~(bit ^ 0x0b)) & bit);
603 return 0;
604 }
605
606 #ifdef CONFIG_PCI
607 extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
608
609 int rbtx4938_get_tx4938_ethaddr(struct pci_dev *dev, unsigned char *addr)
610 {
611 struct pci_controller *channel = (struct pci_controller *)dev->bus->sysdata;
612 static unsigned char dat[17];
613 static int read_dat = 0;
614 int ch = 0;
615
616 if (channel != &tx4938_pci_controller[1])
617 return -ENODEV;
618 /* TX4938 PCIC1 */
619 switch (PCI_SLOT(dev->devfn)) {
620 case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
621 ch = 0;
622 break;
623 case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
624 ch = 1;
625 break;
626 default:
627 return -ENODEV;
628 }
629 if (!read_dat) {
630 unsigned char sum;
631 int i;
632 read_dat = 1;
633 /* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
634 if (spi_eeprom_read(RBTX4938_SEEPROM1_CHIPID,
635 0, dat, sizeof(dat))) {
636 printk(KERN_ERR "seeprom: read error.\n");
637 } else {
638 if (strcmp(dat, "MAC") != 0)
639 printk(KERN_WARNING "seeprom: bad signature.\n");
640 for (i = 0, sum = 0; i < sizeof(dat); i++)
641 sum += dat[i];
642 if (sum)
643 printk(KERN_WARNING "seeprom: bad checksum.\n");
644 }
645 }
646 memcpy(addr, &dat[4 + 6 * ch], 6);
647 return 0;
648 }
649 #endif /* CONFIG_PCI */
650
651 extern void __init txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on));
652 static void __init rbtx4938_spi_setup(void)
653 {
654 /* set SPI_SEL */
655 tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL;
656 /* chip selects for SPI devices */
657 tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
658 tx4938_pioptr->dir |= (1 << SEEPROM1_CS);
659 txx9_spi_init(TX4938_SPI_REG, rbtx4938_spi_cs_func);
660 }
661
662 static struct resource rbtx4938_fpga_resource;
663
664 static char pcode_str[8];
665 static struct resource tx4938_reg_resource = {
666 .start = TX4938_REG_BASE,
667 .end = TX4938_REG_BASE + TX4938_REG_SIZE,
668 .name = pcode_str,
669 .flags = IORESOURCE_MEM
670 };
671
672 void __init tx4938_board_setup(void)
673 {
674 int i;
675 unsigned long divmode;
676 int cpuclk = 0;
677 unsigned long pcode = TX4938_REV_PCODE();
678
679 ioport_resource.start = 0x1000;
680 ioport_resource.end = 0xffffffff;
681 iomem_resource.start = 0x1000;
682 iomem_resource.end = 0xffffffff; /* expand to 4GB */
683
684 sprintf(pcode_str, "TX%lx", pcode);
685 /* SDRAMC,EBUSC are configured by PROM */
686 for (i = 0; i < 8; i++) {
687 if (!(tx4938_ebuscptr->cr[i] & 0x8))
688 continue; /* disabled */
689 rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i);
690 txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i));
691 }
692
693 /* clocks */
694 if (txx9_master_clock) {
695 /* calculate gbus_clock and cpu_clock from master_clock */
696 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
697 switch (divmode) {
698 case TX4938_CCFG_DIVMODE_8:
699 case TX4938_CCFG_DIVMODE_10:
700 case TX4938_CCFG_DIVMODE_12:
701 case TX4938_CCFG_DIVMODE_16:
702 case TX4938_CCFG_DIVMODE_18:
703 txx9_gbus_clock = txx9_master_clock * 4; break;
704 default:
705 txx9_gbus_clock = txx9_master_clock;
706 }
707 switch (divmode) {
708 case TX4938_CCFG_DIVMODE_2:
709 case TX4938_CCFG_DIVMODE_8:
710 cpuclk = txx9_gbus_clock * 2; break;
711 case TX4938_CCFG_DIVMODE_2_5:
712 case TX4938_CCFG_DIVMODE_10:
713 cpuclk = txx9_gbus_clock * 5 / 2; break;
714 case TX4938_CCFG_DIVMODE_3:
715 case TX4938_CCFG_DIVMODE_12:
716 cpuclk = txx9_gbus_clock * 3; break;
717 case TX4938_CCFG_DIVMODE_4:
718 case TX4938_CCFG_DIVMODE_16:
719 cpuclk = txx9_gbus_clock * 4; break;
720 case TX4938_CCFG_DIVMODE_4_5:
721 case TX4938_CCFG_DIVMODE_18:
722 cpuclk = txx9_gbus_clock * 9 / 2; break;
723 }
724 txx9_cpu_clock = cpuclk;
725 } else {
726 if (txx9_cpu_clock == 0) {
727 txx9_cpu_clock = 300000000; /* 300MHz */
728 }
729 /* calculate gbus_clock and master_clock from cpu_clock */
730 cpuclk = txx9_cpu_clock;
731 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK;
732 switch (divmode) {
733 case TX4938_CCFG_DIVMODE_2:
734 case TX4938_CCFG_DIVMODE_8:
735 txx9_gbus_clock = cpuclk / 2; break;
736 case TX4938_CCFG_DIVMODE_2_5:
737 case TX4938_CCFG_DIVMODE_10:
738 txx9_gbus_clock = cpuclk * 2 / 5; break;
739 case TX4938_CCFG_DIVMODE_3:
740 case TX4938_CCFG_DIVMODE_12:
741 txx9_gbus_clock = cpuclk / 3; break;
742 case TX4938_CCFG_DIVMODE_4:
743 case TX4938_CCFG_DIVMODE_16:
744 txx9_gbus_clock = cpuclk / 4; break;
745 case TX4938_CCFG_DIVMODE_4_5:
746 case TX4938_CCFG_DIVMODE_18:
747 txx9_gbus_clock = cpuclk * 2 / 9; break;
748 }
749 switch (divmode) {
750 case TX4938_CCFG_DIVMODE_8:
751 case TX4938_CCFG_DIVMODE_10:
752 case TX4938_CCFG_DIVMODE_12:
753 case TX4938_CCFG_DIVMODE_16:
754 case TX4938_CCFG_DIVMODE_18:
755 txx9_master_clock = txx9_gbus_clock / 4; break;
756 default:
757 txx9_master_clock = txx9_gbus_clock;
758 }
759 }
760 /* change default value to udelay/mdelay take reasonable time */
761 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
762
763 /* CCFG */
764 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
765 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW;
766 /* clear PCIC1 reset */
767 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST)
768 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
769
770 /* enable Timeout BusError */
771 if (tx4938_ccfg_toeon)
772 tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE;
773
774 /* DMA selection */
775 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL;
776
777 /* Use external clock for external arbiter */
778 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB))
779 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL;
780
781 printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n",
782 pcode_str,
783 cpuclk / 1000000, txx9_master_clock / 1000000,
784 (unsigned long)tx4938_ccfgptr->crir,
785 tx4938_ccfgptr->ccfg,
786 tx4938_ccfgptr->pcfg);
787
788 printk("%s SDRAMC --", pcode_str);
789 for (i = 0; i < 4; i++) {
790 unsigned long long cr = tx4938_sdramcptr->cr[i];
791 unsigned long ram_base, ram_size;
792 if (!((unsigned long)cr & 0x00000400))
793 continue; /* disabled */
794 ram_base = (unsigned long)(cr >> 49) << 21;
795 ram_size = ((unsigned long)(cr >> 33) + 1) << 21;
796 if (ram_base >= 0x20000000)
797 continue; /* high memory (ignore) */
798 printk(" CR%d:%016Lx", i, cr);
799 txboard_add_phys_region(ram_base, ram_size);
800 }
801 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
802
803 /* SRAM */
804 if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) {
805 unsigned int size = 0x800;
806 unsigned long base =
807 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
808 txboard_add_phys_region(base, size);
809 }
810
811 /* IRC */
812 /* disable interrupt control */
813 tx4938_ircptr->cer = 0;
814
815 /* TMR */
816 /* disable all timers */
817 for (i = 0; i < TX4938_NR_TMR; i++) {
818 tx4938_tmrptr(i)->tcr = 0x00000020;
819 tx4938_tmrptr(i)->tisr = 0;
820 tx4938_tmrptr(i)->cpra = 0xffffffff;
821 tx4938_tmrptr(i)->itmr = 0;
822 tx4938_tmrptr(i)->ccdr = 0;
823 tx4938_tmrptr(i)->pgmr = 0;
824 }
825
826 /* enable DMA */
827 TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
828 TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);
829
830 /* PIO */
831 tx4938_pioptr->maskcpu = 0;
832 tx4938_pioptr->maskext = 0;
833
834 /* TX4938 internal registers */
835 if (request_resource(&iomem_resource, &tx4938_reg_resource))
836 printk("request resource for internal registers failed\n");
837 }
838
839 #ifdef CONFIG_PCI
840 static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr)
841 {
842 unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16);
843 unsigned long g2pstatus = pcicptr->g2pstatus;
844 unsigned long pcicstatus = pcicptr->pcicstatus;
845 static struct {
846 unsigned long flag;
847 const char *str;
848 } pcistat_tbl[] = {
849 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
850 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
851 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
852 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
853 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
854 { PCI_STATUS_PARITY, "MasterParityError" },
855 }, g2pstat_tbl[] = {
856 { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" },
857 { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" },
858 }, pcicstat_tbl[] = {
859 { TX4938_PCIC_PCICSTATUS_PME, "PME" },
860 { TX4938_PCIC_PCICSTATUS_TLB, "TLB" },
861 { TX4938_PCIC_PCICSTATUS_NIB, "NIB" },
862 { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" },
863 { TX4938_PCIC_PCICSTATUS_PERR, "PERR" },
864 { TX4938_PCIC_PCICSTATUS_SERR, "SERR" },
865 { TX4938_PCIC_PCICSTATUS_GBE, "GBE" },
866 { TX4938_PCIC_PCICSTATUS_IWB, "IWB" },
867 };
868 int i;
869
870 printk("pcistat:%04x(", pcistatus);
871 for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
872 if (pcistatus & pcistat_tbl[i].flag)
873 printk("%s ", pcistat_tbl[i].str);
874 printk("), g2pstatus:%08lx(", g2pstatus);
875 for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
876 if (g2pstatus & g2pstat_tbl[i].flag)
877 printk("%s ", g2pstat_tbl[i].str);
878 printk("), pcicstatus:%08lx(", pcicstatus);
879 for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
880 if (pcicstatus & pcicstat_tbl[i].flag)
881 printk("%s ", pcicstat_tbl[i].str);
882 printk(")\n");
883 }
884
885 void tx4938_report_pcic_status(void)
886 {
887 int i;
888 struct tx4938_pcic_reg *pcicptr;
889 for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++)
890 tx4938_report_pcic_status1(pcicptr);
891 }
892
893 #endif /* CONFIG_PCI */
894
895 /* We use onchip r4k counter or TMR timer as our system wide timer
896 * interrupt running at 100HZ. */
897
898 extern void __init rtc_rx5c348_init(int chipid);
899 void __init rbtx4938_time_init(void)
900 {
901 rtc_rx5c348_init(RBTX4938_SRTC_CHIPID);
902 mips_hpt_frequency = txx9_cpu_clock / 2;
903 }
904
905 void __init toshiba_rbtx4938_setup(void)
906 {
907 unsigned long long pcfg;
908 char *argptr;
909
910 iomem_resource.end = 0xffffffff; /* 4GB */
911
912 if (txx9_master_clock == 0)
913 txx9_master_clock = 25000000; /* 25MHz */
914 tx4938_board_setup();
915 /* setup irq stuff */
916 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM0), 0x00000000); /* irq trigger */
917 TX4938_WR(TX4938_MKA(TX4938_IRC_IRDM1), 0x00000000); /* irq trigger */
918 /* setup serial stuff */
919 TX4938_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
920 TX4938_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
921
922 #ifndef CONFIG_PCI
923 set_io_port_base(RBTX4938_ETHER_BASE);
924 #endif
925
926 #ifdef CONFIG_SERIAL_TXX9
927 {
928 extern int early_serial_txx9_setup(struct uart_port *port);
929 int i;
930 struct uart_port req;
931 for(i = 0; i < 2; i++) {
932 memset(&req, 0, sizeof(req));
933 req.line = i;
934 req.iotype = UPIO_MEM;
935 req.membase = (char *)(0xff1ff300 + i * 0x100);
936 req.mapbase = 0xff1ff300 + i * 0x100;
937 req.irq = 32 + i;
938 req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
939 req.uartclk = 50000000;
940 early_serial_txx9_setup(&req);
941 }
942 }
943 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
944 argptr = prom_getcmdline();
945 if (strstr(argptr, "console=") == NULL) {
946 strcat(argptr, " console=ttyS0,38400");
947 }
948 #endif
949 #endif
950
951 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
952 printk("PIOSEL: disabling both ata and nand selection\n");
953 local_irq_disable();
954 tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
955 #endif
956
957 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
958 printk("PIOSEL: enabling nand selection\n");
959 tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL;
960 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL;
961 #endif
962
963 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
964 printk("PIOSEL: enabling ata selection\n");
965 tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL;
966 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL;
967 #endif
968
969 #ifdef CONFIG_IP_PNP
970 argptr = prom_getcmdline();
971 if (strstr(argptr, "ip=") == NULL) {
972 strcat(argptr, " ip=any");
973 }
974 #endif
975
976
977 #ifdef CONFIG_FB
978 {
979 conswitchp = &dummy_con;
980 }
981 #endif
982
983 rbtx4938_spi_setup();
984 pcfg = tx4938_ccfgptr->pcfg; /* updated */
985 /* fixup piosel */
986 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
987 TX4938_PCFG_ATA_SEL) {
988 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x04;
989 }
990 else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
991 TX4938_PCFG_NDF_SEL) {
992 *rbtx4938_piosel_ptr = (*rbtx4938_piosel_ptr & 0x03) | 0x08;
993 }
994 else {
995 *rbtx4938_piosel_ptr &= ~(0x08 | 0x04);
996 }
997
998 rbtx4938_fpga_resource.name = "FPGA Registers";
999 rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
1000 rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
1001 rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
1002 if (request_resource(&iomem_resource, &rbtx4938_fpga_resource))
1003 printk("request resource for fpga failed\n");
1004
1005 /* disable all OnBoard I/O interrupts */
1006 *rbtx4938_imask_ptr = 0;
1007
1008 _machine_restart = rbtx4938_machine_restart;
1009 _machine_halt = rbtx4938_machine_halt;
1010 pm_power_off = rbtx4938_machine_power_off;
1011
1012 *rbtx4938_led_ptr = 0xff;
1013 printk("RBTX4938 --- FPGA(Rev %02x)", *rbtx4938_fpga_rev_ptr);
1014 printk(" DIPSW:%02x,%02x\n",
1015 *rbtx4938_dipsw_ptr, *rbtx4938_bdipsw_ptr);
1016 }
1017
1018 #ifdef CONFIG_PROC_FS
1019 extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid);
1020 static int __init tx4938_spi_proc_setup(void)
1021 {
1022 struct proc_dir_entry *tx4938_spi_eeprom_dir;
1023
1024 tx4938_spi_eeprom_dir = proc_mkdir("spi_eeprom", 0);
1025
1026 if (!tx4938_spi_eeprom_dir)
1027 return -ENOMEM;
1028
1029 /* don't allow user access to RBTX4938_SEEPROM1_CHIPID
1030 * as it contains eth0 and eth1 MAC addresses
1031 */
1032 spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM2_CHIPID);
1033 spi_eeprom_proc_create(tx4938_spi_eeprom_dir, RBTX4938_SEEPROM3_CHIPID);
1034
1035 return 0;
1036 }
1037
1038 __initcall(tx4938_spi_proc_setup);
1039 #endif
hh.org GIT migration