arch/powerpc/platforms/86xx/mpc86xx_hpcn.c

   1 /*
   2  * MPC86xx HPCN board specific routines
   3  *
   4  * Recode: ZHANG WEI <wei.zhang@freescale.com>
   5  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   6  *
   7  * Copyright 2006 Freescale Semiconductor Inc.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 #include <linux/stddef.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/kdev_t.h>
  19 #include <linux/delay.h>
  20 #include <linux/seq_file.h>
  21 #include <linux/root_dev.h>
  22
  23 #include <asm/system.h>
  24 #include <asm/time.h>
  25 #include <asm/machdep.h>
  26 #include <asm/pci-bridge.h>
  27 #include <asm/mpc86xx.h>
  28 #include <asm/prom.h>
  29 #include <mm/mmu_decl.h>
  30 #include <asm/udbg.h>
  31 #include <asm/i8259.h>
  32
  33 #include <asm/mpic.h>
  34
  35 #include <sysdev/fsl_soc.h>
  36
  37 #include "mpc86xx.h"
  38 #include "mpc8641_hpcn.h"
  39
  40 #undef DEBUG
  41
  42 #ifdef DEBUG
  43 #define DBG(fmt...) do { printk(KERN_ERR fmt); } while(0)
  44 #else
  45 #define DBG(fmt...) do { } while(0)
  46 #endif
  47
  48 #ifndef CONFIG_PCI
  49 unsigned long isa_io_base = 0;
  50 unsigned long isa_mem_base = 0;
  51 unsigned long pci_dram_offset = 0;
  52 #endif
  53
  54
  55 #ifdef CONFIG_PCI
  56 static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
  57 {
  58         unsigned int cascade_irq = i8259_irq();
  59         if (cascade_irq != NO_IRQ)
  60                 generic_handle_irq(cascade_irq);
  61         desc->chip->eoi(irq);
  62 }
  63 #endif  /* CONFIG_PCI */
  64
  65 void __init
  66 mpc86xx_hpcn_init_irq(void)
  67 {
  68         struct mpic *mpic1;
  69         struct device_node *np;
  70         struct resource res;
  71 #ifdef CONFIG_PCI
  72         struct device_node *cascade_node = NULL;
  73         int cascade_irq;
  74 #endif
  75
  76         /* Determine PIC address. */
  77         np = of_find_node_by_type(NULL, "open-pic");
  78         if (np == NULL)
  79                 return;
  80         of_address_to_resource(np, 0, &res);
  81
  82         /* Alloc mpic structure and per isu has 16 INT entries. */
  83         mpic1 = mpic_alloc(np, res.start,
  84                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
  85                         16, NR_IRQS - 4,
  86                         " MPIC     ");
  87         BUG_ON(mpic1 == NULL);
  88
  89         mpic_assign_isu(mpic1, 0, res.start + 0x10000);
  90
  91         /* 48 Internal Interrupts */
  92         mpic_assign_isu(mpic1, 1, res.start + 0x10200);
  93         mpic_assign_isu(mpic1, 2, res.start + 0x10400);
  94         mpic_assign_isu(mpic1, 3, res.start + 0x10600);
  95
  96         /* 16 External interrupts
  97          * Moving them from [0 - 15] to [64 - 79]
  98          */
  99         mpic_assign_isu(mpic1, 4, res.start + 0x10000);
 100
 101         mpic_init(mpic1);
 102
 103 #ifdef CONFIG_PCI
 104         /* Initialize i8259 controller */
 105         for_each_node_by_type(np, "interrupt-controller")
 106                 if (device_is_compatible(np, "chrp,iic")) {
 107                         cascade_node = np;
 108                         break;
 109                 }
 110         if (cascade_node == NULL) {
 111                 printk(KERN_DEBUG "mpc86xxhpcn: no ISA interrupt controller\n");
 112                 return;
 113         }
 114
 115         cascade_irq = irq_of_parse_and_map(cascade_node, 0);
 116         if (cascade_irq == NO_IRQ) {
 117                 printk(KERN_ERR "mpc86xxhpcn: failed to map cascade interrupt");
 118                 return;
 119         }
 120         DBG("mpc86xxhpcn: cascade mapped to irq %d\n", cascade_irq);
 121
 122         i8259_init(cascade_node, 0);
 123         set_irq_chained_handler(cascade_irq, mpc86xx_8259_cascade);
 124 #endif
 125 }
 126
 127 #ifdef CONFIG_PCI
 128
 129 enum pirq{PIRQA = 8, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH};
 130 const unsigned char uli1575_irq_route_table[16] = {
 131         0,      /* 0: Reserved */
 132         0x8,    /* 1: 0b1000 */
 133         0,      /* 2: Reserved */
 134         0x2,    /* 3: 0b0010 */
 135         0x4,    /* 4: 0b0100 */
 136         0x5,    /* 5: 0b0101 */
 137         0x7,    /* 6: 0b0111 */
 138         0x6,    /* 7: 0b0110 */
 139         0,      /* 8: Reserved */
 140         0x1,    /* 9: 0b0001 */
 141         0x3,    /* 10: 0b0011 */
 142         0x9,    /* 11: 0b1001 */
 143         0xb,    /* 12: 0b1011 */
 144         0,      /* 13: Reserved */
 145         0xd,    /* 14, 0b1101 */
 146         0xf,    /* 15, 0b1111 */
 147 };
 148
 149 static int __devinit
 150 get_pci_irq_from_of(struct pci_controller *hose, int slot, int pin)
 151 {
 152         struct of_irq oirq;
 153         u32 laddr[3];
 154         struct device_node *hosenode = hose ? hose->arch_data : NULL;
 155
 156         if (!hosenode) return -EINVAL;
 157
 158         laddr[0] = (hose->first_busno << 16) | (PCI_DEVFN(slot, 0) << 8);
 159         laddr[1] = laddr[2] = 0;
 160         of_irq_map_raw(hosenode, &pin, 1, laddr, &oirq);
 161         DBG("mpc86xx_hpcn: pci irq addr %x, slot %d, pin %d, irq %d\n",
 162                         laddr[0], slot, pin, oirq.specifier[0]);
 163         return oirq.specifier[0];
 164 }
 165
 166 static void __devinit quirk_uli1575(struct pci_dev *dev)
 167 {
 168         unsigned short temp;
 169         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 170         unsigned char irq2pin[16];
 171         unsigned long pirq_map_word = 0;
 172         u32 irq;
 173         int i;
 174
 175         /*
 176          * ULI1575 interrupts route setup
 177          */
 178         memset(irq2pin, 0, 16); /* Initialize default value 0 */
 179
 180         /*
 181          * PIRQA -> PIRQD mapping read from OF-tree
 182          *
 183          * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
 184          *                PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
 185          */
 186         for (i = 0; i < 4; i++){
 187                 irq = get_pci_irq_from_of(hose, 17, i + 1);
 188                 if (irq > 0 && irq < 16)
 189                         irq2pin[irq] = PIRQA + i;
 190                 else
 191                         printk(KERN_WARNING "ULI1575 device"
 192                             "(slot %d, pin %d) irq %d is invalid.\n",
 193                             17, i, irq);
 194         }
 195
 196         /*
 197          * PIRQE -> PIRQF mapping set manually
 198          *
 199          * IRQ pin   IRQ#
 200          * PIRQE ---- 9
 201          * PIRQF ---- 10
 202          * PIRQG ---- 11
 203          * PIRQH ---- 12
 204          */
 205         for (i = 0; i < 4; i++) irq2pin[i + 9] = PIRQE + i;
 206
 207         /* Set IRQ-PIRQ Mapping to ULI1575 */
 208         for (i = 0; i < 16; i++)
 209                 if (irq2pin[i])
 210                         pirq_map_word |= (uli1575_irq_route_table[i] & 0xf)
 211                                 << ((irq2pin[i] - PIRQA) * 4);
 212
 213         /* ULI1575 IRQ mapping conf register default value is 0xb9317542 */
 214         DBG("Setup ULI1575 IRQ mapping configuration register value = 0x%x\n",
 215                         pirq_map_word);
 216         pci_write_config_dword(dev, 0x48, pirq_map_word);
 217
 218 #define ULI1575_SET_DEV_IRQ(slot, pin, reg)                             \
 219         do {                                                            \
 220                 int irq;                                                \
 221                 irq = get_pci_irq_from_of(hose, slot, pin);             \
 222                 if (irq > 0 && irq < 16)                                \
 223                         pci_write_config_byte(dev, reg, irq2pin[irq]);  \
 224                 else                                                    \
 225                         printk(KERN_WARNING "ULI1575 device"            \
 226                             "(slot %d, pin %d) irq %d is invalid.\n",   \
 227                             slot, pin, irq);                            \
 228         } while(0)
 229
 230         /* USB 1.1 OHCI controller 1, slot 28, pin 1 */
 231         ULI1575_SET_DEV_IRQ(28, 1, 0x86);
 232
 233         /* USB 1.1 OHCI controller 2, slot 28, pin 2 */
 234         ULI1575_SET_DEV_IRQ(28, 2, 0x87);
 235
 236         /* USB 1.1 OHCI controller 3, slot 28, pin 3 */
 237         ULI1575_SET_DEV_IRQ(28, 3, 0x88);
 238
 239         /* USB 2.0 controller, slot 28, pin 4 */
 240         irq = get_pci_irq_from_of(hose, 28, 4);
 241         if (irq >= 0 && irq <=15)
 242                 pci_write_config_dword(dev, 0x74, uli1575_irq_route_table[irq]);
 243
 244         /* Audio controller, slot 29, pin 1 */
 245         ULI1575_SET_DEV_IRQ(29, 1, 0x8a);
 246
 247         /* Modem controller, slot 29, pin 2 */
 248         ULI1575_SET_DEV_IRQ(29, 2, 0x8b);
 249
 250         /* HD audio controller, slot 29, pin 3 */
 251         ULI1575_SET_DEV_IRQ(29, 3, 0x8c);
 252
 253         /* SMB interrupt: slot 30, pin 1 */
 254         ULI1575_SET_DEV_IRQ(30, 1, 0x8e);
 255
 256         /* PMU ACPI SCI interrupt: slot 30, pin 2 */
 257         ULI1575_SET_DEV_IRQ(30, 2, 0x8f);
 258
 259         /* Serial ATA interrupt: slot 31, pin 1 */
 260         ULI1575_SET_DEV_IRQ(31, 1, 0x8d);
 261
 262         /* Primary PATA IDE IRQ: 14
 263          * Secondary PATA IDE IRQ: 15
 264          */
 265         pci_write_config_byte(dev, 0x44, 0x30 | uli1575_irq_route_table[14]);
 266         pci_write_config_byte(dev, 0x75, uli1575_irq_route_table[15]);
 267
 268         /* Set IRQ14 and IRQ15 to legacy IRQs */
 269         pci_read_config_word(dev, 0x46, &temp);
 270         temp |= 0xc000;
 271         pci_write_config_word(dev, 0x46, temp);
 272
 273         /* Set i8259 interrupt trigger
 274          * IRQ 3:  Level
 275          * IRQ 4:  Level
 276          * IRQ 5:  Level
 277          * IRQ 6:  Level
 278          * IRQ 7:  Level
 279          * IRQ 9:  Level
 280          * IRQ 10: Level
 281          * IRQ 11: Level
 282          * IRQ 12: Level
 283          * IRQ 14: Edge
 284          * IRQ 15: Edge
 285          */
 286         outb(0xfa, 0x4d0);
 287         outb(0x1e, 0x4d1);
 288
 289 #undef ULI1575_SET_DEV_IRQ
 290 }
 291
 292 static void __devinit quirk_uli5288(struct pci_dev *dev)
 293 {
 294         unsigned char c;
 295
 296         pci_read_config_byte(dev,0x83,&c);
 297         c |= 0x80;
 298         pci_write_config_byte(dev, 0x83, c);
 299
 300         pci_write_config_byte(dev, 0x09, 0x01);
 301         pci_write_config_byte(dev, 0x0a, 0x06);
 302
 303         pci_read_config_byte(dev,0x83,&c);
 304         c &= 0x7f;
 305         pci_write_config_byte(dev, 0x83, c);
 306
 307         pci_read_config_byte(dev,0x84,&c);
 308         c |= 0x01;
 309         pci_write_config_byte(dev, 0x84, c);
 310 }
 311
 312 static void __devinit quirk_uli5229(struct pci_dev *dev)
 313 {
 314         unsigned short temp;
 315         pci_write_config_word(dev, 0x04, 0x0405);
 316         pci_read_config_word(dev, 0x4a, &temp);
 317         temp |= 0x1000;
 318         pci_write_config_word(dev, 0x4a, temp);
 319 }
 320
 321 static void __devinit early_uli5249(struct pci_dev *dev)
 322 {
 323         unsigned char temp;
 324         pci_write_config_word(dev, 0x04, 0x0007);
 325         pci_read_config_byte(dev, 0x7c, &temp);
 326         pci_write_config_byte(dev, 0x7c, 0x80);
 327         pci_write_config_byte(dev, 0x09, 0x01);
 328         pci_write_config_byte(dev, 0x7c, temp);
 329         dev->class |= 0x1;
 330 }
 331
 332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_uli1575);
 333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
 334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
 335 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
 336 #endif /* CONFIG_PCI */
 337
 338
 339 static void __init
 340 mpc86xx_hpcn_setup_arch(void)
 341 {
 342         struct device_node *np;
 343
 344         if (ppc_md.progress)
 345                 ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
 346
 347         np = of_find_node_by_type(NULL, "cpu");
 348         if (np != 0) {
 349                 const unsigned int *fp;
 350
 351                 fp = get_property(np, "clock-frequency", NULL);
 352                 if (fp != 0)
 353                         loops_per_jiffy = *fp / HZ;
 354                 else
 355                         loops_per_jiffy = 50000000 / HZ;
 356                 of_node_put(np);
 357         }
 358
 359 #ifdef CONFIG_PCI
 360         for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
 361                 add_bridge(np);
 362
 363         ppc_md.pci_exclude_device = mpc86xx_exclude_device;
 364 #endif
 365
 366         printk("MPC86xx HPCN board from Freescale Semiconductor\n");
 367
 368 #ifdef  CONFIG_ROOT_NFS
 369         ROOT_DEV = Root_NFS;
 370 #else
 371         ROOT_DEV = Root_HDA1;
 372 #endif
 373
 374 #ifdef CONFIG_SMP
 375         mpc86xx_smp_init();
 376 #endif
 377 }
 378
 379
 380 void
 381 mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
 382 {
 383         struct device_node *root;
 384         uint memsize = total_memory;
 385         const char *model = "";
 386         uint svid = mfspr(SPRN_SVR);
 387
 388         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 389
 390         root = of_find_node_by_path("/");
 391         if (root)
 392                 model = get_property(root, "model", NULL);
 393         seq_printf(m, "Machine\t\t: %s\n", model);
 394         of_node_put(root);
 395
 396         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 397         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 398 }
 399
 400
 401 void __init mpc86xx_hpcn_pcibios_fixup(void)
 402 {
 403         struct pci_dev *dev = NULL;
 404
 405         for_each_pci_dev(dev)
 406                 pci_read_irq_line(dev);
 407 }
 408
 409
 410 /*
 411  * Called very early, device-tree isn't unflattened
 412  */
 413 static int __init mpc86xx_hpcn_probe(void)
 414 {
 415         unsigned long root = of_get_flat_dt_root();
 416
 417         if (of_flat_dt_is_compatible(root, "mpc86xx"))
 418                 return 1;       /* Looks good */
 419
 420         return 0;
 421 }
 422
 423
 424 void
 425 mpc86xx_restart(char *cmd)
 426 {
 427         void __iomem *rstcr;
 428
 429         rstcr = ioremap(get_immrbase() + MPC86XX_RSTCR_OFFSET, 0x100);
 430
 431         local_irq_disable();
 432
 433         /* Assert reset request to Reset Control Register */
 434         out_be32(rstcr, 0x2);
 435
 436         /* not reached */
 437 }
 438
 439
 440 long __init
 441 mpc86xx_time_init(void)
 442 {
 443         unsigned int temp;
 444
 445         /* Set the time base to zero */
 446         mtspr(SPRN_TBWL, 0);
 447         mtspr(SPRN_TBWU, 0);
 448
 449         temp = mfspr(SPRN_HID0);
 450         temp |= HID0_TBEN;
 451         mtspr(SPRN_HID0, temp);
 452         asm volatile("isync");
 453
 454         return 0;
 455 }
 456
 457
 458 define_machine(mpc86xx_hpcn) {
 459         .name                   = "MPC86xx HPCN",
 460         .probe                  = mpc86xx_hpcn_probe,
 461         .setup_arch             = mpc86xx_hpcn_setup_arch,
 462         .init_IRQ               = mpc86xx_hpcn_init_irq,
 463         .show_cpuinfo           = mpc86xx_hpcn_show_cpuinfo,
 464         .pcibios_fixup          = mpc86xx_hpcn_pcibios_fixup,
 465         .get_irq                = mpic_get_irq,
 466         .restart                = mpc86xx_restart,
 467         .time_init              = mpc86xx_time_init,
 468         .calibrate_decr         = generic_calibrate_decr,
 469         .progress               = udbg_progress,
 470 };